linux/sound/soc/fsl/fsl_micfil.c
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   1// SPDX-License-Identifier: GPL-2.0
   2// Copyright 2018 NXP
   3
   4#include <linux/clk.h>
   5#include <linux/device.h>
   6#include <linux/interrupt.h>
   7#include <linux/kobject.h>
   8#include <linux/kernel.h>
   9#include <linux/module.h>
  10#include <linux/of.h>
  11#include <linux/of_address.h>
  12#include <linux/of_irq.h>
  13#include <linux/of_platform.h>
  14#include <linux/pm_runtime.h>
  15#include <linux/regmap.h>
  16#include <linux/sysfs.h>
  17#include <linux/types.h>
  18#include <sound/dmaengine_pcm.h>
  19#include <sound/pcm.h>
  20#include <sound/soc.h>
  21#include <sound/tlv.h>
  22#include <sound/core.h>
  23
  24#include "fsl_micfil.h"
  25#include "imx-pcm.h"
  26
  27#define FSL_MICFIL_RATES                SNDRV_PCM_RATE_8000_48000
  28#define FSL_MICFIL_FORMATS              (SNDRV_PCM_FMTBIT_S16_LE)
  29
  30struct fsl_micfil {
  31        struct platform_device *pdev;
  32        struct regmap *regmap;
  33        const struct fsl_micfil_soc_data *soc;
  34        struct clk *busclk;
  35        struct clk *mclk;
  36        struct snd_dmaengine_dai_dma_data dma_params_rx;
  37        unsigned int dataline;
  38        char name[32];
  39        int irq[MICFIL_IRQ_LINES];
  40        unsigned int mclk_streams;
  41        int quality;    /*QUALITY 2-0 bits */
  42        bool slave_mode;
  43        int channel_gain[8];
  44};
  45
  46struct fsl_micfil_soc_data {
  47        unsigned int fifos;
  48        unsigned int fifo_depth;
  49        unsigned int dataline;
  50        bool imx;
  51};
  52
  53static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
  54        .imx = true,
  55        .fifos = 8,
  56        .fifo_depth = 8,
  57        .dataline =  0xf,
  58};
  59
  60static const struct of_device_id fsl_micfil_dt_ids[] = {
  61        { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
  62        {}
  63};
  64MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
  65
  66/* Table 5. Quality Modes
  67 * Medium       0 0 0
  68 * High         0 0 1
  69 * Very Low 2   1 0 0
  70 * Very Low 1   1 0 1
  71 * Very Low 0   1 1 0
  72 * Low          1 1 1
  73 */
  74static const char * const micfil_quality_select_texts[] = {
  75        "Medium", "High",
  76        "N/A", "N/A",
  77        "VLow2", "VLow1",
  78        "VLow0", "Low",
  79};
  80
  81static const struct soc_enum fsl_micfil_quality_enum =
  82        SOC_ENUM_SINGLE(REG_MICFIL_CTRL2,
  83                        MICFIL_CTRL2_QSEL_SHIFT,
  84                        ARRAY_SIZE(micfil_quality_select_texts),
  85                        micfil_quality_select_texts);
  86
  87static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
  88
  89static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
  90        SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
  91                          MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv),
  92        SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
  93                          MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0x7, gain_tlv),
  94        SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
  95                          MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0x7, gain_tlv),
  96        SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
  97                          MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0x7, gain_tlv),
  98        SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
  99                          MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0x7, gain_tlv),
 100        SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
 101                          MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0x7, gain_tlv),
 102        SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
 103                          MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0x7, gain_tlv),
 104        SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
 105                          MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv),
 106        SOC_ENUM_EXT("MICFIL Quality Select",
 107                     fsl_micfil_quality_enum,
 108                     snd_soc_get_enum_double, snd_soc_put_enum_double),
 109};
 110
 111static inline int get_pdm_clk(struct fsl_micfil *micfil,
 112                              unsigned int rate)
 113{
 114        u32 ctrl2_reg;
 115        int qsel, osr;
 116        int bclk;
 117
 118        regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
 119        osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
 120                    >> MICFIL_CTRL2_CICOSR_SHIFT);
 121
 122        regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
 123        qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
 124
 125        switch (qsel) {
 126        case MICFIL_HIGH_QUALITY:
 127                bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
 128                break;
 129        case MICFIL_MEDIUM_QUALITY:
 130        case MICFIL_VLOW0_QUALITY:
 131                bclk = rate * 4 * osr * 1; /* kfactor = 1 */
 132                break;
 133        case MICFIL_LOW_QUALITY:
 134        case MICFIL_VLOW1_QUALITY:
 135                bclk = rate * 2 * osr * 2; /* kfactor = 2 */
 136                break;
 137        case MICFIL_VLOW2_QUALITY:
 138                bclk = rate * osr * 4; /* kfactor = 4 */
 139                break;
 140        default:
 141                dev_err(&micfil->pdev->dev,
 142                        "Please make sure you select a valid quality.\n");
 143                bclk = -1;
 144                break;
 145        }
 146
 147        return bclk;
 148}
 149
 150static inline int get_clk_div(struct fsl_micfil *micfil,
 151                              unsigned int rate)
 152{
 153        u32 ctrl2_reg;
 154        long mclk_rate;
 155        int clk_div;
 156
 157        regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
 158
 159        mclk_rate = clk_get_rate(micfil->mclk);
 160
 161        clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
 162
 163        return clk_div;
 164}
 165
 166/* The SRES is a self-negated bit which provides the CPU with the
 167 * capability to initialize the PDM Interface module through the
 168 * slave-bus interface. This bit always reads as zero, and this
 169 * bit is only effective when MDIS is cleared
 170 */
 171static int fsl_micfil_reset(struct device *dev)
 172{
 173        struct fsl_micfil *micfil = dev_get_drvdata(dev);
 174        int ret;
 175
 176        ret = regmap_update_bits(micfil->regmap,
 177                                 REG_MICFIL_CTRL1,
 178                                 MICFIL_CTRL1_MDIS_MASK,
 179                                 0);
 180        if (ret) {
 181                dev_err(dev, "failed to clear MDIS bit %d\n", ret);
 182                return ret;
 183        }
 184
 185        ret = regmap_update_bits(micfil->regmap,
 186                                 REG_MICFIL_CTRL1,
 187                                 MICFIL_CTRL1_SRES_MASK,
 188                                 MICFIL_CTRL1_SRES);
 189        if (ret) {
 190                dev_err(dev, "failed to reset MICFIL: %d\n", ret);
 191                return ret;
 192        }
 193
 194        return 0;
 195}
 196
 197static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
 198                                    unsigned int freq)
 199{
 200        struct device *dev = &micfil->pdev->dev;
 201        int ret;
 202
 203        clk_disable_unprepare(micfil->mclk);
 204
 205        ret = clk_set_rate(micfil->mclk, freq * 1024);
 206        if (ret)
 207                dev_warn(dev, "failed to set rate (%u): %d\n",
 208                         freq * 1024, ret);
 209
 210        clk_prepare_enable(micfil->mclk);
 211
 212        return ret;
 213}
 214
 215static int fsl_micfil_startup(struct snd_pcm_substream *substream,
 216                              struct snd_soc_dai *dai)
 217{
 218        struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
 219
 220        if (!micfil) {
 221                dev_err(dai->dev, "micfil dai priv_data not set\n");
 222                return -EINVAL;
 223        }
 224
 225        return 0;
 226}
 227
 228static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
 229                              struct snd_soc_dai *dai)
 230{
 231        struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
 232        struct device *dev = &micfil->pdev->dev;
 233        int ret;
 234
 235        switch (cmd) {
 236        case SNDRV_PCM_TRIGGER_START:
 237        case SNDRV_PCM_TRIGGER_RESUME:
 238        case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 239                ret = fsl_micfil_reset(dev);
 240                if (ret) {
 241                        dev_err(dev, "failed to soft reset\n");
 242                        return ret;
 243                }
 244
 245                /* DMA Interrupt Selection - DISEL bits
 246                 * 00 - DMA and IRQ disabled
 247                 * 01 - DMA req enabled
 248                 * 10 - IRQ enabled
 249                 * 11 - reserved
 250                 */
 251                ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
 252                                         MICFIL_CTRL1_DISEL_MASK,
 253                                         (1 << MICFIL_CTRL1_DISEL_SHIFT));
 254                if (ret) {
 255                        dev_err(dev, "failed to update DISEL bits\n");
 256                        return ret;
 257                }
 258
 259                /* Enable the module */
 260                ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
 261                                         MICFIL_CTRL1_PDMIEN_MASK,
 262                                         MICFIL_CTRL1_PDMIEN);
 263                if (ret) {
 264                        dev_err(dev, "failed to enable the module\n");
 265                        return ret;
 266                }
 267
 268                break;
 269        case SNDRV_PCM_TRIGGER_STOP:
 270        case SNDRV_PCM_TRIGGER_SUSPEND:
 271        case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 272                /* Disable the module */
 273                ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
 274                                         MICFIL_CTRL1_PDMIEN_MASK,
 275                                         0);
 276                if (ret) {
 277                        dev_err(dev, "failed to enable the module\n");
 278                        return ret;
 279                }
 280
 281                ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
 282                                         MICFIL_CTRL1_DISEL_MASK,
 283                                         (0 << MICFIL_CTRL1_DISEL_SHIFT));
 284                if (ret) {
 285                        dev_err(dev, "failed to update DISEL bits\n");
 286                        return ret;
 287                }
 288                break;
 289        default:
 290                return -EINVAL;
 291        }
 292        return 0;
 293}
 294
 295static int fsl_set_clock_params(struct device *dev, unsigned int rate)
 296{
 297        struct fsl_micfil *micfil = dev_get_drvdata(dev);
 298        int clk_div;
 299        int ret;
 300
 301        ret = fsl_micfil_set_mclk_rate(micfil, rate);
 302        if (ret < 0)
 303                dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
 304                        clk_get_rate(micfil->mclk), rate);
 305
 306        /* set CICOSR */
 307        ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
 308                                 MICFIL_CTRL2_CICOSR_MASK,
 309                                 MICFIL_CTRL2_OSR_DEFAULT);
 310        if (ret)
 311                dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
 312                        REG_MICFIL_CTRL2);
 313
 314        /* set CLK_DIV */
 315        clk_div = get_clk_div(micfil, rate);
 316        if (clk_div < 0)
 317                ret = -EINVAL;
 318
 319        ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
 320                                 MICFIL_CTRL2_CLKDIV_MASK, clk_div);
 321        if (ret)
 322                dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
 323                        REG_MICFIL_CTRL2);
 324
 325        return ret;
 326}
 327
 328static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
 329                                struct snd_pcm_hw_params *params,
 330                                struct snd_soc_dai *dai)
 331{
 332        struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
 333        unsigned int channels = params_channels(params);
 334        unsigned int rate = params_rate(params);
 335        struct device *dev = &micfil->pdev->dev;
 336        int ret;
 337
 338        /* 1. Disable the module */
 339        ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
 340                                 MICFIL_CTRL1_PDMIEN_MASK, 0);
 341        if (ret) {
 342                dev_err(dev, "failed to disable the module\n");
 343                return ret;
 344        }
 345
 346        /* enable channels */
 347        ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
 348                                 0xFF, ((1 << channels) - 1));
 349        if (ret) {
 350                dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret,
 351                        REG_MICFIL_CTRL1);
 352                return ret;
 353        }
 354
 355        ret = fsl_set_clock_params(dev, rate);
 356        if (ret < 0) {
 357                dev_err(dev, "Failed to set clock parameters [%d]\n", ret);
 358                return ret;
 359        }
 360
 361        micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
 362
 363        return 0;
 364}
 365
 366static int fsl_micfil_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
 367                                     unsigned int freq, int dir)
 368{
 369        struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
 370        struct device *dev = &micfil->pdev->dev;
 371
 372        int ret;
 373
 374        if (!freq)
 375                return 0;
 376
 377        ret = fsl_micfil_set_mclk_rate(micfil, freq);
 378        if (ret < 0)
 379                dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
 380                        clk_get_rate(micfil->mclk), freq);
 381
 382        return ret;
 383}
 384
 385static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
 386        .startup = fsl_micfil_startup,
 387        .trigger = fsl_micfil_trigger,
 388        .hw_params = fsl_micfil_hw_params,
 389        .set_sysclk = fsl_micfil_set_dai_sysclk,
 390};
 391
 392static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
 393{
 394        struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
 395        struct device *dev = cpu_dai->dev;
 396        unsigned int val;
 397        int ret;
 398        int i;
 399
 400        /* set qsel to medium */
 401        ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
 402                                 MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY);
 403        if (ret) {
 404                dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
 405                        REG_MICFIL_CTRL2);
 406                return ret;
 407        }
 408
 409        /* set default gain to max_gain */
 410        regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
 411        for (i = 0; i < 8; i++)
 412                micfil->channel_gain[i] = 0xF;
 413
 414        snd_soc_dai_init_dma_data(cpu_dai, NULL,
 415                                  &micfil->dma_params_rx);
 416
 417        /* FIFO Watermark Control - FIFOWMK*/
 418        val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1;
 419        ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
 420                                 MICFIL_FIFO_CTRL_FIFOWMK_MASK,
 421                                 val);
 422        if (ret) {
 423                dev_err(dev, "failed to set FIFOWMK\n");
 424                return ret;
 425        }
 426
 427        return 0;
 428}
 429
 430static struct snd_soc_dai_driver fsl_micfil_dai = {
 431        .probe = fsl_micfil_dai_probe,
 432        .capture = {
 433                .stream_name = "CPU-Capture",
 434                .channels_min = 1,
 435                .channels_max = 8,
 436                .rates = FSL_MICFIL_RATES,
 437                .formats = FSL_MICFIL_FORMATS,
 438        },
 439        .ops = &fsl_micfil_dai_ops,
 440};
 441
 442static const struct snd_soc_component_driver fsl_micfil_component = {
 443        .name           = "fsl-micfil-dai",
 444        .controls       = fsl_micfil_snd_controls,
 445        .num_controls   = ARRAY_SIZE(fsl_micfil_snd_controls),
 446
 447};
 448
 449/* REGMAP */
 450static const struct reg_default fsl_micfil_reg_defaults[] = {
 451        {REG_MICFIL_CTRL1,              0x00000000},
 452        {REG_MICFIL_CTRL2,              0x00000000},
 453        {REG_MICFIL_STAT,               0x00000000},
 454        {REG_MICFIL_FIFO_CTRL,          0x00000007},
 455        {REG_MICFIL_FIFO_STAT,          0x00000000},
 456        {REG_MICFIL_DATACH0,            0x00000000},
 457        {REG_MICFIL_DATACH1,            0x00000000},
 458        {REG_MICFIL_DATACH2,            0x00000000},
 459        {REG_MICFIL_DATACH3,            0x00000000},
 460        {REG_MICFIL_DATACH4,            0x00000000},
 461        {REG_MICFIL_DATACH5,            0x00000000},
 462        {REG_MICFIL_DATACH6,            0x00000000},
 463        {REG_MICFIL_DATACH7,            0x00000000},
 464        {REG_MICFIL_DC_CTRL,            0x00000000},
 465        {REG_MICFIL_OUT_CTRL,           0x00000000},
 466        {REG_MICFIL_OUT_STAT,           0x00000000},
 467        {REG_MICFIL_VAD0_CTRL1,         0x00000000},
 468        {REG_MICFIL_VAD0_CTRL2,         0x000A0000},
 469        {REG_MICFIL_VAD0_STAT,          0x00000000},
 470        {REG_MICFIL_VAD0_SCONFIG,       0x00000000},
 471        {REG_MICFIL_VAD0_NCONFIG,       0x80000000},
 472        {REG_MICFIL_VAD0_NDATA,         0x00000000},
 473        {REG_MICFIL_VAD0_ZCD,           0x00000004},
 474};
 475
 476static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
 477{
 478        switch (reg) {
 479        case REG_MICFIL_CTRL1:
 480        case REG_MICFIL_CTRL2:
 481        case REG_MICFIL_STAT:
 482        case REG_MICFIL_FIFO_CTRL:
 483        case REG_MICFIL_FIFO_STAT:
 484        case REG_MICFIL_DATACH0:
 485        case REG_MICFIL_DATACH1:
 486        case REG_MICFIL_DATACH2:
 487        case REG_MICFIL_DATACH3:
 488        case REG_MICFIL_DATACH4:
 489        case REG_MICFIL_DATACH5:
 490        case REG_MICFIL_DATACH6:
 491        case REG_MICFIL_DATACH7:
 492        case REG_MICFIL_DC_CTRL:
 493        case REG_MICFIL_OUT_CTRL:
 494        case REG_MICFIL_OUT_STAT:
 495        case REG_MICFIL_VAD0_CTRL1:
 496        case REG_MICFIL_VAD0_CTRL2:
 497        case REG_MICFIL_VAD0_STAT:
 498        case REG_MICFIL_VAD0_SCONFIG:
 499        case REG_MICFIL_VAD0_NCONFIG:
 500        case REG_MICFIL_VAD0_NDATA:
 501        case REG_MICFIL_VAD0_ZCD:
 502                return true;
 503        default:
 504                return false;
 505        }
 506}
 507
 508static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
 509{
 510        switch (reg) {
 511        case REG_MICFIL_CTRL1:
 512        case REG_MICFIL_CTRL2:
 513        case REG_MICFIL_STAT:           /* Write 1 to Clear */
 514        case REG_MICFIL_FIFO_CTRL:
 515        case REG_MICFIL_FIFO_STAT:      /* Write 1 to Clear */
 516        case REG_MICFIL_DC_CTRL:
 517        case REG_MICFIL_OUT_CTRL:
 518        case REG_MICFIL_OUT_STAT:       /* Write 1 to Clear */
 519        case REG_MICFIL_VAD0_CTRL1:
 520        case REG_MICFIL_VAD0_CTRL2:
 521        case REG_MICFIL_VAD0_STAT:      /* Write 1 to Clear */
 522        case REG_MICFIL_VAD0_SCONFIG:
 523        case REG_MICFIL_VAD0_NCONFIG:
 524        case REG_MICFIL_VAD0_ZCD:
 525                return true;
 526        default:
 527                return false;
 528        }
 529}
 530
 531static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
 532{
 533        switch (reg) {
 534        case REG_MICFIL_STAT:
 535        case REG_MICFIL_DATACH0:
 536        case REG_MICFIL_DATACH1:
 537        case REG_MICFIL_DATACH2:
 538        case REG_MICFIL_DATACH3:
 539        case REG_MICFIL_DATACH4:
 540        case REG_MICFIL_DATACH5:
 541        case REG_MICFIL_DATACH6:
 542        case REG_MICFIL_DATACH7:
 543        case REG_MICFIL_VAD0_STAT:
 544        case REG_MICFIL_VAD0_NDATA:
 545                return true;
 546        default:
 547                return false;
 548        }
 549}
 550
 551static const struct regmap_config fsl_micfil_regmap_config = {
 552        .reg_bits = 32,
 553        .reg_stride = 4,
 554        .val_bits = 32,
 555
 556        .max_register = REG_MICFIL_VAD0_ZCD,
 557        .reg_defaults = fsl_micfil_reg_defaults,
 558        .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
 559        .readable_reg = fsl_micfil_readable_reg,
 560        .volatile_reg = fsl_micfil_volatile_reg,
 561        .writeable_reg = fsl_micfil_writeable_reg,
 562        .cache_type = REGCACHE_RBTREE,
 563};
 564
 565/* END OF REGMAP */
 566
 567static irqreturn_t micfil_isr(int irq, void *devid)
 568{
 569        struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
 570        struct platform_device *pdev = micfil->pdev;
 571        u32 stat_reg;
 572        u32 fifo_stat_reg;
 573        u32 ctrl1_reg;
 574        bool dma_enabled;
 575        int i;
 576
 577        regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
 578        regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
 579        regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
 580
 581        dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg);
 582
 583        /* Channel 0-7 Output Data Flags */
 584        for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
 585                if (stat_reg & MICFIL_STAT_CHXF_MASK(i))
 586                        dev_dbg(&pdev->dev,
 587                                "Data available in Data Channel %d\n", i);
 588                /* if DMA is not enabled, field must be written with 1
 589                 * to clear
 590                 */
 591                if (!dma_enabled)
 592                        regmap_write_bits(micfil->regmap,
 593                                          REG_MICFIL_STAT,
 594                                          MICFIL_STAT_CHXF_MASK(i),
 595                                          1);
 596        }
 597
 598        for (i = 0; i < MICFIL_FIFO_NUM; i++) {
 599                if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER_MASK(i))
 600                        dev_dbg(&pdev->dev,
 601                                "FIFO Overflow Exception flag for channel %d\n",
 602                                i);
 603
 604                if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(i))
 605                        dev_dbg(&pdev->dev,
 606                                "FIFO Underflow Exception flag for channel %d\n",
 607                                i);
 608        }
 609
 610        return IRQ_HANDLED;
 611}
 612
 613static irqreturn_t micfil_err_isr(int irq, void *devid)
 614{
 615        struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
 616        struct platform_device *pdev = micfil->pdev;
 617        u32 stat_reg;
 618
 619        regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
 620
 621        if (stat_reg & MICFIL_STAT_BSY_FIL_MASK)
 622                dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
 623
 624        if (stat_reg & MICFIL_STAT_FIR_RDY_MASK)
 625                dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
 626
 627        if (stat_reg & MICFIL_STAT_LOWFREQF_MASK) {
 628                dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
 629                regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
 630                                  MICFIL_STAT_LOWFREQF_MASK, 1);
 631        }
 632
 633        return IRQ_HANDLED;
 634}
 635
 636static int fsl_micfil_probe(struct platform_device *pdev)
 637{
 638        struct device_node *np = pdev->dev.of_node;
 639        struct fsl_micfil *micfil;
 640        struct resource *res;
 641        void __iomem *regs;
 642        int ret, i;
 643        unsigned long irqflag = 0;
 644
 645        micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
 646        if (!micfil)
 647                return -ENOMEM;
 648
 649        micfil->pdev = pdev;
 650        strncpy(micfil->name, np->name, sizeof(micfil->name) - 1);
 651
 652        micfil->soc = of_device_get_match_data(&pdev->dev);
 653
 654        /* ipg_clk is used to control the registers
 655         * ipg_clk_app is used to operate the filter
 656         */
 657        micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
 658        if (IS_ERR(micfil->mclk)) {
 659                dev_err(&pdev->dev, "failed to get core clock: %ld\n",
 660                        PTR_ERR(micfil->mclk));
 661                return PTR_ERR(micfil->mclk);
 662        }
 663
 664        micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");
 665        if (IS_ERR(micfil->busclk)) {
 666                dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",
 667                        PTR_ERR(micfil->busclk));
 668                return PTR_ERR(micfil->busclk);
 669        }
 670
 671        /* init regmap */
 672        regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 673        if (IS_ERR(regs))
 674                return PTR_ERR(regs);
 675
 676        micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
 677                                               regs,
 678                                               &fsl_micfil_regmap_config);
 679        if (IS_ERR(micfil->regmap)) {
 680                dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
 681                        PTR_ERR(micfil->regmap));
 682                return PTR_ERR(micfil->regmap);
 683        }
 684
 685        /* dataline mask for RX */
 686        ret = of_property_read_u32_index(np,
 687                                         "fsl,dataline",
 688                                         0,
 689                                         &micfil->dataline);
 690        if (ret)
 691                micfil->dataline = 1;
 692
 693        if (micfil->dataline & ~micfil->soc->dataline) {
 694                dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
 695                        micfil->soc->dataline);
 696                return -EINVAL;
 697        }
 698
 699        /* get IRQs */
 700        for (i = 0; i < MICFIL_IRQ_LINES; i++) {
 701                micfil->irq[i] = platform_get_irq(pdev, i);
 702                dev_err(&pdev->dev, "GET IRQ: %d\n", micfil->irq[i]);
 703                if (micfil->irq[i] < 0)
 704                        return micfil->irq[i];
 705        }
 706
 707        if (of_property_read_bool(np, "fsl,shared-interrupt"))
 708                irqflag = IRQF_SHARED;
 709
 710        /* Digital Microphone interface interrupt */
 711        ret = devm_request_irq(&pdev->dev, micfil->irq[0],
 712                               micfil_isr, irqflag,
 713                               micfil->name, micfil);
 714        if (ret) {
 715                dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
 716                        micfil->irq[0]);
 717                return ret;
 718        }
 719
 720        /* Digital Microphone interface error interrupt */
 721        ret = devm_request_irq(&pdev->dev, micfil->irq[1],
 722                               micfil_err_isr, irqflag,
 723                               micfil->name, micfil);
 724        if (ret) {
 725                dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
 726                        micfil->irq[1]);
 727                return ret;
 728        }
 729
 730        micfil->dma_params_rx.chan_name = "rx";
 731        micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
 732        micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
 733
 734
 735        platform_set_drvdata(pdev, micfil);
 736
 737        pm_runtime_enable(&pdev->dev);
 738        regcache_cache_only(micfil->regmap, true);
 739
 740        /*
 741         * Register platform component before registering cpu dai for there
 742         * is not defer probe for platform component in snd_soc_add_pcm_runtime().
 743         */
 744        ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 745        if (ret) {
 746                dev_err(&pdev->dev, "failed to pcm register\n");
 747                return ret;
 748        }
 749
 750        ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
 751                                              &fsl_micfil_dai, 1);
 752        if (ret) {
 753                dev_err(&pdev->dev, "failed to register component %s\n",
 754                        fsl_micfil_component.name);
 755        }
 756
 757        return ret;
 758}
 759
 760static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev)
 761{
 762        struct fsl_micfil *micfil = dev_get_drvdata(dev);
 763
 764        regcache_cache_only(micfil->regmap, true);
 765
 766        clk_disable_unprepare(micfil->mclk);
 767        clk_disable_unprepare(micfil->busclk);
 768
 769        return 0;
 770}
 771
 772static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev)
 773{
 774        struct fsl_micfil *micfil = dev_get_drvdata(dev);
 775        int ret;
 776
 777        ret = clk_prepare_enable(micfil->busclk);
 778        if (ret < 0)
 779                return ret;
 780
 781        ret = clk_prepare_enable(micfil->mclk);
 782        if (ret < 0) {
 783                clk_disable_unprepare(micfil->busclk);
 784                return ret;
 785        }
 786
 787        regcache_cache_only(micfil->regmap, false);
 788        regcache_mark_dirty(micfil->regmap);
 789        regcache_sync(micfil->regmap);
 790
 791        return 0;
 792}
 793
 794static int __maybe_unused fsl_micfil_suspend(struct device *dev)
 795{
 796        pm_runtime_force_suspend(dev);
 797
 798        return 0;
 799}
 800
 801static int __maybe_unused fsl_micfil_resume(struct device *dev)
 802{
 803        pm_runtime_force_resume(dev);
 804
 805        return 0;
 806}
 807
 808static const struct dev_pm_ops fsl_micfil_pm_ops = {
 809        SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
 810                           fsl_micfil_runtime_resume,
 811                           NULL)
 812        SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend,
 813                                fsl_micfil_resume)
 814};
 815
 816static struct platform_driver fsl_micfil_driver = {
 817        .probe = fsl_micfil_probe,
 818        .driver = {
 819                .name = "fsl-micfil-dai",
 820                .pm = &fsl_micfil_pm_ops,
 821                .of_match_table = fsl_micfil_dt_ids,
 822        },
 823};
 824module_platform_driver(fsl_micfil_driver);
 825
 826MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
 827MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
 828MODULE_LICENSE("GPL v2");
 829