LXR linux/sound/soc/tegra/tegra210

   1// SPDX-License-Identifier: GPL-2.0-only
   2//
   3// tegra210_sfc.c - Tegra210 SFC driver
   4//
   5// Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
   6
   7#include <linux/clk.h>
   8#include <linux/device.h>
   9#include <linux/io.h>
  10#include <linux/module.h>
  11#include <linux/of.h>
  12#include <linux/of_device.h>
  13#include <linux/platform_device.h>
  14#include <linux/pm_runtime.h>
  15#include <linux/regmap.h>
  16#include <sound/core.h>
  17#include <sound/pcm.h>
  18#include <sound/pcm_params.h>
  19#include <sound/soc.h>
  20
  21#include "tegra210_sfc.h"
  22#include "tegra_cif.h"
  23
  24#define UNSUPP_CONV ((void *)(-EOPNOTSUPP))
  25#define BYPASS_CONV NULL
  26
  27static const struct reg_default tegra210_sfc_reg_defaults[] = {
  28        { TEGRA210_SFC_RX_INT_MASK, 0x00000001},
  29        { TEGRA210_SFC_RX_CIF_CTRL, 0x00007700},
  30        { TEGRA210_SFC_TX_INT_MASK, 0x00000001},
  31        { TEGRA210_SFC_TX_CIF_CTRL, 0x00007700},
  32        { TEGRA210_SFC_CG, 0x1},
  33        { TEGRA210_SFC_CFG_RAM_CTRL, 0x00004000},
  34};
  35
  36static const int tegra210_sfc_rates[TEGRA210_SFC_NUM_RATES] = {
  37        8000,
  38        11025,
  39        16000,
  40        22050,
  41        24000,
  42        32000,
  43        44100,
  44        48000,
  45        88200,
  46        96000,
  47        176400,
  48        192000,
  49};
  50
  51/* coeff RAM tables required for SFC */
  52static u32 coef_8to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
  53        0x000c6102,//header
  54        0x0001d727,//input gain
  55        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
  56        0x00e55557, 0xffcadd5b, 0x003d80ba,
  57        0x00d13397, 0xfff232f8, 0x00683337,
  58        0x00000002,//output gain
  59        0x0018a102,//header
  60        0x000005d6,//input gain
  61        0x00c6543e, 0xff342935, 0x0052f116,
  62        0x000a1d78, 0xff3330c0, 0x005f88a3,
  63        0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
  64        0x00000003,//output gain
  65        0x00235204,//farrow
  66        0x000aaaab,
  67        0xffaaaaab,
  68        0xfffaaaab,
  69        0x00555555,
  70        0xff600000,
  71        0xfff55555,
  72        0x00155555,
  73        0x00055555,
  74        0xffeaaaab,
  75        0x00200000,
  76        0x00005102,//header
  77        0x0000015f,//input gain
  78        0x00a7909c, 0xff241c71, 0x005f5e00,
  79        0xffca77f4, 0xff20dd50, 0x006855eb,
  80        0xff86c552, 0xff18137a, 0x00773648,
  81        0x00000001//output gain
  82};
  83
  84static u32 coef_8to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
  85        0x00006102,//header
  86        0x0001d727,//input gain
  87        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
  88        0x00e55557, 0xffcadd5b, 0x003d80ba,
  89        0x00d13397, 0xfff232f8, 0x00683337,
  90        0x00000002//output gain
  91};
  92
  93static u32 coef_8to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
  94        0x000c6102,//header
  95        0x0001d727,//input gain
  96        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
  97        0x00e55557, 0xffcadd5b, 0x003d80ba,
  98        0x00d13397, 0xfff232f8, 0x00683337,
  99        0x00000002,//output gain
 100        0x0018a102,//header
 101        0x000005d6,//input gain
 102        0x00c6543e, 0xff342935, 0x0052f116,
 103        0x000a1d78, 0xff3330c0, 0x005f88a3,
 104        0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
 105        0x00000003,//output gain
 106        0x00230204,//farrow
 107        0x000aaaab,
 108        0xffaaaaab,
 109        0xfffaaaab,
 110        0x00555555,
 111        0xff600000,
 112        0xfff55555,
 113        0x00155555,
 114        0x00055555,
 115        0xffeaaaab,
 116        0x00200000,
 117        0x00005102,//header
 118        0x000005f3,//input gain
 119        0x00d816d6, 0xff385383, 0x004fe566,
 120        0x003c548d, 0xff38c23d, 0x005d0b1c,
 121        0xfff02f7d, 0xff31e983, 0x0072d65d,
 122        0x00000001//output gain
 123};
 124
 125static u32 coef_8to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 126        0x0000a105,//header
 127        0x000005e1,//input gain
 128        0x00dca92f, 0xff45647a, 0x0046b59c,
 129        0x00429d1e, 0xff4fec62, 0x00516d30,
 130        0xffdea779, 0xff5e08ba, 0x0060185e,
 131        0xffafbab2, 0xff698d5a, 0x006ce3ae,
 132        0xff9a82d2, 0xff704674, 0x007633c5,
 133        0xff923433, 0xff721128, 0x007cff42,
 134        0x00000003//output gain
 135};
 136
 137static u32 coef_8to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 138        0x000c6102,//header
 139        0x0001d727,//input gain
 140        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 141        0x00e55557, 0xffcadd5b, 0x003d80ba,
 142        0x00d13397, 0xfff232f8, 0x00683337,
 143        0x00000002,//output gain
 144        0x00006102,//header
 145        0x000013d9,//input gain
 146        0x00ebd477, 0xff4ce383, 0x0042049d,
 147        0x0089c278, 0xff54414d, 0x00531ded,
 148        0x004a5e07, 0xff53cf41, 0x006efbdc,
 149        0x00000002//output gain
 150};
 151
 152static u32 coef_8to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 153        0x0156105,//interpolation + IIR filter
 154        0x0000d649,//input gain
 155        0x00e87afb, 0xff5f69d0, 0x003df3cf,
 156        0x007ce488, 0xff99a5c8, 0x0056a6a0,
 157        0x00344928, 0xffcba3e5, 0x006be470,
 158        0x00137aa7, 0xffe60276, 0x00773410,
 159        0x0005fa2a, 0xfff1ac11, 0x007c795b,
 160        0x00012d36, 0xfff5eca2, 0x007f10ef,
 161        0x00000002,//ouptut gain
 162        0x0021a102,//interpolation + IIR filter
 163        0x00000e00,//input gain
 164        0x00e2e000, 0xff6e1a00, 0x002aaa00,
 165        0x00610a00, 0xff5dda00, 0x003ccc00,
 166        0x00163a00, 0xff3c0400, 0x00633200,
 167        0x00000003,//Output gain
 168        0x00000204,//Farrow filter
 169        0x000aaaab,
 170        0xffaaaaab,
 171        0xfffaaaab,
 172        0x00555555,
 173        0xff600000,
 174        0xfff55555,
 175        0x00155555,
 176        0x00055555,
 177        0xffeaaaab,
 178        0x00200000
 179};
 180
 181static u32 coef_8to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 182        0x00156105,//interpolation + IIR Filter
 183        0x0000d649,//input gain
 184        0x00e87afb, 0xff5f69d0, 0x003df3cf,
 185        0x007ce488, 0xff99a5c8, 0x0056a6a0,
 186        0x00344928, 0xffcba3e5, 0x006be470,
 187        0x00137aa7, 0xffe60276, 0x00773410,
 188        0x0005fa2a, 0xfff1ac11, 0x007c795b,
 189        0x00012d36, 0xfff5eca2, 0x007f10ef,
 190        0x00000002,//ouptut gain
 191        0x0000a102,//interpolation + IIR filter
 192        0x00000e00,//input gain
 193        0x00e2e000, 0xff6e1a00, 0x002aaa00,
 194        0x00610a00, 0xff5dda00, 0x003ccc00,
 195        0x00163a00, 0xff3c0400, 0x00633200,
 196        0x00000003//output gain
 197};
 198
 199static u32 coef_8to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 200        0x000c6102,//header
 201        0x0001d727,//input gain
 202        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 203        0x00e55557, 0xffcadd5b, 0x003d80ba,
 204        0x00d13397, 0xfff232f8, 0x00683337,
 205        0x00000002,//output gain
 206        0x00186102,//header
 207        0x000013d9,//input gain
 208        0x00ebd477, 0xff4ce383, 0x0042049d,
 209        0x0089c278, 0xff54414d, 0x00531ded,
 210        0x004a5e07, 0xff53cf41, 0x006efbdc,
 211        0x00000002,//output gain
 212        0x0024a102,//header
 213        0x0000007d,//input gain
 214        0x007d1f20, 0xff1a540e, 0x00678bf9,
 215        0xff916625, 0xff16b0ff, 0x006e433a,
 216        0xff5af660, 0xff0eb91f, 0x00797356,
 217        0x00000003,//output gain
 218        0x00000204,//farrow
 219        0x000aaaab,
 220        0xffaaaaab,
 221        0xfffaaaab,
 222        0x00555555,
 223        0xff600000,
 224        0xfff55555,
 225        0x00155555,
 226        0x00055555,
 227        0xffeaaaab,
 228        0x00200000
 229};
 230
 231static u32 coef_8to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 232        0x000c6102,//header
 233        0x0001d727,//input gain
 234        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 235        0x00e55557, 0xffcadd5b, 0x003d80ba,
 236        0x00d13397, 0xfff232f8, 0x00683337,
 237        0x00000002,//output gain
 238        0x00186102,//header
 239        0x000013d9,//input gain
 240        0x00ebd477, 0xff4ce383, 0x0042049d,
 241        0x0089c278, 0xff54414d, 0x00531ded,
 242        0x004a5e07, 0xff53cf41, 0x006efbdc,
 243        0x00000002,//output gain
 244        0x0000a102,//header
 245        0x0000007d,//input gain
 246        0x007d1f20, 0xff1a540e, 0x00678bf9,
 247        0xff916625, 0xff16b0ff, 0x006e433a,
 248        0xff5af660, 0xff0eb91f, 0x00797356,
 249        0x00000003//output gain
 250};
 251
 252static u32 coef_11to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 253        0x000c6102,//header
 254        0x0000015f,//input gain
 255        0x00a7909c, 0xff241c71, 0x005f5e00,
 256        0xffca77f4, 0xff20dd50, 0x006855eb,
 257        0xff86c552, 0xff18137a, 0x00773648,
 258        0x00000002,//output gain
 259        0x00186102,//header
 260        0x000005f3,//input gain
 261        0x00d816d6, 0xff385383, 0x004fe566,
 262        0x003c548d, 0xff38c23d, 0x005d0b1c,
 263        0xfff02f7d, 0xff31e983, 0x0072d65d,
 264        0x00000002,//output gain
 265        0x00239204,//farrow
 266        0x000aaaab,
 267        0xffaaaaab,
 268        0xfffaaaab,
 269        0x00555555,
 270        0xff600000,
 271        0xfff55555,
 272        0x00155555,
 273        0x00055555,
 274        0xffeaaaab,
 275        0x00200000,
 276        0x00005102,//header
 277        0x0001d727,//input gain
 278        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 279        0x00e55557, 0xffcadd5b, 0x003d80ba,
 280        0x00d13397, 0xfff232f8, 0x00683337,
 281        0x00000001//output gain
 282};
 283
 284static u32 coef_11to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 285        0x000c6102,//header
 286        0x0001d727,//input gain
 287        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 288        0x00e55557, 0xffcadd5b, 0x003d80ba,
 289        0x00d13397, 0xfff232f8, 0x00683337,
 290        0x00000002,//output gain
 291        0x00186102,//header
 292        0x000013d9,//input gain
 293        0x00ebd477, 0xff4ce383, 0x0042049d,
 294        0x0089c278, 0xff54414d, 0x00531ded,
 295        0x004a5e07, 0xff53cf41, 0x006efbdc,
 296        0x00000002,//output gain
 297        0x00009204,//farrow
 298        0x000aaaab,
 299        0xffaaaaab,
 300        0xfffaaaab,
 301        0x00555555,
 302        0xff600000,
 303        0xfff55555,
 304        0x00155555,
 305        0x00055555,
 306        0xffeaaaab,
 307        0x00200000
 308};
 309
 310static u32 coef_11to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 311        0x00006102,//header
 312        0x0001d727,//input gain
 313        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 314        0x00e55557, 0xffcadd5b, 0x003d80ba,
 315        0x00d13397, 0xfff232f8, 0x00683337,
 316        0x00000002//output gain
 317};
 318
 319static u32 coef_11to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 320        0x000c6102,//header
 321        0x0001d727,//input gain
 322        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 323        0x00e55557, 0xffcadd5b, 0x003d80ba,
 324        0x00d13397, 0xfff232f8, 0x00683337,
 325        0x00000002,//output gain
 326        0x00186102,//header
 327        0x000013d9,//input gain
 328        0x00ebd477, 0xff4ce383, 0x0042049d,
 329        0x0089c278, 0xff54414d, 0x00531ded,
 330        0x004a5e07, 0xff53cf41, 0x006efbdc,
 331        0x00000002,//output gain
 332        0x00005204,//farrow
 333        0x000aaaab,
 334        0xffaaaaab,
 335        0xfffaaaab,
 336        0x00555555,
 337        0xff600000,
 338        0xfff55555,
 339        0x00155555,
 340        0x00055555,
 341        0xffeaaaab,
 342        0x00200000
 343};
 344
 345static u32 coef_11to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 346        0x000c6102,//header
 347        0x0001d727,//input gain
 348        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 349        0x00e55557, 0xffcadd5b, 0x003d80ba,
 350        0x00d13397, 0xfff232f8, 0x00683337,
 351        0x00000002,//output gain
 352        0x00186102,//header
 353        0x000013d9,//input gain
 354        0x00ebd477, 0xff4ce383, 0x0042049d,
 355        0x0089c278, 0xff54414d, 0x00531ded,
 356        0x004a5e07, 0xff53cf41, 0x006efbdc,
 357        0x00000002,//output gain
 358        0x00246102,//header
 359        0x0000010a,//input gain
 360        0x00c93dc4, 0xff26f5f6, 0x005d1041,
 361        0x001002c4, 0xff245b76, 0x00666002,
 362        0xffc30a45, 0xff1baecd, 0x00765921,
 363        0x00000002,//output gain
 364        0x00009204,//farrow
 365        0x000aaaab,
 366        0xffaaaaab,
 367        0xfffaaaab,
 368        0x00555555,
 369        0xff600000,
 370        0xfff55555,
 371        0x00155555,
 372        0x00055555,
 373        0xffeaaaab,
 374        0x00200000
 375};
 376
 377static u32 coef_11to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 378        0x000c6102,//header
 379        0x0001d727,//input gain
 380        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 381        0x00e55557, 0xffcadd5b, 0x003d80ba,
 382        0x00d13397, 0xfff232f8, 0x00683337,
 383        0x00000002,//output gain
 384        0x00006102,//header
 385        0x000013d9,//input gain
 386        0x00ebd477, 0xff4ce383, 0x0042049d,
 387        0x0089c278, 0xff54414d, 0x00531ded,
 388        0x004a5e07, 0xff53cf41, 0x006efbdc,
 389        0x00000002//output gain
 390};
 391
 392static u32 coef_11to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 393        0x000c6102,//header
 394        0x0001d727,//input gain
 395        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 396        0x00e55557, 0xffcadd5b, 0x003d80ba,
 397        0x00d13397, 0xfff232f8, 0x00683337,
 398        0x00000002,//output gain
 399        0x00186102,//header
 400        0x000013d9,//input gain
 401        0x00ebd477, 0xff4ce383, 0x0042049d,
 402        0x0089c278, 0xff54414d, 0x00531ded,
 403        0x004a5e07, 0xff53cf41, 0x006efbdc,
 404        0x00000002,//output gain
 405        0x00246102,//header
 406        0x0000010a,//input gain
 407        0x00c93dc4, 0xff26f5f6, 0x005d1041,
 408        0x001002c4, 0xff245b76, 0x00666002,
 409        0xffc30a45, 0xff1baecd, 0x00765921,
 410        0x00000002,//output gain
 411        0x00005204,//farrow
 412        0x000aaaab,
 413        0xffaaaaab,
 414        0xfffaaaab,
 415        0x00555555,
 416        0xff600000,
 417        0xfff55555,
 418        0x00155555,
 419        0x00055555,
 420        0xffeaaaab,
 421        0x00200000
 422};
 423
 424static u32 coef_11to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 425        0x000c6102,//header
 426        0x0001d727,//input gain
 427        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 428        0x00e55557, 0xffcadd5b, 0x003d80ba,
 429        0x00d13397, 0xfff232f8, 0x00683337,
 430        0x00000002,//output gain
 431        0x00186102,//header
 432        0x000013d9,//input gain
 433        0x00ebd477, 0xff4ce383, 0x0042049d,
 434        0x0089c278, 0xff54414d, 0x00531ded,
 435        0x004a5e07, 0xff53cf41, 0x006efbdc,
 436        0x00000002,//output gain
 437        0x00006102,//header
 438        0x0000010a,//input gain
 439        0x00c93dc4, 0xff26f5f6, 0x005d1041,
 440        0x001002c4, 0xff245b76, 0x00666002,
 441        0xffc30a45, 0xff1baecd, 0x00765921,
 442        0x00000002//output gain
 443};
 444
 445static u32 coef_11to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 446        0x000c6102,//header
 447        0x0001d727,//input gain
 448        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 449        0x00e55557, 0xffcadd5b, 0x003d80ba,
 450        0x00d13397, 0xfff232f8, 0x00683337,
 451        0x00000002,//output gain
 452        0x00186102,//header
 453        0x000013d9,//input gain
 454        0x00ebd477, 0xff4ce383, 0x0042049d,
 455        0x0089c278, 0xff54414d, 0x00531ded,
 456        0x004a5e07, 0xff53cf41, 0x006efbdc,
 457        0x00000002,//output gain
 458        0x00246102,//header
 459        0x0000010a,//input gain
 460        0x00c93dc4, 0xff26f5f6, 0x005d1041,
 461        0x001002c4, 0xff245b76, 0x00666002,
 462        0xffc30a45, 0xff1baecd, 0x00765921,
 463        0x00000002,//output gain
 464        0x00000204,//farrow
 465        0x000aaaab,
 466        0xffaaaaab,
 467        0xfffaaaab,
 468        0x00555555,
 469        0xff600000,
 470        0xfff55555,
 471        0x00155555,
 472        0x00055555,
 473        0xffeaaaab,
 474        0x00200000
 475};
 476
 477static u32 coef_16to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 478        0x00005102,//header
 479        0x0001d727,//input gain
 480        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 481        0x00e55557, 0xffcadd5b, 0x003d80ba,
 482        0x00d13397, 0xfff232f8, 0x00683337,
 483        0x00000001//output gain
 484};
 485
 486static u32 coef_16to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 487        0x000fa103,//header
 488        0x000001e0,//input gain
 489        0x00de44c0, 0xff380b7f, 0x004ffc73,
 490        0x00494b44, 0xff3d493a, 0x005908bf,
 491        0xffe9a3c8, 0xff425647, 0x006745f7,
 492        0xffc42d61, 0xff40a6c7, 0x00776709,
 493        0x00000003,//output gain
 494        0x001a5204,//farrow
 495        0x000aaaab,
 496        0xffaaaaab,
 497        0xfffaaaab,
 498        0x00555555,
 499        0xff600000,
 500        0xfff55555,
 501        0x00155555,
 502        0x00055555,
 503        0xffeaaaab,
 504        0x00200000,
 505        0x00005102,//header
 506        0x0001d727,//input gain
 507        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 508        0x00e55557, 0xffcadd5b, 0x003d80ba,
 509        0x00d13397, 0xfff232f8, 0x00683337,
 510        0x00000001//output gain
 511};
 512
 513static u32 coef_16to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 514        0x000c6102,//header
 515        0x0001d727,//input gain
 516        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 517        0x00e55557, 0xffcadd5b, 0x003d80ba,
 518        0x00d13397, 0xfff232f8, 0x00683337,
 519        0x00000002,//output gain
 520        0x0018a102,//header
 521        0x000005d6,//input gain
 522        0x00c6543e, 0xff342935, 0x0052f116,
 523        0x000a1d78, 0xff3330c0, 0x005f88a3,
 524        0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
 525        0x00000003,//output gain
 526        0x00235204,//farrow
 527        0x000aaaab,
 528        0xffaaaaab,
 529        0xfffaaaab,
 530        0x00555555,
 531        0xff600000,
 532        0xfff55555,
 533        0x00155555,
 534        0x00055555,
 535        0xffeaaaab,
 536        0x00200000,
 537        0x00005102,//header
 538        0x0000015f,//input gain
 539        0x00a7909c, 0xff241c71, 0x005f5e00,
 540        0xffca77f4, 0xff20dd50, 0x006855eb,
 541        0xff86c552, 0xff18137a, 0x00773648,
 542        0x00000001//output gain
 543};
 544
 545static u32 coef_16to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 546        0x0015a105,//header
 547        0x00000292,//input gain
 548        0x00e4320a, 0xff41d2d9, 0x004911ac,
 549        0x005dd9e3, 0xff4c7d80, 0x0052103e,
 550        0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
 551        0xffc4b414, 0xff68582c, 0x006b38e5,
 552        0xffabb861, 0xff704bec, 0x0074de52,
 553        0xffa19f4c, 0xff729059, 0x007c7e90,
 554        0x00000003,//output gain
 555        0x00005105,//header
 556        0x00000292,//input gain
 557        0x00e4320a, 0xff41d2d9, 0x004911ac,
 558        0x005dd9e3, 0xff4c7d80, 0x0052103e,
 559        0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
 560        0xffc4b414, 0xff68582c, 0x006b38e5,
 561        0xffabb861, 0xff704bec, 0x0074de52,
 562        0xffa19f4c, 0xff729059, 0x007c7e90,
 563        0x00000001//output gain
 564};
 565
 566static u32 coef_16to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 567        0x00006102,//header
 568        0x0001d727,//input gain
 569        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 570        0x00e55557, 0xffcadd5b, 0x003d80ba,
 571        0x00d13397, 0xfff232f8, 0x00683337,
 572        0x00000002//output gain
 573};
 574
 575static u32 coef_16to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 576        0x00156105,//interpolation + IIR filter
 577        0x0000d649,//input gain
 578        0x00e87afb, 0xff5f69d0, 0x003df3cf,
 579        0x007ce488, 0xff99a5c8, 0x0056a6a0,
 580        0x00344928, 0xffcba3e5, 0x006be470,
 581        0x00137aa7, 0xffe60276, 0x00773410,
 582        0x0005fa2a, 0xfff1ac11, 0x007c795b,
 583        0x00012d36, 0xfff5eca2, 0x007f10ef,
 584        0x00000002,//output gain
 585        0x0021a102,//interpolation + IIR filter
 586        0x00000e00,//input gain
 587        0x00e2e000, 0xff6e1a00, 0x002aaa00,
 588        0x00610a00, 0xff5dda00, 0x003ccc00,
 589        0x00163a00, 0xff3c0400, 0x00633200,
 590        0x00000003,//output gain
 591        0x002c0204,//Farrow Filter
 592        0x000aaaab,
 593        0xffaaaaab,
 594        0xfffaaaab,
 595        0x00555555,
 596        0xff600000,
 597        0xfff55555,
 598        0x00155555,
 599        0x00055555,
 600        0xffeaaaab,
 601        0x00200000,
 602        0x00005101,//IIR Filter + Decimator
 603        0x0000203c,//input gain
 604        0x00f52d35, 0xff2e2162, 0x005a21e0,
 605        0x00c6f0f0, 0xff2ecd69, 0x006fa78d,
 606        0x00000001//output gain
 607};
 608
 609static u32 coef_16to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 610        0x0000a105,//interpolation + IIR Filter
 611        0x00000784,//input gain
 612        0x00cc516e, 0xff2c9639, 0x005ad5b3,
 613        0x0013ad0d, 0xff3d4799, 0x0063ce75,
 614        0xffb6f398, 0xff5138d1, 0x006e9e1f,
 615        0xff9186e5, 0xff5f96a4, 0x0076a86e,
 616        0xff82089c, 0xff676b81, 0x007b9f8a,
 617        0xff7c48a5, 0xff6a31e7, 0x007ebb7b,
 618        0x00000003//output gain
 619};
 620
 621static u32 coef_16to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 622        0x000c6102,//header
 623        0x0001d727,//input gain
 624        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 625        0x00e55557, 0xffcadd5b, 0x003d80ba,
 626        0x00d13397, 0xfff232f8, 0x00683337,
 627        0x00000002,//output gain
 628        0x0018a102,//header
 629        0x000005d6,//input gain
 630        0x00c6543e, 0xff342935, 0x0052f116,
 631        0x000a1d78, 0xff3330c0, 0x005f88a3,
 632        0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
 633        0x00000003,//output gain
 634        0x00000204,//farrow
 635        0x000aaaab,
 636        0xffaaaaab,
 637        0xfffaaaab,
 638        0x00555555,
 639        0xff600000,
 640        0xfff55555,
 641        0x00155555,
 642        0x00055555,
 643        0xffeaaaab,
 644        0x00200000
 645};
 646
 647static u32 coef_16to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 648        0x000c6102,//header
 649        0x0001d727,//input gain
 650        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 651        0x00e55557, 0xffcadd5b, 0x003d80ba,
 652        0x00d13397, 0xfff232f8, 0x00683337,
 653        0x00000002,//output gain
 654        0x0000a102,//header
 655        0x000005d6,//input gain
 656        0x00c6543e, 0xff342935, 0x0052f116,
 657        0x000a1d78, 0xff3330c0, 0x005f88a3,
 658        0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
 659        0x00000003//output gain
 660};
 661
 662static u32 coef_16to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 663        0x000c6102,//header
 664        0x0001d727,//input gain
 665        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 666        0x00e55557, 0xffcadd5b, 0x003d80ba,
 667        0x00d13397, 0xfff232f8, 0x00683337,
 668        0x00000002,//output gain
 669        0x00186102,//header
 670        0x000013d9,//input gain
 671        0x00ebd477, 0xff4ce383, 0x0042049d,
 672        0x0089c278, 0xff54414d, 0x00531ded,
 673        0x004a5e07, 0xff53cf41, 0x006efbdc,
 674        0x00000002,//output gain
 675        0x0024a102,//header
 676        0x0000007d,//input gain
 677        0x007d1f20, 0xff1a540e, 0x00678bf9,
 678        0xff916625, 0xff16b0ff, 0x006e433a,
 679        0xff5af660, 0xff0eb91f, 0x00797356,
 680        0x00000003,//output gain
 681        0x00000204,//farrow
 682        0x000aaaab,
 683        0xffaaaaab,
 684        0xfffaaaab,
 685        0x00555555,
 686        0xff600000,
 687        0xfff55555,
 688        0x00155555,
 689        0x00055555,
 690        0xffeaaaab,
 691        0x00200000
 692};
 693
 694static u32 coef_16to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 695        0x000c6102,//header
 696        0x0001d727,//input gain
 697        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 698        0x00e55557, 0xffcadd5b, 0x003d80ba,
 699        0x00d13397, 0xfff232f8, 0x00683337,
 700        0x00000002,//output gain
 701        0x00186102,//header
 702        0x000013d9,//input gain
 703        0x00ebd477, 0xff4ce383, 0x0042049d,
 704        0x0089c278, 0xff54414d, 0x00531ded,
 705        0x004a5e07, 0xff53cf41, 0x006efbdc,
 706        0x00000002,//output gain
 707        0x0000a102,//header
 708        0x0000007d,//input gain
 709        0x007d1f20, 0xff1a540e, 0x00678bf9,
 710        0xff916625, 0xff16b0ff, 0x006e433a,
 711        0xff5af660, 0xff0eb91f, 0x00797356,
 712        0x00000003//output gain
 713};
 714
 715static u32 coef_22to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 716        0x000c6102,//header
 717        0x000005f3,//input gain
 718        0x00d816d6, 0xff385383, 0x004fe566,
 719        0x003c548d, 0xff38c23d, 0x005d0b1c,
 720        0xfff02f7d, 0xff31e983, 0x0072d65d,
 721        0x00000002,//output gain
 722        0x00179204,//farrow
 723        0x000aaaab,
 724        0xffaaaaab,
 725        0xfffaaaab,
 726        0x00555555,
 727        0xff600000,
 728        0xfff55555,
 729        0x00155555,
 730        0x00055555,
 731        0xffeaaaab,
 732        0x00200000,
 733        0x00005102,//header
 734        0x0001d727,//input gain
 735        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 736        0x00e55557, 0xffcadd5b, 0x003d80ba,
 737        0x00d13397, 0xfff232f8, 0x00683337,
 738        0x00000001//output gain
 739};
 740
 741static u32 coef_22to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 742        0x00005102,//header
 743        0x0001d727,//input gain
 744        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 745        0x00e55557, 0xffcadd5b, 0x003d80ba,
 746        0x00d13397, 0xfff232f8, 0x00683337,
 747        0x00000001//output gain
 748};
 749
 750static u32 coef_22to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 751        0x000c6102,//header
 752        0x0000015f,//input gain
 753        0x00a7909c, 0xff241c71, 0x005f5e00,
 754        0xffca77f4, 0xff20dd50, 0x006855eb,
 755        0xff86c552, 0xff18137a, 0x00773648,
 756        0x00000002,//output gain
 757        0x00186102,//header
 758        0x000005f3,//input gain
 759        0x00d816d6, 0xff385383, 0x004fe566,
 760        0x003c548d, 0xff38c23d, 0x005d0b1c,
 761        0xfff02f7d, 0xff31e983, 0x0072d65d,
 762        0x00000002,//output gain
 763        0x00239204,//farrow
 764        0x000aaaab,
 765        0xffaaaaab,
 766        0xfffaaaab,
 767        0x00555555,
 768        0xff600000,
 769        0xfff55555,
 770        0x00155555,
 771        0x00055555,
 772        0xffeaaaab,
 773        0x00200000,
 774        0x00005102,//header
 775        0x0001d727,//input gain
 776        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 777        0x00e55557, 0xffcadd5b, 0x003d80ba,
 778        0x00d13397, 0xfff232f8, 0x00683337,
 779        0x00000001//output gain
 780};
 781
 782static u32 coef_22to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 783        0x000c6102,//header
 784        0x0001d727,//input gain
 785        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 786        0x00e55557, 0xffcadd5b, 0x003d80ba,
 787        0x00d13397, 0xfff232f8, 0x00683337,
 788        0x00000002,//output gain
 789        0x00186102,//header
 790        0x000013d9,//input gain
 791        0x00ebd477, 0xff4ce383, 0x0042049d,
 792        0x0089c278, 0xff54414d, 0x00531ded,
 793        0x004a5e07, 0xff53cf41, 0x006efbdc,
 794        0x00000002,//output gain
 795        0x00235204,//farrow
 796        0x000aaaab,
 797        0xffaaaaab,
 798        0xfffaaaab,
 799        0x00555555,
 800        0xff600000,
 801        0xfff55555,
 802        0x00155555,
 803        0x00055555,
 804        0xffeaaaab,
 805        0x00200000,
 806        0x00005102,//header
 807        0x0001d029,//input gain
 808        0x00f2a98b, 0xff92aa71, 0x001fcd16,
 809        0x00ae9004, 0xffb85140, 0x0041813a,
 810        0x007f8ed1, 0xffd585fc, 0x006a69e6,
 811        0x00000001//output gain
 812};
 813
 814static u32 coef_22to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 815        0x000c6102,//header
 816        0x0001d727,//input gain
 817        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 818        0x00e55557, 0xffcadd5b, 0x003d80ba,
 819        0x00d13397, 0xfff232f8, 0x00683337,
 820        0x00000002,//output gain
 821        0x00186102,//header
 822        0x000013d9,//input gain
 823        0x00ebd477, 0xff4ce383, 0x0042049d,
 824        0x0089c278, 0xff54414d, 0x00531ded,
 825        0x004a5e07, 0xff53cf41, 0x006efbdc,
 826        0x00000002,//output gain
 827        0x00009204,//farrow
 828        0x000aaaab,
 829        0xffaaaaab,
 830        0xfffaaaab,
 831        0x00555555,
 832        0xff600000,
 833        0xfff55555,
 834        0x00155555,
 835        0x00055555,
 836        0xffeaaaab,
 837        0x00200000
 838};
 839
 840static u32 coef_22to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 841        0x00006102,//header
 842        0x0001d727,//input gain
 843        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 844        0x00e55557, 0xffcadd5b, 0x003d80ba,
 845        0x00d13397, 0xfff232f8, 0x00683337,
 846        0x00000002//output gain
 847};
 848
 849static u32 coef_22to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 850        0x000c6102,//header
 851        0x0001d727,//input gain
 852        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 853        0x00e55557, 0xffcadd5b, 0x003d80ba,
 854        0x00d13397, 0xfff232f8, 0x00683337,
 855        0x00000002,//output gain
 856        0x00186102,//header
 857        0x000013d9,//input gain
 858        0x00ebd477, 0xff4ce383, 0x0042049d,
 859        0x0089c278, 0xff54414d, 0x00531ded,
 860        0x004a5e07, 0xff53cf41, 0x006efbdc,
 861        0x00000002,//output gain
 862        0x00005204,//farrow
 863        0x000aaaab,
 864        0xffaaaaab,
 865        0xfffaaaab,
 866        0x00555555,
 867        0xff600000,
 868        0xfff55555,
 869        0x00155555,
 870        0x00055555,
 871        0xffeaaaab,
 872        0x00200000
 873};
 874
 875static u32 coef_22to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 876        0x000c6102,//header
 877        0x0001d727,//input gain
 878        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 879        0x00e55557, 0xffcadd5b, 0x003d80ba,
 880        0x00d13397, 0xfff232f8, 0x00683337,
 881        0x00000002,//output gain
 882        0x00006102,//header
 883        0x000013d9,//input gain
 884        0x00ebd477, 0xff4ce383, 0x0042049d,
 885        0x0089c278, 0xff54414d, 0x00531ded,
 886        0x004a5e07, 0xff53cf41, 0x006efbdc,
 887        0x00000002//output gain
 888};
 889
 890static u32 coef_22to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 891        0x000c6102,//header
 892        0x0001d727,//input gain
 893        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 894        0x00e55557, 0xffcadd5b, 0x003d80ba,
 895        0x00d13397, 0xfff232f8, 0x00683337,
 896        0x00000002,//output gain
 897        0x00186102,//header
 898        0x000013d9,//input gain
 899        0x00ebd477, 0xff4ce383, 0x0042049d,
 900        0x0089c278, 0xff54414d, 0x00531ded,
 901        0x004a5e07, 0xff53cf41, 0x006efbdc,
 902        0x00000002,//output gain
 903        0x00246102,//header
 904        0x0000010a,//input gain
 905        0x00c93dc4, 0xff26f5f6, 0x005d1041,
 906        0x001002c4, 0xff245b76, 0x00666002,
 907        0xffc30a45, 0xff1baecd, 0x00765921,
 908        0x00000002,//output gain
 909        0x00005204,//farrow
 910        0x000aaaab,
 911        0xffaaaaab,
 912        0xfffaaaab,
 913        0x00555555,
 914        0xff600000,
 915        0xfff55555,
 916        0x00155555,
 917        0x00055555,
 918        0xffeaaaab,
 919        0x00200000
 920};
 921
 922static u32 coef_22to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 923        0x000c6102,//header
 924        0x0001d727,//input gain
 925        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 926        0x00e55557, 0xffcadd5b, 0x003d80ba,
 927        0x00d13397, 0xfff232f8, 0x00683337,
 928        0x00000002,//output gain
 929        0x00186102,//header
 930        0x000013d9,//input gain
 931        0x00ebd477, 0xff4ce383, 0x0042049d,
 932        0x0089c278, 0xff54414d, 0x00531ded,
 933        0x004a5e07, 0xff53cf41, 0x006efbdc,
 934        0x00000002,//output gain
 935        0x00006102,//header
 936        0x0000010a,//input gain
 937        0x00c93dc4, 0xff26f5f6, 0x005d1041,
 938        0x001002c4, 0xff245b76, 0x00666002,
 939        0xffc30a45, 0xff1baecd, 0x00765921,
 940        0x00000002//output gain
 941};
 942
 943static u32 coef_22to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 944        0x000c6102,//header
 945        0x0001d727,//input gain
 946        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
 947        0x00e55557, 0xffcadd5b, 0x003d80ba,
 948        0x00d13397, 0xfff232f8, 0x00683337,
 949        0x00000002,//output gain
 950        0x00186102,//header
 951        0x000013d9,//input gain
 952        0x00ebd477, 0xff4ce383, 0x0042049d,
 953        0x0089c278, 0xff54414d, 0x00531ded,
 954        0x004a5e07, 0xff53cf41, 0x006efbdc,
 955        0x00000002,//output gain
 956        0x00246102,//header
 957        0x0000010a,//input gain
 958        0x00c93dc4, 0xff26f5f6, 0x005d1041,
 959        0x001002c4, 0xff245b76, 0x00666002,
 960        0xffc30a45, 0xff1baecd, 0x00765921,
 961        0x00000002,//output gain
 962        0x00000204,//farrow
 963        0x000aaaab,
 964        0xffaaaaab,
 965        0xfffaaaab,
 966        0x00555555,
 967        0xff600000,
 968        0xfff55555,
 969        0x00155555,
 970        0x00055555,
 971        0xffeaaaab,
 972        0x00200000
 973};
 974
 975static u32 coef_24to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 976        0x00009105,//header
 977        0x000005e1,//input gain
 978        0x00dca92f, 0xff45647a, 0x0046b59c,
 979        0x00429d1e, 0xff4fec62, 0x00516d30,
 980        0xffdea779, 0xff5e08ba, 0x0060185e,
 981        0xffafbab2, 0xff698d5a, 0x006ce3ae,
 982        0xff9a82d2, 0xff704674, 0x007633c5,
 983        0xff923433, 0xff721128, 0x007cff42,
 984        0x00000001//output gain
 985};
 986
 987static u32 coef_24to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
 988        0x000f6103,//header
 989        0x000001e0,//input gain
 990        0x00de44c0, 0xff380b7f, 0x004ffc73,
 991        0x00494b44, 0xff3d493a, 0x005908bf,
 992        0xffe9a3c8, 0xff425647, 0x006745f7,
 993        0xffc42d61, 0xff40a6c7, 0x00776709,
 994        0x00000002,//output gain
 995        0x001a5204,//farrow
 996        0x000aaaab,
 997        0xffaaaaab,
 998        0xfffaaaab,
 999        0x00555555,
1000        0xff600000,

1001        0xfff55555,
1002        0x00155555,
1003        0x00055555,
1004        0xffeaaaab,
1005        0x00200000,
1006        0x00005102,//header
1007        0x0001d727,//input gain
1008        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1009        0x00e55557, 0xffcadd5b, 0x003d80ba,
1010        0x00d13397, 0xfff232f8, 0x00683337,
1011        0x00000001//output gain
1012};
1013
1014static u32 coef_24to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1015        0x00156105,//header
1016        0x00000292,//input gain
1017        0x00e4320a, 0xff41d2d9, 0x004911ac,
1018        0x005dd9e3, 0xff4c7d80, 0x0052103e,
1019        0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
1020        0xffc4b414, 0xff68582c, 0x006b38e5,
1021        0xffabb861, 0xff704bec, 0x0074de52,
1022        0xffa19f4c, 0xff729059, 0x007c7e90,
1023        0x00000002,//output gain
1024        0x00009105,//header
1025        0x00000292,//input gain
1026        0x00e4320a, 0xff41d2d9, 0x004911ac,
1027        0x005dd9e3, 0xff4c7d80, 0x0052103e,
1028        0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
1029        0xffc4b414, 0xff68582c, 0x006b38e5,
1030        0xffabb861, 0xff704bec, 0x0074de52,
1031        0xffa19f4c, 0xff729059, 0x007c7e90,
1032        0x00000001//output gain
1033};
1034
1035static u32 coef_24to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1036        0x000c6102,//header
1037        0x0001d029,//input gain
1038        0x00f2a98b, 0xff92aa71, 0x001fcd16,
1039        0x00ae9004, 0xffb85140, 0x0041813a,
1040        0x007f8ed1, 0xffd585fc, 0x006a69e6,
1041        0x00000002,//output gain
1042        0x001b6103,//header
1043        0x000001e0,//input gain
1044        0x00de44c0, 0xff380b7f, 0x004ffc73,
1045        0x00494b44, 0xff3d493a, 0x005908bf,
1046        0xffe9a3c8, 0xff425647, 0x006745f7,
1047        0xffc42d61, 0xff40a6c7, 0x00776709,
1048        0x00000002,//output gain
1049        0x00265204,//farrow
1050        0x000aaaab,
1051        0xffaaaaab,
1052        0xfffaaaab,
1053        0x00555555,
1054        0xff600000,
1055        0xfff55555,
1056        0x00155555,
1057        0x00055555,
1058        0xffeaaaab,
1059        0x00200000,
1060        0x00005102,//header
1061        0x0001d727,//input gain
1062        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1063        0x00e55557, 0xffcadd5b, 0x003d80ba,
1064        0x00d13397, 0xfff232f8, 0x00683337,
1065        0x00000001//output gain
1066};
1067
1068static u32 coef_24to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1069        0x000c6102,//header
1070        0x0001d727,//input gain
1071        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1072        0x00e55557, 0xffcadd5b, 0x003d80ba,
1073        0x00d13397, 0xfff232f8, 0x00683337,
1074        0x00000002,//output gain
1075        0x00186102,//header
1076        0x000013d9,//input gain
1077        0x00ebd477, 0xff4ce383, 0x0042049d,
1078        0x0089c278, 0xff54414d, 0x00531ded,
1079        0x004a5e07, 0xff53cf41, 0x006efbdc,
1080        0x00000002,//output gain
1081        0x00009102,//header
1082        0x000013d9,//input gain
1083        0x00ebd477, 0xff4ce383, 0x0042049d,
1084        0x0089c278, 0xff54414d, 0x00531ded,
1085        0x004a5e07, 0xff53cf41, 0x006efbdc,
1086        0x00000001//output gain
1087};
1088
1089static u32 coef_24to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1090        0x000c6102,//header
1091        0x0001d727,//input gain
1092        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1093        0x00e55557, 0xffcadd5b, 0x003d80ba,
1094        0x00d13397, 0xfff232f8, 0x00683337,
1095        0x00000002,//output gain
1096        0x00186102,//header
1097        0x000013d9,//input gain
1098        0x00ebd477, 0xff4ce383, 0x0042049d,
1099        0x0089c278, 0xff54414d, 0x00531ded,
1100        0x004a5e07, 0xff53cf41, 0x006efbdc,
1101        0x00000002,//output gain
1102        0x00230204,//farrow
1103        0x000aaaab,
1104        0xffaaaaab,
1105        0xfffaaaab,
1106        0x00555555,
1107        0xff600000,
1108        0xfff55555,
1109        0x00155555,
1110        0x00055555,
1111        0xffeaaaab,
1112        0x00200000,
1113        0x00005102,//header
1114        0x00001685,//input gain
1115        0x00f53ae9, 0xff52f196, 0x003e3e08,
1116        0x00b9f857, 0xff5d8985, 0x0050070a,
1117        0x008c3e86, 0xff6053f0, 0x006d98ef,
1118        0x00000001//output gain
1119};
1120
1121static u32 coef_24to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1122        0x00006102,//header
1123        0x0001d727,//input gain
1124        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1125        0x00e55557, 0xffcadd5b, 0x003d80ba,
1126        0x00d13397, 0xfff232f8, 0x00683337,
1127        0x00000002//output gain
1128};
1129
1130static u32 coef_24to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1131        0x000c6102,//header
1132        0x0001d727,//input gain
1133        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1134        0x00e55557, 0xffcadd5b, 0x003d80ba,
1135        0x00d13397, 0xfff232f8, 0x00683337,
1136        0x00000002,//output gain
1137        0x00186102,//header
1138        0x000013d9,//input gain
1139        0x00ebd477, 0xff4ce383, 0x0042049d,
1140        0x0089c278, 0xff54414d, 0x00531ded,
1141        0x004a5e07, 0xff53cf41, 0x006efbdc,
1142        0x00000002,//output gain
1143        0x00246102,//header
1144        0x0000010a,//input gain
1145        0x00c93dc4, 0xff26f5f6, 0x005d1041,
1146        0x001002c4, 0xff245b76, 0x00666002,
1147        0xffc30a45, 0xff1baecd, 0x00765921,
1148        0x00000002,//output gain
1149        0x002f0204,//farrow
1150        0x000aaaab,
1151        0xffaaaaab,
1152        0xfffaaaab,
1153        0x00555555,
1154        0xff600000,
1155        0xfff55555,
1156        0x00155555,
1157        0x00055555,
1158        0xffeaaaab,
1159        0x00200000,
1160        0x00005102,//header
1161        0x00000138,//input gain
1162        0x00d5d232, 0xff2a3bf8, 0x005a785c,
1163        0x0034001b, 0xff283109, 0x006462a6,
1164        0xffe6746a, 0xff1fb09c, 0x00758a91,
1165        0x00000001//output gain
1166};
1167
1168static u32 coef_24to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1169        0x000c6102,//header
1170        0x0001d727,//input gain
1171        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1172        0x00e55557, 0xffcadd5b, 0x003d80ba,
1173        0x00d13397, 0xfff232f8, 0x00683337,
1174        0x00000002,//output gain
1175        0x00006102,//header
1176        0x000013d9,//input gain
1177        0x00ebd477, 0xff4ce383, 0x0042049d,
1178        0x0089c278, 0xff54414d, 0x00531ded,
1179        0x004a5e07, 0xff53cf41, 0x006efbdc,
1180        0x00000002//output gain
1181};
1182
1183static u32 coef_24to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1184        0x000c6102,//header
1185        0x0001d727,//input gain
1186        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1187        0x00e55557, 0xffcadd5b, 0x003d80ba,
1188        0x00d13397, 0xfff232f8, 0x00683337,
1189        0x00000002,//output gain
1190        0x00186102,//header
1191        0x000013d9,//input gain
1192        0x00ebd477, 0xff4ce383, 0x0042049d,
1193        0x0089c278, 0xff54414d, 0x00531ded,
1194        0x004a5e07, 0xff53cf41, 0x006efbdc,
1195        0x00000002,//output gain
1196        0x00246102,//header
1197        0x0000010a,//input gain
1198        0x00c93dc4, 0xff26f5f6, 0x005d1041,
1199        0x001002c4, 0xff245b76, 0x00666002,
1200        0xffc30a45, 0xff1baecd, 0x00765921,
1201        0x00000002,//output gain
1202        0x00000204,//farrow
1203        0x000aaaab,
1204        0xffaaaaab,
1205        0xfffaaaab,
1206        0x00555555,
1207        0xff600000,
1208        0xfff55555,
1209        0x00155555,
1210        0x00055555,
1211        0xffeaaaab,
1212        0x00200000
1213};
1214
1215static u32 coef_24to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1216        0x000c6102,//header
1217        0x0001d727,//input gain
1218        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1219        0x00e55557, 0xffcadd5b, 0x003d80ba,
1220        0x00d13397, 0xfff232f8, 0x00683337,
1221        0x00000002,//output gain
1222        0x00186102,//header
1223        0x000013d9,//input gain
1224        0x00ebd477, 0xff4ce383, 0x0042049d,
1225        0x0089c278, 0xff54414d, 0x00531ded,
1226        0x004a5e07, 0xff53cf41, 0x006efbdc,
1227        0x00000002,//output gain
1228        0x00006102,//header
1229        0x0000010a,//input gain
1230        0x00c93dc4, 0xff26f5f6, 0x005d1041,
1231        0x001002c4, 0xff245b76, 0x00666002,
1232        0xffc30a45, 0xff1baecd, 0x00765921,
1233        0x00000002//output gain
1234};
1235
1236static u32 coef_32to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1237        0x000c5102,//header
1238        0x000013d9,//input gain
1239        0x00ebd477, 0xff4ce383, 0x0042049d,
1240        0x0089c278, 0xff54414d, 0x00531ded,
1241        0x004a5e07, 0xff53cf41, 0x006efbdc,
1242        0x00000001,//output gain
1243        0x00005102,//header
1244        0x0001d727,//input gain
1245        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1246        0x00e55557, 0xffcadd5b, 0x003d80ba,
1247        0x00d13397, 0xfff232f8, 0x00683337,
1248        0x00000001//output gain
1249};
1250
1251static u32 coef_32to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1252        0x000ca102,//header
1253        0x000000af,//input gain
1254        0x00c65663, 0xff23d2ce, 0x005f97d6,
1255        0x00086ad6, 0xff20ec4f, 0x00683201,
1256        0xffbbbef6, 0xff184447, 0x00770963,
1257        0x00000003,//output gain
1258        0x00175204,//farrow
1259        0x000aaaab,
1260        0xffaaaaab,
1261        0xfffaaaab,
1262        0x00555555,
1263        0xff600000,
1264        0xfff55555,
1265        0x00155555,
1266        0x00055555,
1267        0xffeaaaab,
1268        0x00200000,
1269        0x0000d102,//header
1270        0x000013d9,//input gain
1271        0x00ebd477, 0xff4ce383, 0x0042049d,
1272        0x0089c278, 0xff54414d, 0x00531ded,
1273        0x004a5e07, 0xff53cf41, 0x006efbdc,
1274        0x00000001//output gain
1275};
1276
1277static u32 coef_32to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1278        0x00005102,//header
1279        0x0001d727,//input gain
1280        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1281        0x00e55557, 0xffcadd5b, 0x003d80ba,
1282        0x00d13397, 0xfff232f8, 0x00683337,
1283        0x00000001//output gain
1284};
1285
1286static u32 coef_32to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1287        0x000fa103,//header
1288        0x000001e0,//input gain
1289        0x00de44c0, 0xff380b7f, 0x004ffc73,
1290        0x00494b44, 0xff3d493a, 0x005908bf,
1291        0xffe9a3c8, 0xff425647, 0x006745f7,
1292        0xffc42d61, 0xff40a6c7, 0x00776709,
1293        0x00000003,//output gain
1294        0x001a5204,//farrow
1295        0x000aaaab,
1296        0xffaaaaab,
1297        0xfffaaaab,
1298        0x00555555,
1299        0xff600000,
1300        0xfff55555,
1301        0x00155555,
1302        0x00055555,
1303        0xffeaaaab,
1304        0x00200000,
1305        0x00005102,//header
1306        0x0001d727,//input gain
1307        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1308        0x00e55557, 0xffcadd5b, 0x003d80ba,
1309        0x00d13397, 0xfff232f8, 0x00683337,
1310        0x00000001//output gain
1311};
1312
1313static u32 coef_32to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1314        0x000ca102,//header
1315        0x000013d9,//input gain
1316        0x00ebd477, 0xff4ce383, 0x0042049d,
1317        0x0089c278, 0xff54414d, 0x00531ded,
1318        0x004a5e07, 0xff53cf41, 0x006efbdc,
1319        0x00000003,//output gain
1320        0x0000d102,//header
1321        0x000013d9,//input gain
1322        0x00ebd477, 0xff4ce383, 0x0042049d,
1323        0x0089c278, 0xff54414d, 0x00531ded,
1324        0x004a5e07, 0xff53cf41, 0x006efbdc,
1325        0x00000001//output gain
1326};
1327
1328static u32 coef_32to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1329        0x000c6102,//header
1330        0x0001d727,//input gain
1331        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1332        0x00e55557, 0xffcadd5b, 0x003d80ba,
1333        0x00d13397, 0xfff232f8, 0x00683337,
1334        0x00000002,//output gain
1335        0x0018a102,//header
1336        0x000005d6,//input gain
1337        0x00c6543e, 0xff342935, 0x0052f116,
1338        0x000a1d78, 0xff3330c0, 0x005f88a3,
1339        0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
1340        0x00000003,//output gain
1341        0x00235204,//farrow
1342        0x000aaaab,
1343        0xffaaaaab,
1344        0xfffaaaab,
1345        0x00555555,
1346        0xff600000,
1347        0xfff55555,
1348        0x00155555,
1349        0x00055555,
1350        0xffeaaaab,
1351        0x00200000,
1352        0x00005102,//header
1353        0x0000015f,//input gain
1354        0x00a7909c, 0xff241c71, 0x005f5e00,
1355        0xffca77f4, 0xff20dd50, 0x006855eb,
1356        0xff86c552, 0xff18137a, 0x00773648,
1357        0x00000001//output gain
1358};
1359
1360static u32 coef_32to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1361        0x0015a105,//header
1362        0x00000292,//input gain
1363        0x00e4320a, 0xff41d2d9, 0x004911ac,
1364        0x005dd9e3, 0xff4c7d80, 0x0052103e,
1365        0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
1366        0xffc4b414, 0xff68582c, 0x006b38e5,
1367        0xffabb861, 0xff704bec, 0x0074de52,
1368        0xffa19f4c, 0xff729059, 0x007c7e90,
1369        0x00000003,//output gain
1370        0x00005105,//header
1371        0x00000292,//input gain
1372        0x00e4320a, 0xff41d2d9, 0x004911ac,
1373        0x005dd9e3, 0xff4c7d80, 0x0052103e,
1374        0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
1375        0xffc4b414, 0xff68582c, 0x006b38e5,
1376        0xffabb861, 0xff704bec, 0x0074de52,
1377        0xffa19f4c, 0xff729059, 0x007c7e90,
1378        0x00000001//output gain
1379};
1380
1381static u32 coef_32to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1382        0x000c6102,//header
1383        0x0001d727,//input gain
1384        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1385        0x00e55557, 0xffcadd5b, 0x003d80ba,
1386        0x00d13397, 0xfff232f8, 0x00683337,
1387        0x00000002,//output gain
1388        0x0018a102,//header
1389        0x000005d6,//input gain
1390        0x00c6543e, 0xff342935, 0x0052f116,
1391        0x000a1d78, 0xff3330c0, 0x005f88a3,
1392        0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
1393        0x00000003,//output gain
1394        0x00230204,//farrow
1395        0x000aaaab,
1396        0xffaaaaab,
1397        0xfffaaaab,
1398        0x00555555,
1399        0xff600000,
1400        0xfff55555,
1401        0x00155555,
1402        0x00055555,
1403        0xffeaaaab,
1404        0x00200000,
1405        0x00005102,//header
1406        0x000005f3,//input gain
1407        0x00d816d6, 0xff385383, 0x004fe566,
1408        0x003c548d, 0xff38c23d, 0x005d0b1c,
1409        0xfff02f7d, 0xff31e983, 0x0072d65d,
1410        0x00000001//output gain
1411};
1412
1413static u32 coef_32to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1414        0x0000a105,//header
1415        0x00000292,//input gain
1416        0x00e4320a, 0xff41d2d9, 0x004911ac,
1417        0x005dd9e3, 0xff4c7d80, 0x0052103e,
1418        0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
1419        0xffc4b414, 0xff68582c, 0x006b38e5,
1420        0xffabb861, 0xff704bec, 0x0074de52,
1421        0xffa19f4c, 0xff729059, 0x007c7e90,
1422        0x00000003//output gain
1423};
1424
1425static u32 coef_32to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1426        0x000c6102,//header
1427        0x0001d727,//input gain
1428        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1429        0x00e55557, 0xffcadd5b, 0x003d80ba,
1430        0x00d13397, 0xfff232f8, 0x00683337,
1431        0x00000002,//output gain
1432        0x0018a102,//header
1433        0x000005d6,//input gain
1434        0x00c6543e, 0xff342935, 0x0052f116,
1435        0x000a1d78, 0xff3330c0, 0x005f88a3,
1436        0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
1437        0x00000003,//output gain
1438        0x00000204,//farrow
1439        0x000aaaab,
1440        0xffaaaaab,
1441        0xfffaaaab,
1442        0x00555555,
1443        0xff600000,
1444        0xfff55555,
1445        0x00155555,
1446        0x00055555,
1447        0xffeaaaab,
1448        0x00200000
1449};
1450
1451static u32 coef_32to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1452        0x000c6102,//header
1453        0x0001d727,//input gain
1454        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1455        0x00e55557, 0xffcadd5b, 0x003d80ba,
1456        0x00d13397, 0xfff232f8, 0x00683337,
1457        0x00000002,//output gain
1458        0x0000a102,//header
1459        0x000005d6,//input gain
1460        0x00c6543e, 0xff342935, 0x0052f116,
1461        0x000a1d78, 0xff3330c0, 0x005f88a3,
1462        0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
1463        0x00000003//output gain
1464};
1465
1466static u32 coef_44to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1467        0x00120104,//IIR Filter
1468        0x00000af2,//input gain
1469        0x0057eebe, 0xff1e9863, 0x00652604,
1470        0xff7206ea, 0xff22ad7e, 0x006d47e1,
1471        0xff42a4d7, 0xff26e722, 0x0075fd83,
1472        0xff352f66, 0xff29312b, 0x007b986b,
1473        0xff310a07, 0xff296f51, 0x007eca7c,
1474        0x00000001,//output gain
1475        0x001d9204,//Farrow Filter + decimation
1476        0x000aaaab,
1477        0xffaaaaab,
1478        0xfffaaaab,
1479        0x00555555,
1480        0xff600000,
1481        0xfff55555,
1482        0x00155555,
1483        0x00055555,
1484        0xffeaaaab,
1485        0x00200000,
1486        0x00005105,//IIR Filter + Decimator
1487        0x0000d649,//input gain
1488        0x00e87afb, 0xff5f69d0, 0x003df3cf,
1489        0x007ce488, 0xff99a5c8, 0x0056a6a0,
1490        0x00344928, 0xffcba3e5, 0x006be470,
1491        0x00137aa7, 0xffe60276, 0x00773410,
1492        0x0005fa2a, 0xfff1ac11, 0x007c795b,
1493        0x00012d36, 0xfff5eca2, 0x007f10ef,
1494        0x00000001//output gain
1495};
1496
1497static u32 coef_44to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1498        0x000c5102,//header
1499        0x000013d9,//input gain
1500        0x00ebd477, 0xff4ce383, 0x0042049d,
1501        0x0089c278, 0xff54414d, 0x00531ded,
1502        0x004a5e07, 0xff53cf41, 0x006efbdc,
1503        0x00000001,//output gain
1504        0x00005102,//header
1505        0x0001d727,//input gain
1506        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1507        0x00e55557, 0xffcadd5b, 0x003d80ba,
1508        0x00d13397, 0xfff232f8, 0x00683337,
1509        0x00000001//output gain
1510};
1511
1512static u32 coef_44to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1513        0x00126104,//IIR Filter + interpolation
1514        0x00000af2,//input gain
1515        0x0057eebe, 0xff1e9863, 0x00652604,
1516        0xff7206ea, 0xff22ad7e, 0x006d47e1,
1517        0xff42a4d7, 0xff26e722, 0x0075fd83,
1518        0xff352f66, 0xff29312b, 0x007b986b,
1519        0xff310a07, 0xff296f51, 0x007eca7c,
1520        0x00000002,//output gain
1521        0x001d9204,//Farrow Filter + decimation
1522        0x000aaaab,
1523        0xffaaaaab,
1524        0xfffaaaab,
1525        0x00555555,
1526        0xff600000,
1527        0xfff55555,
1528        0x00155555,
1529        0x00055555,
1530        0xffeaaaab,
1531        0x00200000,
1532        0x00005105,//IIR Filter + Decimator
1533        0x0000d649,//input gain
1534        0x00e87afb, 0xff5f69d0, 0x003df3cf,
1535        0x007ce488, 0xff99a5c8, 0x0056a6a0,
1536        0x00344928, 0xffcba3e5, 0x006be470,
1537        0x00137aa7, 0xffe60276, 0x00773410,
1538        0x0005fa2a, 0xfff1ac11, 0x007c795b,
1539        0x00012d36, 0xfff5eca2, 0x007f10ef,
1540        0x00000001//output gain
1541};
1542
1543static u32 coef_44to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1544        0x00005102,//header
1545        0x0001d727,//input gain
1546        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1547        0x00e55557, 0xffcadd5b, 0x003d80ba,
1548        0x00d13397, 0xfff232f8, 0x00683337,
1549        0x00000001//output gain
1550};
1551
1552static u32 coef_44to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1553        0x000c6102,//header
1554        0x00001685,//input gain
1555        0x00f53ae9, 0xff52f196, 0x003e3e08,
1556        0x00b9f857, 0xff5d8985, 0x0050070a,
1557        0x008c3e86, 0xff6053f0, 0x006d98ef,
1558        0x00000002,//output gain
1559        0x00175204,//farrow
1560        0x000aaaab,
1561        0xffaaaaab,
1562        0xfffaaaab,
1563        0x00555555,
1564        0xff600000,
1565        0xfff55555,
1566        0x00155555,
1567        0x00055555,
1568        0xffeaaaab,
1569        0x00200000,
1570        0x00005102,//header
1571        0x0001d727,//input gain
1572        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1573        0x00e55557, 0xffcadd5b, 0x003d80ba,
1574        0x00d13397, 0xfff232f8, 0x00683337,
1575        0x00000001//output gain
1576};
1577
1578static u32 coef_44to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1579        0x000c6102,//header
1580        0x0000015f,//input gain
1581        0x00a7909c, 0xff241c71, 0x005f5e00,
1582        0xffca77f4, 0xff20dd50, 0x006855eb,
1583        0xff86c552, 0xff18137a, 0x00773648,
1584        0x00000002,//output gain
1585        0x00186102,//header
1586        0x000005f3,//input gain
1587        0x00d816d6, 0xff385383, 0x004fe566,
1588        0x003c548d, 0xff38c23d, 0x005d0b1c,
1589        0xfff02f7d, 0xff31e983, 0x0072d65d,
1590        0x00000002,//output gain
1591        0x00239204,//farrow
1592        0x000aaaab,
1593        0xffaaaaab,
1594        0xfffaaaab,
1595        0x00555555,
1596        0xff600000,
1597        0xfff55555,
1598        0x00155555,
1599        0x00055555,
1600        0xffeaaaab,
1601        0x00200000,
1602        0x00005102,//header
1603        0x0001d727,//input gain
1604        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1605        0x00e55557, 0xffcadd5b, 0x003d80ba,
1606        0x00d13397, 0xfff232f8, 0x00683337,
1607        0x00000001//output gain
1608};
1609
1610static u32 coef_44to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1611        0x000c6102,//header
1612        0x0001d727,//input gain
1613        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1614        0x00e55557, 0xffcadd5b, 0x003d80ba,
1615        0x00d13397, 0xfff232f8, 0x00683337,
1616        0x00000002,//output gain
1617        0x00186102,//header
1618        0x000013d9,//input gain
1619        0x00ebd477, 0xff4ce383, 0x0042049d,
1620        0x0089c278, 0xff54414d, 0x00531ded,
1621        0x004a5e07, 0xff53cf41, 0x006efbdc,
1622        0x00000002,//output gain
1623        0x00235204,//farrow
1624        0x000aaaab,
1625        0xffaaaaab,
1626        0xfffaaaab,
1627        0x00555555,
1628        0xff600000,
1629        0xfff55555,
1630        0x00155555,
1631        0x00055555,
1632        0xffeaaaab,
1633        0x00200000,
1634        0x00005102,//header
1635        0x0001d029,//input gain
1636        0x00f2a98b, 0xff92aa71, 0x001fcd16,
1637        0x00ae9004, 0xffb85140, 0x0041813a,
1638        0x007f8ed1, 0xffd585fc, 0x006a69e6,
1639        0x00000001//output gain
1640};
1641
1642static u32 coef_44to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1643        0x00006102,//header
1644        0x0001d727,//input gain
1645        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1646        0x00e55557, 0xffcadd5b, 0x003d80ba,
1647        0x00d13397, 0xfff232f8, 0x00683337,
1648        0x00000002//output gain
1649};
1650
1651static u32 coef_44to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1652        0x000c6102,//header
1653        0x0001d727,//input gain
1654        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1655        0x00e55557, 0xffcadd5b, 0x003d80ba,
1656        0x00d13397, 0xfff232f8, 0x00683337,
1657        0x00000002,//output gain
1658        0x00186102,//header
1659        0x000013d9,//input gain
1660        0x00ebd477, 0xff4ce383, 0x0042049d,
1661        0x0089c278, 0xff54414d, 0x00531ded,
1662        0x004a5e07, 0xff53cf41, 0x006efbdc,
1663        0x00000002,//output gain
1664        0x00005204,//farrow
1665        0x000aaaab,
1666        0xffaaaaab,
1667        0xfffaaaab,
1668        0x00555555,
1669        0xff600000,
1670        0xfff55555,
1671        0x00155555,
1672        0x00055555,
1673        0xffeaaaab,
1674        0x00200000
1675};
1676
1677static u32 coef_44to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1678        0x000c6102,//header
1679        0x0001d727,//input gain
1680        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1681        0x00e55557, 0xffcadd5b, 0x003d80ba,
1682        0x00d13397, 0xfff232f8, 0x00683337,
1683        0x00000002,//output gain
1684        0x00006102,//header
1685        0x000013d9,//input gain
1686        0x00ebd477, 0xff4ce383, 0x0042049d,
1687        0x0089c278, 0xff54414d, 0x00531ded,
1688        0x004a5e07, 0xff53cf41, 0x006efbdc,
1689        0x00000002//output gain
1690};
1691
1692static u32 coef_44to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1693        0x000c6102,//header
1694        0x0001d727,//input gain
1695        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1696        0x00e55557, 0xffcadd5b, 0x003d80ba,
1697        0x00d13397, 0xfff232f8, 0x00683337,
1698        0x00000002,//output gain
1699        0x00186102,//header
1700        0x000013d9,//input gain
1701        0x00ebd477, 0xff4ce383, 0x0042049d,
1702        0x0089c278, 0xff54414d, 0x00531ded,
1703        0x004a5e07, 0xff53cf41, 0x006efbdc,
1704        0x00000002,//output gain
1705        0x00246102,//header
1706        0x0000010a,//input gain
1707        0x00c93dc4, 0xff26f5f6, 0x005d1041,
1708        0x001002c4, 0xff245b76, 0x00666002,
1709        0xffc30a45, 0xff1baecd, 0x00765921,
1710        0x00000002,//output gain
1711        0x00005204,//farrow
1712        0x000aaaab,
1713        0xffaaaaab,
1714        0xfffaaaab,
1715        0x00555555,
1716        0xff600000,
1717        0xfff55555,
1718        0x00155555,
1719        0x00055555,
1720        0xffeaaaab,
1721        0x00200000
1722};
1723
1724static u32 coef_48to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1725        0x000c9102,//IIR Filter + Decimator
1726        0x00000e00,//input gain
1727        0x00e2e000, 0xff6e1a00, 0x002aaa00,
1728        0x00610a00, 0xff5dda00, 0x003ccc00,
1729        0x00163a00, 0xff3c0400, 0x00633200,
1730        0x00000001,//output gain
1731        0x00005105,//IIR Filter + Decimator
1732        0x0000d649,//input gain
1733        0x00e87afb, 0xff5f69d0, 0x003df3cf,
1734        0x007ce488, 0xff99a5c8, 0x0056a6a0,
1735        0x00344928, 0xffcba3e5, 0x006be470,
1736        0x00137aa7, 0xffe60276, 0x00773410,
1737        0x0005fa2a, 0xfff1ac11, 0x007c795b,
1738        0x00012d36, 0xfff5eca2, 0x007f10ef,
1739        0x00000001//output gain
1740};
1741
1742static u32 coef_48to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1743        0x000c6102,//header
1744        0x000000af,//input gain
1745        0x00c65663, 0xff23d2ce, 0x005f97d6,
1746        0x00086ad6, 0xff20ec4f, 0x00683201,
1747        0xffbbbef6, 0xff184447, 0x00770963,
1748        0x00000002,//output gain
1749        0x00175204,//farrow
1750        0x000aaaab,
1751        0xffaaaaab,
1752        0xfffaaaab,
1753        0x00555555,
1754        0xff600000,
1755        0xfff55555,
1756        0x00155555,
1757        0x00055555,
1758        0xffeaaaab,
1759        0x00200000,
1760        0x00235102,//header
1761        0x000013d9,//input gain
1762        0x00ebd477, 0xff4ce383, 0x0042049d,
1763        0x0089c278, 0xff54414d, 0x00531ded,
1764        0x004a5e07, 0xff53cf41, 0x006efbdc,
1765        0x00000001,//output gain
1766        0x00005102,//header
1767        0x0001d727,//input gain
1768        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1769        0x00e55557, 0xffcadd5b, 0x003d80ba,
1770        0x00d13397, 0xfff232f8, 0x00683337,
1771        0x00000001//output gain
1772};
1773
1774static u32 coef_48to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1775        0x00009105,//IIR Filter + Decimator
1776        0x00000784,//input gain
1777        0x00cc516e, 0xff2c9639, 0x005ad5b3,
1778        0x0013ad0d, 0xff3d4799, 0x0063ce75,
1779        0xffb6f398, 0xff5138d1, 0x006e9e1f,
1780        0xff9186e5, 0xff5f96a4, 0x0076a86e,
1781        0xff82089c, 0xff676b81, 0x007b9f8a,
1782        0xff7c48a5, 0xff6a31e7, 0x007ebb7b,
1783        0x00000001//output gain
1784};
1785
1786static u32 coef_48to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1787        0x000f6103,//header
1788        0x000001e0,//input gain
1789        0x00de44c0, 0xff380b7f, 0x004ffc73,
1790        0x00494b44, 0xff3d493a, 0x005908bf,
1791        0xffe9a3c8, 0xff425647, 0x006745f7,
1792        0xffc42d61, 0xff40a6c7, 0x00776709,
1793        0x00000002,//output gain
1794        0x001a5204,//farrow
1795        0x000aaaab,
1796        0xffaaaaab,
1797        0xfffaaaab,
1798        0x00555555,
1799        0xff600000,
1800        0xfff55555,
1801        0x00155555,
1802        0x00055555,
1803        0xffeaaaab,
1804        0x00200000,
1805        0x00005102,//header
1806        0x0001d727,//input gain
1807        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1808        0x00e55557, 0xffcadd5b, 0x003d80ba,
1809        0x00d13397, 0xfff232f8, 0x00683337,
1810        0x00000001//output gain
1811};
1812
1813static u32 coef_48to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1814        0x00005102,//header
1815        0x0001d727,//input gain
1816        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1817        0x00e55557, 0xffcadd5b, 0x003d80ba,
1818        0x00d13397, 0xfff232f8, 0x00683337,
1819        0x00000001//output gain
1820};
1821
1822static u32 coef_48to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1823        0x00156105,//header
1824        0x00000292,//input gain
1825        0x00e4320a, 0xff41d2d9, 0x004911ac,
1826        0x005dd9e3, 0xff4c7d80, 0x0052103e,
1827        0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
1828        0xffc4b414, 0xff68582c, 0x006b38e5,
1829        0xffabb861, 0xff704bec, 0x0074de52,
1830        0xffa19f4c, 0xff729059, 0x007c7e90,
1831        0x00000002,//output gain
1832        0x00009105,//header
1833        0x00000292,//input gain
1834        0x00e4320a, 0xff41d2d9, 0x004911ac,
1835        0x005dd9e3, 0xff4c7d80, 0x0052103e,
1836        0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
1837        0xffc4b414, 0xff68582c, 0x006b38e5,
1838        0xffabb861, 0xff704bec, 0x0074de52,
1839        0xffa19f4c, 0xff729059, 0x007c7e90,
1840        0x00000001//output gain
1841};
1842
1843static u32 coef_48to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1844        0x000c6102,//header
1845        0x0001d029,//input gain
1846        0x00f2a98b, 0xff92aa71, 0x001fcd16,
1847        0x00ae9004, 0xffb85140, 0x0041813a,
1848        0x007f8ed1, 0xffd585fc, 0x006a69e6,
1849        0x00000002,//output gain
1850        0x001b6103,//header
1851        0x000001e0,//input gain
1852        0x00de44c0, 0xff380b7f, 0x004ffc73,
1853        0x00494b44, 0xff3d493a, 0x005908bf,
1854        0xffe9a3c8, 0xff425647, 0x006745f7,
1855        0xffc42d61, 0xff40a6c7, 0x00776709,
1856        0x00000002,//output gain
1857        0x00265204,//farrow
1858        0x000aaaab,
1859        0xffaaaaab,
1860        0xfffaaaab,
1861        0x00555555,
1862        0xff600000,
1863        0xfff55555,
1864        0x00155555,
1865        0x00055555,
1866        0xffeaaaab,
1867        0x00200000,
1868        0x00005102,//header
1869        0x0001d727,//input gain
1870        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1871        0x00e55557, 0xffcadd5b, 0x003d80ba,
1872        0x00d13397, 0xfff232f8, 0x00683337,
1873        0x00000001//output gain
1874};
1875
1876static u32 coef_48to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1877        0x000c6102,//header
1878        0x0001d727,//input gain
1879        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1880        0x00e55557, 0xffcadd5b, 0x003d80ba,
1881        0x00d13397, 0xfff232f8, 0x00683337,
1882        0x00000002,//output gain
1883        0x00186102,//header
1884        0x000013d9,//input gain
1885        0x00ebd477, 0xff4ce383, 0x0042049d,
1886        0x0089c278, 0xff54414d, 0x00531ded,
1887        0x004a5e07, 0xff53cf41, 0x006efbdc,
1888        0x00000002,//output gain
1889        0x00230204,//farrow
1890        0x000aaaab,
1891        0xffaaaaab,
1892        0xfffaaaab,
1893        0x00555555,
1894        0xff600000,
1895        0xfff55555,
1896        0x00155555,
1897        0x00055555,
1898        0xffeaaaab,
1899        0x00200000,
1900        0x00005102,//header
1901        0x00001685,//input gain
1902        0x00f53ae9, 0xff52f196, 0x003e3e08,
1903        0x00b9f857, 0xff5d8985, 0x0050070a,
1904        0x008c3e86, 0xff6053f0, 0x006d98ef,
1905        0x00000001//output gain
1906};
1907
1908static u32 coef_48to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1909        0x00006102,//header
1910        0x0001d727,//input gain
1911        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1912        0x00e55557, 0xffcadd5b, 0x003d80ba,
1913        0x00d13397, 0xfff232f8, 0x00683337,
1914        0x00000002//output gain
1915};
1916
1917static u32 coef_48to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1918        0x000c6102,//header
1919        0x0001d727,//input gain
1920        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1921        0x00e55557, 0xffcadd5b, 0x003d80ba,
1922        0x00d13397, 0xfff232f8, 0x00683337,
1923        0x00000002,//output gain
1924        0x00186102,//header
1925        0x000013d9,//input gain
1926        0x00ebd477, 0xff4ce383, 0x0042049d,
1927        0x0089c278, 0xff54414d, 0x00531ded,
1928        0x004a5e07, 0xff53cf41, 0x006efbdc,
1929        0x00000002,//output gain
1930        0x00246102,//header
1931        0x0000010a,//input gain
1932        0x00c93dc4, 0xff26f5f6, 0x005d1041,
1933        0x001002c4, 0xff245b76, 0x00666002,
1934        0xffc30a45, 0xff1baecd, 0x00765921,
1935        0x00000002,//output gain
1936        0x002f0204,//farrow
1937        0x000aaaab,
1938        0xffaaaaab,
1939        0xfffaaaab,
1940        0x00555555,
1941        0xff600000,
1942        0xfff55555,
1943        0x00155555,
1944        0x00055555,
1945        0xffeaaaab,
1946        0x00200000,
1947        0x00005102,//header
1948        0x00000138,//input gain
1949        0x00d5d232, 0xff2a3bf8, 0x005a785c,
1950        0x0034001b, 0xff283109, 0x006462a6,
1951        0xffe6746a, 0xff1fb09c, 0x00758a91,
1952        0x00000001//output gain
1953};
1954
1955static u32 coef_48to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1956        0x000c6102,//header
1957        0x0001d727,//input gain
1958        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1959        0x00e55557, 0xffcadd5b, 0x003d80ba,
1960        0x00d13397, 0xfff232f8, 0x00683337,
1961        0x00000002,//output gain
1962        0x00006102,//header
1963        0x000013d9,//input gain
1964        0x00ebd477, 0xff4ce383, 0x0042049d,
1965        0x0089c278, 0xff54414d, 0x00531ded,
1966        0x004a5e07, 0xff53cf41, 0x006efbdc,
1967        0x00000002//output gain
1968};
1969
1970static u32 coef_88to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1971        0x000c0102,//header
1972        0x00000057,//input gain
1973        0x00a8e717, 0xff1c748d, 0x0065b976,
1974        0xffcbccab, 0xff190aff, 0x006cc1cf,
1975        0xff871ce1, 0xff10d878, 0x0078cfc5,
1976        0x00000001,//output gain
1977        0x00179204,//farrow
1978        0x000aaaab,
1979        0xffaaaaab,
1980        0xfffaaaab,
1981        0x00555555,
1982        0xff600000,
1983        0xfff55555,
1984        0x00155555,
1985        0x00055555,
1986        0xffeaaaab,
1987        0x00200000,
1988        0x00235102,//header
1989        0x000013d9,//input gain
1990        0x00ebd477, 0xff4ce383, 0x0042049d,
1991        0x0089c278, 0xff54414d, 0x00531ded,
1992        0x004a5e07, 0xff53cf41, 0x006efbdc,
1993        0x00000001,//output gain
1994        0x00005102,//header
1995        0x0001d727,//input gain
1996        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1997        0x00e55557, 0xffcadd5b, 0x003d80ba,
1998        0x00d13397, 0xfff232f8, 0x00683337,
1999        0x00000001//output gain
2000};

2001
2002static u32 coef_88to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2003        0x000c5102,//header
2004        0x0000010a,//input gain
2005        0x00c93dc4, 0xff26f5f6, 0x005d1041,
2006        0x001002c4, 0xff245b76, 0x00666002,
2007        0xffc30a45, 0xff1baecd, 0x00765921,
2008        0x00000001,//output gain
2009        0x00185102,//header
2010        0x000013d9,//input gain
2011        0x00ebd477, 0xff4ce383, 0x0042049d,
2012        0x0089c278, 0xff54414d, 0x00531ded,
2013        0x004a5e07, 0xff53cf41, 0x006efbdc,
2014        0x00000001,//output gain
2015        0x00005102,//header
2016        0x0001d727,//input gain
2017        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2018        0x00e55557, 0xffcadd5b, 0x003d80ba,
2019        0x00d13397, 0xfff232f8, 0x00683337,
2020        0x00000001//output gain
2021};
2022
2023static u32 coef_88to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2024        0x000c0102,//header
2025        0x000005f3,//input gain
2026        0x00d816d6, 0xff385383, 0x004fe566,
2027        0x003c548d, 0xff38c23d, 0x005d0b1c,
2028        0xfff02f7d, 0xff31e983, 0x0072d65d,
2029        0x00000001,//output gain
2030        0x00179204,//farrow
2031        0x000aaaab,
2032        0xffaaaaab,
2033        0xfffaaaab,
2034        0x00555555,
2035        0xff600000,
2036        0xfff55555,
2037        0x00155555,
2038        0x00055555,
2039        0xffeaaaab,
2040        0x00200000,
2041        0x00005102,//header
2042        0x0001d727,//input gain
2043        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2044        0x00e55557, 0xffcadd5b, 0x003d80ba,
2045        0x00d13397, 0xfff232f8, 0x00683337,
2046        0x00000001//output gain
2047};
2048
2049static u32 coef_88to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2050        0x000c5102,//header
2051        0x000013d9,//input gain
2052        0x00ebd477, 0xff4ce383, 0x0042049d,
2053        0x0089c278, 0xff54414d, 0x00531ded,
2054        0x004a5e07, 0xff53cf41, 0x006efbdc,
2055        0x00000001,//output gain
2056        0x00005102,//header
2057        0x0001d727,//input gain
2058        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2059        0x00e55557, 0xffcadd5b, 0x003d80ba,
2060        0x00d13397, 0xfff232f8, 0x00683337,
2061        0x00000001//output gain
2062};
2063
2064static u32 coef_88to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2065        0x000c0102,//header
2066        0x00001685,//input gain
2067        0x00f53ae9, 0xff52f196, 0x003e3e08,
2068        0x00b9f857, 0xff5d8985, 0x0050070a,
2069        0x008c3e86, 0xff6053f0, 0x006d98ef,
2070        0x00000001,//output gain
2071        0x00175204,//farrow
2072        0x000aaaab,
2073        0xffaaaaab,
2074        0xfffaaaab,
2075        0x00555555,
2076        0xff600000,
2077        0xfff55555,
2078        0x00155555,
2079        0x00055555,
2080        0xffeaaaab,
2081        0x00200000,
2082        0x00005102,//header
2083        0x0001d727,//input gain
2084        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2085        0x00e55557, 0xffcadd5b, 0x003d80ba,
2086        0x00d13397, 0xfff232f8, 0x00683337,
2087        0x00000001//output gain
2088};
2089
2090static u32 coef_88to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2091        0x000c6102,//header
2092        0x000005f3,//input gain
2093        0x00d816d6, 0xff385383, 0x004fe566,
2094        0x003c548d, 0xff38c23d, 0x005d0b1c,
2095        0xfff02f7d, 0xff31e983, 0x0072d65d,
2096        0x00000002,//output gain
2097        0x00179204,//farrow
2098        0x000aaaab,
2099        0xffaaaaab,
2100        0xfffaaaab,
2101        0x00555555,
2102        0xff600000,
2103        0xfff55555,
2104        0x00155555,
2105        0x00055555,
2106        0xffeaaaab,
2107        0x00200000,
2108        0x00005102,//header
2109        0x0001d727,//input gain
2110        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2111        0x00e55557, 0xffcadd5b, 0x003d80ba,
2112        0x00d13397, 0xfff232f8, 0x00683337,
2113        0x00000001//output gain
2114};
2115
2116static u32 coef_88to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2117        0x00005102,//header
2118        0x0001d727,//input gain
2119        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2120        0x00e55557, 0xffcadd5b, 0x003d80ba,
2121        0x00d13397, 0xfff232f8, 0x00683337,
2122        0x00000001//output gain
2123};
2124
2125static u32 coef_88to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2126        0x000c6102,//header
2127        0x00001685,//input gain
2128        0x00f53ae9, 0xff52f196, 0x003e3e08,
2129        0x00b9f857, 0xff5d8985, 0x0050070a,
2130        0x008c3e86, 0xff6053f0, 0x006d98ef,
2131        0x00000002,//output gain
2132        0x00175204,//farrow
2133        0x000aaaab,
2134        0xffaaaaab,
2135        0xfffaaaab,
2136        0x00555555,
2137        0xff600000,
2138        0xfff55555,
2139        0x00155555,
2140        0x00055555,
2141        0xffeaaaab,
2142        0x00200000,
2143        0x00005102,//header
2144        0x0001d727,//input gain
2145        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2146        0x00e55557, 0xffcadd5b, 0x003d80ba,
2147        0x00d13397, 0xfff232f8, 0x00683337,
2148        0x00000001//output gain
2149};
2150
2151static u32 coef_88to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2152        0x000c6102,//header
2153        0x000013d9,//input gain
2154        0x00ebd477, 0xff4ce383, 0x0042049d,
2155        0x0089c278, 0xff54414d, 0x00531ded,
2156        0x004a5e07, 0xff53cf41, 0x006efbdc,
2157        0x00000002,//output gain
2158        0x00005204,//farrow
2159        0x000aaaab,
2160        0xffaaaaab,
2161        0xfffaaaab,
2162        0x00555555,
2163        0xff600000,
2164        0xfff55555,
2165        0x00155555,
2166        0x00055555,
2167        0xffeaaaab,
2168        0x00200000
2169};
2170
2171static u32 coef_88to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2172        0x00006102,//header
2173        0x000013d9,//input gain
2174        0x00ebd477, 0xff4ce383, 0x0042049d,
2175        0x0089c278, 0xff54414d, 0x00531ded,
2176        0x004a5e07, 0xff53cf41, 0x006efbdc,
2177        0x00000002//output gain
2178};
2179
2180static u32 coef_88to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2181        0x000c6102,//header
2182        0x000013d9,//input gain
2183        0x00ebd477, 0xff4ce383, 0x0042049d,
2184        0x0089c278, 0xff54414d, 0x00531ded,
2185        0x004a5e07, 0xff53cf41, 0x006efbdc,
2186        0x00000002,//output gain
2187        0x00186102,//header
2188        0x0000010a,//input gain
2189        0x00c93dc4, 0xff26f5f6, 0x005d1041,
2190        0x001002c4, 0xff245b76, 0x00666002,
2191        0xffc30a45, 0xff1baecd, 0x00765921,
2192        0x00000002,//output gain
2193        0x00005204,//farrow
2194        0x000aaaab,
2195        0xffaaaaab,
2196        0xfffaaaab,
2197        0x00555555,
2198        0xff600000,
2199        0xfff55555,
2200        0x00155555,
2201        0x00055555,
2202        0xffeaaaab,
2203        0x00200000
2204};
2205
2206static u32 coef_96to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2207        0x000c9102,//header
2208        0x0000007d,//input gain
2209        0x007d1f20, 0xff1a540e, 0x00678bf9,
2210        0xff916625, 0xff16b0ff, 0x006e433a,
2211        0xff5af660, 0xff0eb91f, 0x00797356,
2212        0x00000001,//output gain
2213        0x00185102,//header
2214        0x000013d9,//input gain
2215        0x00ebd477, 0xff4ce383, 0x0042049d,
2216        0x0089c278, 0xff54414d, 0x00531ded,
2217        0x004a5e07, 0xff53cf41, 0x006efbdc,
2218        0x00000001,//output gain
2219        0x00005102,//header
2220        0x0001d727,//input gain
2221        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2222        0x00e55557, 0xffcadd5b, 0x003d80ba,
2223        0x00d13397, 0xfff232f8, 0x00683337,
2224        0x00000001//output gain
2225};
2226
2227static u32 coef_96to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2228        0x000c0102,//header
2229        0x000000af,//input gain
2230        0x00c65663, 0xff23d2ce, 0x005f97d6,
2231        0x00086ad6, 0xff20ec4f, 0x00683201,
2232        0xffbbbef6, 0xff184447, 0x00770963,
2233        0x00000001,//output gain
2234        0x00175204,//farrow
2235        0x000aaaab,
2236        0xffaaaaab,
2237        0xfffaaaab,
2238        0x00555555,
2239        0xff600000,
2240        0xfff55555,
2241        0x00155555,
2242        0x00055555,
2243        0xffeaaaab,
2244        0x00200000,
2245        0x00235102,//header
2246        0x000013d9,//input gain
2247        0x00ebd477, 0xff4ce383, 0x0042049d,
2248        0x0089c278, 0xff54414d, 0x00531ded,
2249        0x004a5e07, 0xff53cf41, 0x006efbdc,
2250        0x00000001,//output gain
2251        0x00005102,//header
2252        0x0001d727,//input gain
2253        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2254        0x00e55557, 0xffcadd5b, 0x003d80ba,
2255        0x00d13397, 0xfff232f8, 0x00683337,
2256        0x00000001//output gain
2257};
2258
2259static u32 coef_96to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2260        0x000c9102,//header
2261        0x000005d6,//input gain
2262        0x00c6543e, 0xff342935, 0x0052f116,
2263        0x000a1d78, 0xff3330c0, 0x005f88a3,
2264        0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
2265        0x00000001,//output gain
2266        0x00005102,//header
2267        0x0001d727,//input gain
2268        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2269        0x00e55557, 0xffcadd5b, 0x003d80ba,
2270        0x00d13397, 0xfff232f8, 0x00683337,
2271        0x00000001//output gain
2272};
2273
2274static u32 coef_96to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2275        0x000c6102,//header
2276        0x000000af,//input gain
2277        0x00c65663, 0xff23d2ce, 0x005f97d6,
2278        0x00086ad6, 0xff20ec4f, 0x00683201,
2279        0xffbbbef6, 0xff184447, 0x00770963,
2280        0x00000002,//output gain
2281        0x00175204,//farrow
2282        0x000aaaab,
2283        0xffaaaaab,
2284        0xfffaaaab,
2285        0x00555555,
2286        0xff600000,
2287        0xfff55555,
2288        0x00155555,
2289        0x00055555,
2290        0xffeaaaab,
2291        0x00200000,
2292        0x00235102,//header
2293        0x000013d9,//input gain
2294        0x00ebd477, 0xff4ce383, 0x0042049d,
2295        0x0089c278, 0xff54414d, 0x00531ded,
2296        0x004a5e07, 0xff53cf41, 0x006efbdc,
2297        0x00000001,//output gain
2298        0x00005102,//header
2299        0x0001d727,//input gain
2300        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2301        0x00e55557, 0xffcadd5b, 0x003d80ba,
2302        0x00d13397, 0xfff232f8, 0x00683337,
2303        0x00000001//output gain
2304};
2305
2306static u32 coef_96to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2307        0x000c5102,//header
2308        0x000013d9,//input gain
2309        0x00ebd477, 0xff4ce383, 0x0042049d,
2310        0x0089c278, 0xff54414d, 0x00531ded,
2311        0x004a5e07, 0xff53cf41, 0x006efbdc,
2312        0x00000001,//output gain
2313        0x00005102,//header
2314        0x0001d727,//input gain
2315        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2316        0x00e55557, 0xffcadd5b, 0x003d80ba,
2317        0x00d13397, 0xfff232f8, 0x00683337,
2318        0x00000001//output gain
2319};
2320
2321static u32 coef_96to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2322        0x00009105,//header
2323        0x00000292,//input gain
2324        0x00e4320a, 0xff41d2d9, 0x004911ac,
2325        0x005dd9e3, 0xff4c7d80, 0x0052103e,
2326        0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
2327        0xffc4b414, 0xff68582c, 0x006b38e5,
2328        0xffabb861, 0xff704bec, 0x0074de52,
2329        0xffa19f4c, 0xff729059, 0x007c7e90,
2330        0x00000001//output gain
2331};
2332
2333static u32 coef_96to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2334        0x000f6103,//header
2335        0x000001e0,//input gain
2336        0x00de44c0, 0xff380b7f, 0x004ffc73,
2337        0x00494b44, 0xff3d493a, 0x005908bf,
2338        0xffe9a3c8, 0xff425647, 0x006745f7,
2339        0xffc42d61, 0xff40a6c7, 0x00776709,
2340        0x00000002,//output gain
2341        0x001a5204,//farrow
2342        0x000aaaab,
2343        0xffaaaaab,
2344        0xfffaaaab,
2345        0x00555555,
2346        0xff600000,
2347        0xfff55555,
2348        0x00155555,
2349        0x00055555,
2350        0xffeaaaab,
2351        0x00200000,
2352        0x00005102,//header
2353        0x0001d727,//input gain
2354        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2355        0x00e55557, 0xffcadd5b, 0x003d80ba,
2356        0x00d13397, 0xfff232f8, 0x00683337,
2357        0x00000001//output gain
2358};
2359
2360static u32 coef_96to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2361        0x00005102,//header
2362        0x0001d727,//input gain
2363        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2364        0x00e55557, 0xffcadd5b, 0x003d80ba,
2365        0x00d13397, 0xfff232f8, 0x00683337,
2366        0x00000001//output gain
2367};
2368
2369static u32 coef_96to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2370        0x000f6103,//header
2371        0x000001e0,//input gain
2372        0x00de44c0, 0xff380b7f, 0x004ffc73,
2373        0x00494b44, 0xff3d493a, 0x005908bf,
2374        0xffe9a3c8, 0xff425647, 0x006745f7,
2375        0xffc42d61, 0xff40a6c7, 0x00776709,
2376        0x00000002,//output gain
2377        0x001a0204,//farrow
2378        0x000aaaab,
2379        0xffaaaaab,
2380        0xfffaaaab,
2381        0x00555555,
2382        0xff600000,
2383        0xfff55555,
2384        0x00155555,
2385        0x00055555,
2386        0xffeaaaab,
2387        0x00200000,
2388        0x00005102,//header
2389        0x000013d9,//input gain
2390        0x00ebd477, 0xff4ce383, 0x0042049d,
2391        0x0089c278, 0xff54414d, 0x00531ded,
2392        0x004a5e07, 0xff53cf41, 0x006efbdc,
2393        0x00000001//output gain
2394};
2395
2396static u32 coef_96to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2397        0x000f6103,//header
2398        0x000001e0,//input gain
2399        0x00de44c0, 0xff380b7f, 0x004ffc73,
2400        0x00494b44, 0xff3d493a, 0x005908bf,
2401        0xffe9a3c8, 0xff425647, 0x006745f7,
2402        0xffc42d61, 0xff40a6c7, 0x00776709,
2403        0x00000002,//output gain
2404        0x001b6102,//header
2405        0x000000af,//input gain
2406        0x00c65663, 0xff23d2ce, 0x005f97d6,
2407        0x00086ad6, 0xff20ec4f, 0x00683201,
2408        0xffbbbef6, 0xff184447, 0x00770963,
2409        0x00000002,//output gain
2410        0x00260204,//farrow
2411        0x000aaaab,
2412        0xffaaaaab,
2413        0xfffaaaab,
2414        0x00555555,
2415        0xff600000,
2416        0xfff55555,
2417        0x00155555,
2418        0x00055555,
2419        0xffeaaaab,
2420        0x00200000,
2421        0x00005102,//header
2422        0x0000010a,//input gain
2423        0x00c93dc4, 0xff26f5f6, 0x005d1041,
2424        0x001002c4, 0xff245b76, 0x00666002,
2425        0xffc30a45, 0xff1baecd, 0x00765921,
2426        0x00000001//output gain
2427};
2428
2429static u32 coef_96to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2430        0x00006103,//header
2431        0x000001e0,//input gain
2432        0x00de44c0, 0xff380b7f, 0x004ffc73,
2433        0x00494b44, 0xff3d493a, 0x005908bf,
2434        0xffe9a3c8, 0xff425647, 0x006745f7,
2435        0xffc42d61, 0xff40a6c7, 0x00776709,
2436        0x00000002//output gain
2437};
2438
2439static u32 coef_176to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2440        0x000c0102,//header
2441        0x00000057,//input gain
2442        0x00a8e717, 0xff1c748d, 0x0065b976,
2443        0xffcbccab, 0xff190aff, 0x006cc1cf,
2444        0xff871ce1, 0xff10d878, 0x0078cfc5,
2445        0x00000001,//output gain
2446        0x00179204,//farrow
2447        0x000aaaab,
2448        0xffaaaaab,
2449        0xfffaaaab,
2450        0x00555555,
2451        0xff600000,
2452        0xfff55555,
2453        0x00155555,
2454        0x00055555,
2455        0xffeaaaab,
2456        0x00200000,
2457        0x00235102,//header
2458        0x000013d9,//input gain
2459        0x00ebd477, 0xff4ce383, 0x0042049d,
2460        0x0089c278, 0xff54414d, 0x00531ded,
2461        0x004a5e07, 0xff53cf41, 0x006efbdc,
2462        0x00000001,//output gain
2463        0x00005102,//header
2464        0x0001d727,//input gain
2465        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2466        0x00e55557, 0xffcadd5b, 0x003d80ba,
2467        0x00d13397, 0xfff232f8, 0x00683337,
2468        0x00000001//output gain
2469};
2470
2471static u32 coef_176to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2472        0x000c5102,//header
2473        0x0000010a,//input gain
2474        0x00c93dc4, 0xff26f5f6, 0x005d1041,
2475        0x001002c4, 0xff245b76, 0x00666002,
2476        0xffc30a45, 0xff1baecd, 0x00765921,
2477        0x00000001,//output gain
2478        0x00185102,//header
2479        0x000013d9,//input gain
2480        0x00ebd477, 0xff4ce383, 0x0042049d,
2481        0x0089c278, 0xff54414d, 0x00531ded,
2482        0x004a5e07, 0xff53cf41, 0x006efbdc,
2483        0x00000001,//output gain
2484        0x00005102,//header
2485        0x0001d727,//input gain
2486        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2487        0x00e55557, 0xffcadd5b, 0x003d80ba,
2488        0x00d13397, 0xfff232f8, 0x00683337,
2489        0x00000001//output gain
2490};
2491
2492static u32 coef_176to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2493        0x000c0102,//header
2494        0x00000138,//input gain
2495        0x00d5d232, 0xff2a3bf8, 0x005a785c,
2496        0x0034001b, 0xff283109, 0x006462a6,
2497        0xffe6746a, 0xff1fb09c, 0x00758a91,
2498        0x00000001,//output gain
2499        0x00175204,//farrow
2500        0x000aaaab,
2501        0xffaaaaab,
2502        0xfffaaaab,
2503        0x00555555,
2504        0xff600000,
2505        0xfff55555,
2506        0x00155555,
2507        0x00055555,
2508        0xffeaaaab,
2509        0x00200000,
2510        0x00235102,//header
2511        0x000013d9,//input gain
2512        0x00ebd477, 0xff4ce383, 0x0042049d,
2513        0x0089c278, 0xff54414d, 0x00531ded,
2514        0x004a5e07, 0xff53cf41, 0x006efbdc,
2515        0x00000001,//output gain
2516        0x00005102,//header
2517        0x0001d727,//input gain
2518        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2519        0x00e55557, 0xffcadd5b, 0x003d80ba,
2520        0x00d13397, 0xfff232f8, 0x00683337,
2521        0x00000001//output gain
2522};
2523
2524static u32 coef_176to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2525        0x000c0102,//header
2526        0x000005f3,//input gain
2527        0x00d816d6, 0xff385383, 0x004fe566,
2528        0x003c548d, 0xff38c23d, 0x005d0b1c,
2529        0xfff02f7d, 0xff31e983, 0x0072d65d,
2530        0x00000001,//output gain
2531        0x00179204,//farrow
2532        0x000aaaab,
2533        0xffaaaaab,
2534        0xfffaaaab,
2535        0x00555555,
2536        0xff600000,
2537        0xfff55555,
2538        0x00155555,
2539        0x00055555,
2540        0xffeaaaab,
2541        0x00200000,
2542        0x00005102,//header
2543        0x0001d727,//input gain
2544        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2545        0x00e55557, 0xffcadd5b, 0x003d80ba,
2546        0x00d13397, 0xfff232f8, 0x00683337,
2547        0x00000001//output gain
2548};
2549
2550static u32 coef_176to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2551        0x000c5102,//header
2552        0x000013d9,//input gain
2553        0x00ebd477, 0xff4ce383, 0x0042049d,
2554        0x0089c278, 0xff54414d, 0x00531ded,
2555        0x004a5e07, 0xff53cf41, 0x006efbdc,
2556        0x00000001,//output gain
2557        0x00005102,//header
2558        0x0001d727,//input gain
2559        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2560        0x00e55557, 0xffcadd5b, 0x003d80ba,
2561        0x00d13397, 0xfff232f8, 0x00683337,
2562        0x00000001//output gain
2563};
2564
2565static u32 coef_176to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2566        0x000c0102,//header
2567        0x00001685,//input gain
2568        0x00f53ae9, 0xff52f196, 0x003e3e08,
2569        0x00b9f857, 0xff5d8985, 0x0050070a,
2570        0x008c3e86, 0xff6053f0, 0x006d98ef,
2571        0x00000001,//output gain
2572        0x00175204,//farrow
2573        0x000aaaab,
2574        0xffaaaaab,
2575        0xfffaaaab,
2576        0x00555555,
2577        0xff600000,
2578        0xfff55555,
2579        0x00155555,
2580        0x00055555,
2581        0xffeaaaab,
2582        0x00200000,
2583        0x00005102,//header
2584        0x0001d727,//input gain
2585        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2586        0x00e55557, 0xffcadd5b, 0x003d80ba,
2587        0x00d13397, 0xfff232f8, 0x00683337,
2588        0x00000001//output gain
2589};
2590
2591static u32 coef_176to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2592        0x00005102,//header
2593        0x000013d9,//input gain
2594        0x00ebd477, 0xff4ce383, 0x0042049d,
2595        0x0089c278, 0xff54414d, 0x00531ded,
2596        0x004a5e07, 0xff53cf41, 0x006efbdc,
2597        0x00000001//output gain
2598};
2599
2600static u32 coef_176to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2601        0x000c6102,//header
2602        0x0000010a,//input gain
2603        0x00c93dc4, 0xff26f5f6, 0x005d1041,
2604        0x001002c4, 0xff245b76, 0x00666002,
2605        0xffc30a45, 0xff1baecd, 0x00765921,
2606        0x00000002,//output gain
2607        0x00175204,//farrow
2608        0x000aaaab,
2609        0xffaaaaab,
2610        0xfffaaaab,
2611        0x00555555,
2612        0xff600000,
2613        0xfff55555,
2614        0x00155555,
2615        0x00055555,
2616        0xffeaaaab,
2617        0x00200000,
2618        0x00005103,//header
2619        0x000001e0,//input gain
2620        0x00de44c0, 0xff380b7f, 0x004ffc73,
2621        0x00494b44, 0xff3d493a, 0x005908bf,
2622        0xffe9a3c8, 0xff425647, 0x006745f7,
2623        0xffc42d61, 0xff40a6c7, 0x00776709,
2624        0x00000001//output gain
2625};
2626
2627static u32 coef_176to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2628        0x000c6102,//header
2629        0x0000010a,//input gain
2630        0x00c93dc4, 0xff26f5f6, 0x005d1041,
2631        0x001002c4, 0xff245b76, 0x00666002,
2632        0xffc30a45, 0xff1baecd, 0x00765921,
2633        0x00000002,//output gain
2634        0x00005204,//farrow
2635        0x000aaaab,
2636        0xffaaaaab,
2637        0xfffaaaab,
2638        0x00555555,
2639        0xff600000,
2640        0xfff55555,
2641        0x00155555,
2642        0x00055555,
2643        0xffeaaaab,
2644        0x00200000
2645};
2646
2647static u32 coef_192to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2648        0x000c9102,//header
2649        0x0000007d,//input gain
2650        0x007d1f20, 0xff1a540e, 0x00678bf9,
2651        0xff916625, 0xff16b0ff, 0x006e433a,
2652        0xff5af660, 0xff0eb91f, 0x00797356,
2653        0x00000001,//output gain
2654        0x00185102,//header
2655        0x000013d9,//input gain
2656        0x00ebd477, 0xff4ce383, 0x0042049d,
2657        0x0089c278, 0xff54414d, 0x00531ded,
2658        0x004a5e07, 0xff53cf41, 0x006efbdc,
2659        0x00000001,//output gain
2660        0x00005102,//header
2661        0x0001d727,//input gain
2662        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2663        0x00e55557, 0xffcadd5b, 0x003d80ba,
2664        0x00d13397, 0xfff232f8, 0x00683337,
2665        0x00000001//output gain
2666};
2667
2668static u32 coef_192to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2669        0x000c0102,//header
2670        0x000000af,//input gain
2671        0x00c65663, 0xff23d2ce, 0x005f97d6,
2672        0x00086ad6, 0xff20ec4f, 0x00683201,
2673        0xffbbbef6, 0xff184447, 0x00770963,
2674        0x00000001,//output gain
2675        0x00175204,//farrow
2676        0x000aaaab,
2677        0xffaaaaab,
2678        0xfffaaaab,
2679        0x00555555,
2680        0xff600000,
2681        0xfff55555,
2682        0x00155555,
2683        0x00055555,
2684        0xffeaaaab,
2685        0x00200000,
2686        0x00235102,//header
2687        0x000013d9,//input gain
2688        0x00ebd477, 0xff4ce383, 0x0042049d,
2689        0x0089c278, 0xff54414d, 0x00531ded,
2690        0x004a5e07, 0xff53cf41, 0x006efbdc,
2691        0x00000001,//output gain
2692        0x00005102,//header
2693        0x0001d727,//input gain
2694        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2695        0x00e55557, 0xffcadd5b, 0x003d80ba,
2696        0x00d13397, 0xfff232f8, 0x00683337,
2697        0x00000001//output gain
2698};
2699
2700static u32 coef_192to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2701        0x000c5102,//header
2702        0x0000010a,//input gain
2703        0x00c93dc4, 0xff26f5f6, 0x005d1041,
2704        0x001002c4, 0xff245b76, 0x00666002,
2705        0xffc30a45, 0xff1baecd, 0x00765921,
2706        0x00000001,//output gain
2707        0x00185102,//header
2708        0x000013d9,//input gain
2709        0x00ebd477, 0xff4ce383, 0x0042049d,
2710        0x0089c278, 0xff54414d, 0x00531ded,
2711        0x004a5e07, 0xff53cf41, 0x006efbdc,
2712        0x00000001,//output gain
2713        0x00005102,//header
2714        0x0001d727,//input gain
2715        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2716        0x00e55557, 0xffcadd5b, 0x003d80ba,
2717        0x00d13397, 0xfff232f8, 0x00683337,
2718        0x00000001//output gain
2719};
2720
2721static u32 coef_192to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2722        0x000c9102,//header
2723        0x000005d6,//input gain
2724        0x00c6543e, 0xff342935, 0x0052f116,
2725        0x000a1d78, 0xff3330c0, 0x005f88a3,
2726        0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
2727        0x00000001,//output gain
2728        0x00005102,//header
2729        0x0001d727,//input gain
2730        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2731        0x00e55557, 0xffcadd5b, 0x003d80ba,
2732        0x00d13397, 0xfff232f8, 0x00683337,
2733        0x00000001//output gain
2734};
2735
2736static u32 coef_192to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2737        0x000c6102,//header
2738        0x000000af,//input gain
2739        0x00c65663, 0xff23d2ce, 0x005f97d6,
2740        0x00086ad6, 0xff20ec4f, 0x00683201,
2741        0xffbbbef6, 0xff184447, 0x00770963,
2742        0x00000002,//output gain
2743        0x00175204,//farrow
2744        0x000aaaab,
2745        0xffaaaaab,
2746        0xfffaaaab,
2747        0x00555555,
2748        0xff600000,
2749        0xfff55555,
2750        0x00155555,
2751        0x00055555,
2752        0xffeaaaab,
2753        0x00200000,
2754        0x00235102,//header
2755        0x000013d9,//input gain
2756        0x00ebd477, 0xff4ce383, 0x0042049d,
2757        0x0089c278, 0xff54414d, 0x00531ded,
2758        0x004a5e07, 0xff53cf41, 0x006efbdc,
2759        0x00000001,//output gain
2760        0x00005102,//header
2761        0x0001d727,//input gain
2762        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2763        0x00e55557, 0xffcadd5b, 0x003d80ba,
2764        0x00d13397, 0xfff232f8, 0x00683337,
2765        0x00000001//output gain
2766};
2767
2768static u32 coef_192to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2769        0x000c5102,//header
2770        0x000013d9,//input gain
2771        0x00ebd477, 0xff4ce383, 0x0042049d,
2772        0x0089c278, 0xff54414d, 0x00531ded,
2773        0x004a5e07, 0xff53cf41, 0x006efbdc,
2774        0x00000001,//output gain
2775        0x00005102,//header
2776        0x0001d727,//input gain
2777        0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2778        0x00e55557, 0xffcadd5b, 0x003d80ba,
2779        0x00d13397, 0xfff232f8, 0x00683337,
2780        0x00000001//output gain
2781};
2782
2783static u32 coef_192to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2784        0x000c6102,//header
2785        0x000000af,//input gain
2786        0x00c65663, 0xff23d2ce, 0x005f97d6,
2787        0x00086ad6, 0xff20ec4f, 0x00683201,
2788        0xffbbbef6, 0xff184447, 0x00770963,
2789        0x00000002,//output gain
2790        0x00175204,//farrow
2791        0x000aaaab,
2792        0xffaaaaab,
2793        0xfffaaaab,
2794        0x00555555,
2795        0xff600000,
2796        0xfff55555,
2797        0x00155555,
2798        0x00055555,
2799        0xffeaaaab,
2800        0x00200000,
2801        0x00005102,//header
2802        0x000013d9,//input gain
2803        0x00ebd477, 0xff4ce383, 0x0042049d,
2804        0x0089c278, 0xff54414d, 0x00531ded,
2805        0x004a5e07, 0xff53cf41, 0x006efbdc,
2806        0x00000001//output gain
2807};
2808
2809static u32 coef_192to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2810        0x00005103,//header
2811        0x000001e0,//input gain
2812        0x00de44c0, 0xff380b7f, 0x004ffc73,
2813        0x00494b44, 0xff3d493a, 0x005908bf,
2814        0xffe9a3c8, 0xff425647, 0x006745f7,
2815        0xffc42d61, 0xff40a6c7, 0x00776709,
2816        0x00000001//output gain
2817};
2818
2819static u32 coef_192to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2820        0x000c6102,//header
2821        0x000000af,//input gain
2822        0x00c65663, 0xff23d2ce, 0x005f97d6,
2823        0x00086ad6, 0xff20ec4f, 0x00683201,
2824        0xffbbbef6, 0xff184447, 0x00770963,
2825        0x00000002,//output gain
2826        0x00170204,//farrow
2827        0x000aaaab,
2828        0xffaaaaab,
2829        0xfffaaaab,
2830        0x00555555,
2831        0xff600000,
2832        0xfff55555,
2833        0x00155555,
2834        0x00055555,
2835        0xffeaaaab,
2836        0x00200000,
2837        0x00005102,//header
2838        0x0000010a,//input gain
2839        0x00c93dc4, 0xff26f5f6, 0x005d1041,
2840        0x001002c4, 0xff245b76, 0x00666002,
2841        0xffc30a45, 0xff1baecd, 0x00765921,
2842        0x00000001//output gain
2843};
2844
2845/*
2846 * Coefficient table for various sample rate conversions. The sample
2847 * rates available are as per tegra210_sfc_rates[].
2848 */
2849static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
2850        /* Convertions from 8 kHz */
2851        {
2852                BYPASS_CONV,
2853                coef_8to11,
2854                coef_8to16,
2855                coef_8to22,
2856                coef_8to24,
2857                coef_8to32,
2858                coef_8to44,
2859                coef_8to48,
2860                coef_8to88,
2861                coef_8to96,
2862                UNSUPP_CONV,
2863                UNSUPP_CONV,
2864        },
2865        /* Convertions from 11.025 kHz */
2866        {
2867                coef_11to8,
2868                BYPASS_CONV,
2869                coef_11to16,
2870                coef_11to22,
2871                coef_11to24,
2872                coef_11to32,
2873                coef_11to44,
2874                coef_11to48,
2875                coef_11to88,
2876                coef_11to96,
2877                UNSUPP_CONV,
2878                UNSUPP_CONV,
2879        },
2880        /* Convertions from 16 kHz */
2881        {
2882                coef_16to8,
2883                coef_16to11,
2884                BYPASS_CONV,
2885                coef_16to22,
2886                coef_16to24,
2887                coef_16to32,
2888                coef_16to44,
2889                coef_16to48,
2890                coef_16to88,
2891                coef_16to96,
2892                coef_16to176,
2893                coef_16to192,
2894        },
2895        /* Convertions from 22.05 kHz */
2896        {
2897                coef_22to8,
2898                coef_22to11,
2899                coef_22to16,
2900                BYPASS_CONV,
2901                coef_22to24,
2902                coef_22to32,
2903                coef_22to44,
2904                coef_22to48,
2905                coef_22to88,
2906                coef_22to96,
2907                coef_22to176,
2908                coef_22to192,
2909        },
2910        /* Convertions from 24 kHz */
2911        {
2912                coef_24to8,
2913                coef_24to11,
2914                coef_24to16,
2915                coef_24to22,
2916                BYPASS_CONV,
2917                coef_24to32,
2918                coef_24to44,
2919                coef_24to48,
2920                coef_24to88,
2921                coef_24to96,
2922                coef_24to176,
2923                coef_24to192,
2924        },
2925        /* Convertions from 32 kHz */
2926        {
2927                coef_32to8,
2928                coef_32to11,
2929                coef_32to16,
2930                coef_32to22,
2931                coef_32to24,
2932                BYPASS_CONV,
2933                coef_32to44,
2934                coef_32to48,
2935                coef_32to88,
2936                coef_32to96,
2937                coef_32to176,
2938                coef_32to192,
2939        },
2940        /* Convertions from 44.1 kHz */
2941        {
2942                coef_44to8,
2943                coef_44to11,
2944                coef_44to16,
2945                coef_44to22,
2946                coef_44to24,
2947                coef_44to32,
2948                BYPASS_CONV,
2949                coef_44to48,
2950                coef_44to88,
2951                coef_44to96,
2952                coef_44to176,
2953                coef_44to192,
2954        },
2955        /* Convertions from 48 kHz */
2956        {
2957                coef_48to8,
2958                coef_48to11,
2959                coef_48to16,
2960                coef_48to22,
2961                coef_48to24,
2962                coef_48to32,
2963                coef_48to44,
2964                BYPASS_CONV,
2965                coef_48to88,
2966                coef_48to96,
2967                coef_48to176,
2968                coef_48to192,
2969        },
2970        /* Convertions from 88.2 kHz */
2971        {
2972                coef_88to8,
2973                coef_88to11,
2974                coef_88to16,
2975                coef_88to22,
2976                coef_88to24,
2977                coef_88to32,
2978                coef_88to44,
2979                coef_88to48,
2980                BYPASS_CONV,
2981                coef_88to96,
2982                coef_88to176,
2983                coef_88to192,
2984        },
2985        /* Convertions from 96 kHz */
2986        {       coef_96to8,
2987                coef_96to11,
2988                coef_96to16,
2989                coef_96to22,
2990                coef_96to24,
2991                coef_96to32,
2992                coef_96to44,
2993                coef_96to48,
2994                coef_96to88,
2995                BYPASS_CONV,
2996                coef_96to176,
2997                coef_96to192,
2998        },
2999        /* Convertions from 176.4 kHz */
3000        {

3001                UNSUPP_CONV,
3002                UNSUPP_CONV,
3003                coef_176to16,
3004                coef_176to22,
3005                coef_176to24,
3006                coef_176to32,
3007                coef_176to44,
3008                coef_176to48,
3009                coef_176to88,
3010                coef_176to96,
3011                BYPASS_CONV,
3012                coef_176to192,
3013        },
3014        /* Convertions from 192 kHz */
3015        {
3016                UNSUPP_CONV,
3017                UNSUPP_CONV,
3018                coef_192to16,
3019                coef_192to22,
3020                coef_192to24,
3021                coef_192to32,
3022                coef_192to44,
3023                coef_192to48,
3024                coef_192to88,
3025                coef_192to96,
3026                coef_192to176,
3027                BYPASS_CONV,
3028        },
3029};
3030
3031static int __maybe_unused tegra210_sfc_runtime_suspend(struct device *dev)
3032{
3033        struct tegra210_sfc *sfc = dev_get_drvdata(dev);
3034
3035        regcache_cache_only(sfc->regmap, true);
3036        regcache_mark_dirty(sfc->regmap);
3037
3038        return 0;
3039}
3040
3041static int __maybe_unused tegra210_sfc_runtime_resume(struct device *dev)
3042{
3043        struct tegra210_sfc *sfc = dev_get_drvdata(dev);
3044
3045        regcache_cache_only(sfc->regmap, false);
3046        regcache_sync(sfc->regmap);
3047
3048        return 0;
3049}
3050
3051static inline void tegra210_sfc_write_ram(struct regmap *regmap,
3052                                          s32 *data)
3053{
3054        int i;
3055
3056        regmap_write(regmap, TEGRA210_SFC_CFG_RAM_CTRL,
3057                     TEGRA210_SFC_RAM_CTRL_SEQ_ACCESS_EN |
3058                     TEGRA210_SFC_RAM_CTRL_ADDR_INIT_EN |
3059                     TEGRA210_SFC_RAM_CTRL_RW_WRITE);
3060
3061        for (i = 0; i < TEGRA210_SFC_COEF_RAM_DEPTH; i++)
3062                regmap_write(regmap, TEGRA210_SFC_CFG_RAM_DATA, data[i]);
3063}
3064
3065static int tegra210_sfc_write_coeff_ram(struct snd_soc_component *cmpnt)
3066{
3067        struct tegra210_sfc *sfc = dev_get_drvdata(cmpnt->dev);
3068        s32 *coeff_ram;
3069
3070        /* Bypass */
3071        if (sfc->srate_in == sfc->srate_out)
3072                return 0;
3073
3074        coeff_ram = coef_addr_table[sfc->srate_in][sfc->srate_out];
3075        if (IS_ERR_OR_NULL(coeff_ram)) {
3076                dev_err(cmpnt->dev,
3077                        "Conversion from %d to %d Hz is not supported\n",
3078                        sfc->srate_in, sfc->srate_out);
3079
3080                return PTR_ERR_OR_ZERO(coeff_ram);
3081        }
3082
3083        tegra210_sfc_write_ram(sfc->regmap, coeff_ram);
3084
3085        regmap_update_bits(sfc->regmap,
3086                           TEGRA210_SFC_COEF_RAM,
3087                           TEGRA210_SFC_COEF_RAM_EN,
3088                           TEGRA210_SFC_COEF_RAM_EN);
3089
3090        return 0;
3091}
3092
3093static int tegra210_sfc_set_audio_cif(struct tegra210_sfc *sfc,
3094                                      struct snd_pcm_hw_params *params,
3095                                      unsigned int reg)
3096{
3097        unsigned int channels, audio_bits, path;
3098        struct tegra_cif_conf cif_conf;
3099
3100        memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
3101
3102        channels = params_channels(params);
3103
3104        switch (params_format(params)) {
3105        case SNDRV_PCM_FORMAT_S16_LE:
3106                audio_bits = TEGRA_ACIF_BITS_16;
3107                break;
3108        case SNDRV_PCM_FORMAT_S32_LE:
3109                audio_bits = TEGRA_ACIF_BITS_32;
3110                break;
3111        default:
3112                return -EOPNOTSUPP;
3113        }
3114
3115        cif_conf.audio_ch = channels;
3116        cif_conf.client_ch = channels;
3117        cif_conf.audio_bits = audio_bits;
3118        cif_conf.client_bits = TEGRA_ACIF_BITS_32;
3119
3120        if (reg == TEGRA210_SFC_RX_CIF_CTRL)
3121                path = SFC_RX_PATH;
3122        else
3123                path = SFC_TX_PATH;
3124
3125        cif_conf.stereo_conv = sfc->stereo_to_mono[path];
3126        cif_conf.mono_conv = sfc->mono_to_stereo[path];
3127
3128        tegra_set_cif(sfc->regmap, reg, &cif_conf);
3129
3130        return 0;
3131}
3132
3133static int tegra210_sfc_soft_reset(struct tegra210_sfc *sfc)
3134{
3135        u32 val;
3136
3137        /*
3138         * Soft Reset: Below performs module soft reset which clears
3139         * all FSM logic, flushes flow control of FIFO and resets the
3140         * state register. It also brings module back to disabled
3141         * state (without flushing the data in the pipe).
3142         */
3143        regmap_update_bits(sfc->regmap, TEGRA210_SFC_SOFT_RESET,
3144                           TEGRA210_SFC_SOFT_RESET_EN, 1);
3145
3146        return regmap_read_poll_timeout(sfc->regmap,
3147                                        TEGRA210_SFC_SOFT_RESET,
3148                                        val,
3149                                        !(val & TEGRA210_SFC_SOFT_RESET_EN),
3150                                        10, 10000);
3151}
3152
3153static int tegra210_sfc_rate_to_idx(struct device *dev, int rate,
3154                                    int *rate_idx)
3155{
3156        int i;
3157
3158        for (i = 0; i < ARRAY_SIZE(tegra210_sfc_rates); i++) {
3159                if (rate == tegra210_sfc_rates[i]) {
3160                        *rate_idx = i;
3161
3162                        return 0;
3163                }
3164        }
3165
3166        dev_err(dev, "Sample rate %d Hz is not supported\n", rate);
3167
3168        return -EOPNOTSUPP;
3169}
3170
3171static int tegra210_sfc_startup(struct snd_pcm_substream *substream,
3172                                struct snd_soc_dai *dai)
3173{
3174        struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai);
3175        int err;
3176
3177        regmap_update_bits(sfc->regmap, TEGRA210_SFC_COEF_RAM,
3178                           TEGRA210_SFC_COEF_RAM_EN, 0);
3179
3180        err = tegra210_sfc_soft_reset(sfc);
3181        if (err < 0) {
3182                dev_err(dai->dev, "Failed to reset SFC in %s, err = %d\n",
3183                        __func__, err);
3184
3185                return err;
3186        }
3187
3188        return 0;
3189}
3190
3191static int tegra210_sfc_in_hw_params(struct snd_pcm_substream *substream,
3192                                     struct snd_pcm_hw_params *params,
3193                                     struct snd_soc_dai *dai)
3194{
3195        struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai);
3196        struct device *dev = dai->dev;
3197        int err;
3198
3199        err = tegra210_sfc_rate_to_idx(dev, params_rate(params),
3200                                       &sfc->srate_in);
3201        if (err < 0)
3202                return err;
3203
3204        err = tegra210_sfc_set_audio_cif(sfc, params, TEGRA210_SFC_RX_CIF_CTRL);
3205        if (err < 0) {
3206                dev_err(dev, "Can't set SFC RX CIF: %d\n", err);
3207                return err;
3208        }
3209
3210        regmap_write(sfc->regmap, TEGRA210_SFC_RX_FREQ, sfc->srate_in);
3211
3212        return err;
3213}
3214
3215static int tegra210_sfc_out_hw_params(struct snd_pcm_substream *substream,
3216                                      struct snd_pcm_hw_params *params,
3217                                      struct snd_soc_dai *dai)
3218{
3219        struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai);
3220        struct device *dev = dai->dev;
3221        int err;
3222
3223        err = tegra210_sfc_rate_to_idx(dev, params_rate(params),
3224                                       &sfc->srate_out);
3225        if (err < 0)
3226                return err;
3227
3228        err = tegra210_sfc_set_audio_cif(sfc, params, TEGRA210_SFC_TX_CIF_CTRL);
3229        if (err < 0) {
3230                dev_err(dev, "Can't set SFC TX CIF: %d\n", err);
3231                return err;
3232        }
3233
3234        regmap_write(sfc->regmap, TEGRA210_SFC_TX_FREQ, sfc->srate_out);
3235
3236        return 0;
3237}
3238
3239static int tegra210_sfc_init(struct snd_soc_dapm_widget *w,
3240                             struct snd_kcontrol *kcontrol, int event)
3241{
3242        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
3243
3244        return tegra210_sfc_write_coeff_ram(cmpnt);
3245}
3246
3247static int tegra210_sfc_iget_stereo_to_mono(struct snd_kcontrol *kcontrol,
3248                                    struct snd_ctl_elem_value *ucontrol)
3249{
3250        struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3251        struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3252
3253        ucontrol->value.enumerated.item[0] = sfc->stereo_to_mono[SFC_RX_PATH];
3254
3255        return 0;
3256}
3257
3258static int tegra210_sfc_iput_stereo_to_mono(struct snd_kcontrol *kcontrol,
3259                                    struct snd_ctl_elem_value *ucontrol)
3260{
3261        struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3262        struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3263        unsigned int value = ucontrol->value.enumerated.item[0];
3264
3265        if (value == sfc->stereo_to_mono[SFC_RX_PATH])
3266                return 0;
3267
3268        sfc->stereo_to_mono[SFC_RX_PATH] = value;
3269
3270        return 1;
3271}
3272
3273static int tegra210_sfc_iget_mono_to_stereo(struct snd_kcontrol *kcontrol,
3274                                    struct snd_ctl_elem_value *ucontrol)
3275{
3276        struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3277        struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3278
3279        ucontrol->value.enumerated.item[0] = sfc->mono_to_stereo[SFC_RX_PATH];
3280
3281        return 0;
3282}
3283
3284static int tegra210_sfc_iput_mono_to_stereo(struct snd_kcontrol *kcontrol,
3285                                    struct snd_ctl_elem_value *ucontrol)
3286{
3287        struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3288        struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3289        unsigned int value = ucontrol->value.enumerated.item[0];
3290
3291        if (value == sfc->mono_to_stereo[SFC_RX_PATH])
3292                return 0;
3293
3294        sfc->mono_to_stereo[SFC_RX_PATH] = value;
3295
3296        return 1;
3297}
3298
3299static int tegra210_sfc_oget_stereo_to_mono(struct snd_kcontrol *kcontrol,
3300                                    struct snd_ctl_elem_value *ucontrol)
3301{
3302        struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3303        struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3304
3305        ucontrol->value.enumerated.item[0] = sfc->stereo_to_mono[SFC_TX_PATH];
3306
3307        return 0;
3308}
3309
3310static int tegra210_sfc_oput_stereo_to_mono(struct snd_kcontrol *kcontrol,
3311                                    struct snd_ctl_elem_value *ucontrol)
3312{
3313        struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3314        struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3315        unsigned int value = ucontrol->value.enumerated.item[0];
3316
3317        if (value == sfc->stereo_to_mono[SFC_TX_PATH])
3318                return 0;
3319
3320        sfc->stereo_to_mono[SFC_TX_PATH] = value;
3321
3322        return 1;
3323}
3324
3325static int tegra210_sfc_oget_mono_to_stereo(struct snd_kcontrol *kcontrol,
3326                                    struct snd_ctl_elem_value *ucontrol)
3327{
3328        struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3329        struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3330
3331        ucontrol->value.enumerated.item[0] = sfc->mono_to_stereo[SFC_TX_PATH];
3332
3333        return 0;
3334}
3335
3336static int tegra210_sfc_oput_mono_to_stereo(struct snd_kcontrol *kcontrol,
3337                                    struct snd_ctl_elem_value *ucontrol)
3338{
3339        struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3340        struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3341        unsigned int value = ucontrol->value.enumerated.item[0];
3342
3343        if (value == sfc->mono_to_stereo[SFC_TX_PATH])
3344                return 0;
3345
3346        sfc->mono_to_stereo[SFC_TX_PATH] = value;
3347
3348        return 1;
3349}
3350
3351static const struct snd_soc_dai_ops tegra210_sfc_in_dai_ops = {
3352        .hw_params      = tegra210_sfc_in_hw_params,
3353        .startup        = tegra210_sfc_startup,
3354};
3355
3356static const struct snd_soc_dai_ops tegra210_sfc_out_dai_ops = {
3357        .hw_params      = tegra210_sfc_out_hw_params,
3358};
3359
3360static struct snd_soc_dai_driver tegra210_sfc_dais[] = {
3361        {
3362                .name = "SFC-RX-CIF",
3363                .playback = {
3364                        .stream_name = "RX-CIF-Playback",
3365                        .channels_min = 1,
3366                        .channels_max = 2,
3367                        .rates = SNDRV_PCM_RATE_8000_192000,
3368                        .formats = SNDRV_PCM_FMTBIT_S8 |
3369                                SNDRV_PCM_FMTBIT_S16_LE |
3370                                SNDRV_PCM_FMTBIT_S32_LE,
3371                },
3372                .capture = {
3373                        .stream_name = "RX-CIF-Capture",
3374                        .channels_min = 1,
3375                        .channels_max = 2,
3376                        .rates = SNDRV_PCM_RATE_8000_192000,
3377                        .formats = SNDRV_PCM_FMTBIT_S8 |
3378                                SNDRV_PCM_FMTBIT_S16_LE |
3379                                SNDRV_PCM_FMTBIT_S32_LE,
3380                },
3381                .ops = &tegra210_sfc_in_dai_ops,
3382        },
3383        {
3384                .name = "SFC-TX-CIF",
3385                .playback = {
3386                        .stream_name = "TX-CIF-Playback",
3387                        .channels_min = 1,
3388                        .channels_max = 2,
3389                        .rates = SNDRV_PCM_RATE_8000_192000,
3390                        .formats = SNDRV_PCM_FMTBIT_S8 |
3391                                SNDRV_PCM_FMTBIT_S16_LE |
3392                                SNDRV_PCM_FMTBIT_S32_LE,
3393                },
3394                .capture = {
3395                        .stream_name = "TX-CIF-Capture",
3396                        .channels_min = 1,
3397                        .channels_max = 2,
3398                        .rates = SNDRV_PCM_RATE_8000_192000,
3399                        .formats = SNDRV_PCM_FMTBIT_S8 |
3400                                SNDRV_PCM_FMTBIT_S16_LE |
3401                                SNDRV_PCM_FMTBIT_S32_LE,
3402                },
3403                .ops = &tegra210_sfc_out_dai_ops,
3404        },
3405};
3406
3407static const struct snd_soc_dapm_widget tegra210_sfc_widgets[] = {
3408        SND_SOC_DAPM_AIF_IN("RX", NULL, 0, SND_SOC_NOPM, 0, 0),
3409        SND_SOC_DAPM_AIF_OUT_E("TX", NULL, 0, TEGRA210_SFC_ENABLE,
3410                               TEGRA210_SFC_EN_SHIFT, 0,
3411                               tegra210_sfc_init, SND_SOC_DAPM_PRE_PMU),
3412};
3413
3414#define RESAMPLE_ROUTE(sname)                                   \
3415        { "RX XBAR-" sname,     NULL,   "XBAR-TX" },            \
3416        { "RX-CIF-" sname,      NULL,   "RX XBAR-" sname },     \
3417        { "RX",                 NULL,   "RX-CIF-" sname },      \
3418        { "TX-CIF-" sname,      NULL,   "TX" },                 \
3419        { "TX XBAR-" sname,     NULL,   "TX-CIF-" sname },      \
3420        { "XBAR-RX",            NULL,   "TX XBAR-" sname }
3421
3422static const struct snd_soc_dapm_route tegra210_sfc_routes[] = {
3423        { "TX", NULL, "RX" },
3424        RESAMPLE_ROUTE("Playback"),
3425        RESAMPLE_ROUTE("Capture"),
3426};
3427
3428static const char * const tegra210_sfc_stereo_conv_text[] = {
3429        "CH0", "CH1", "AVG",
3430};
3431
3432static const char * const tegra210_sfc_mono_conv_text[] = {
3433        "Zero", "Copy",
3434};
3435
3436static const struct soc_enum tegra210_sfc_stereo_conv_enum =
3437        SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
3438                        ARRAY_SIZE(tegra210_sfc_stereo_conv_text),
3439                        tegra210_sfc_stereo_conv_text);
3440
3441static const struct soc_enum tegra210_sfc_mono_conv_enum =
3442        SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
3443                        ARRAY_SIZE(tegra210_sfc_mono_conv_text),
3444                        tegra210_sfc_mono_conv_text);
3445
3446static const struct snd_kcontrol_new tegra210_sfc_controls[] = {
3447        SOC_ENUM_EXT("Input Stereo To Mono", tegra210_sfc_stereo_conv_enum,
3448                     tegra210_sfc_iget_stereo_to_mono,
3449                     tegra210_sfc_iput_stereo_to_mono),
3450        SOC_ENUM_EXT("Input Mono To Stereo", tegra210_sfc_mono_conv_enum,
3451                     tegra210_sfc_iget_mono_to_stereo,
3452                     tegra210_sfc_iput_mono_to_stereo),
3453        SOC_ENUM_EXT("Output Stereo To Mono", tegra210_sfc_stereo_conv_enum,
3454                     tegra210_sfc_oget_stereo_to_mono,
3455                     tegra210_sfc_oput_stereo_to_mono),
3456        SOC_ENUM_EXT("Output Mono To Stereo", tegra210_sfc_mono_conv_enum,
3457                     tegra210_sfc_oget_mono_to_stereo,
3458                     tegra210_sfc_oput_mono_to_stereo),
3459};
3460
3461static const struct snd_soc_component_driver tegra210_sfc_cmpnt = {
3462        .dapm_widgets           = tegra210_sfc_widgets,
3463        .num_dapm_widgets       = ARRAY_SIZE(tegra210_sfc_widgets),
3464        .dapm_routes            = tegra210_sfc_routes,
3465        .num_dapm_routes        = ARRAY_SIZE(tegra210_sfc_routes),
3466        .controls               = tegra210_sfc_controls,
3467        .num_controls           = ARRAY_SIZE(tegra210_sfc_controls),
3468};
3469
3470static bool tegra210_sfc_wr_reg(struct device *dev, unsigned int reg)
3471{
3472        switch (reg) {
3473        case TEGRA210_SFC_RX_INT_MASK ... TEGRA210_SFC_RX_FREQ:
3474        case TEGRA210_SFC_TX_INT_MASK ... TEGRA210_SFC_TX_FREQ:
3475        case TEGRA210_SFC_ENABLE ... TEGRA210_SFC_CG:
3476        case TEGRA210_SFC_COEF_RAM ... TEGRA210_SFC_CFG_RAM_DATA:
3477                return true;
3478        default:
3479                return false;
3480        }
3481}
3482
3483static bool tegra210_sfc_rd_reg(struct device *dev, unsigned int reg)
3484{
3485        switch (reg) {
3486        case TEGRA210_SFC_RX_STATUS ... TEGRA210_SFC_RX_FREQ:
3487        case TEGRA210_SFC_TX_STATUS ... TEGRA210_SFC_TX_FREQ:
3488        case TEGRA210_SFC_ENABLE ... TEGRA210_SFC_INT_STATUS:
3489        case TEGRA210_SFC_COEF_RAM ... TEGRA210_SFC_CFG_RAM_DATA:
3490                return true;
3491        default:
3492                return false;
3493        }
3494}
3495
3496static bool tegra210_sfc_volatile_reg(struct device *dev, unsigned int reg)
3497{
3498        switch (reg) {
3499        case TEGRA210_SFC_RX_STATUS:
3500        case TEGRA210_SFC_RX_INT_STATUS:
3501        case TEGRA210_SFC_RX_INT_SET:
3502
3503        case TEGRA210_SFC_TX_STATUS:
3504        case TEGRA210_SFC_TX_INT_STATUS:
3505        case TEGRA210_SFC_TX_INT_SET:
3506
3507        case TEGRA210_SFC_SOFT_RESET:
3508        case TEGRA210_SFC_STATUS:
3509        case TEGRA210_SFC_INT_STATUS:
3510        case TEGRA210_SFC_CFG_RAM_CTRL:
3511        case TEGRA210_SFC_CFG_RAM_DATA:
3512                return true;
3513        default:
3514                return false;
3515        }
3516}
3517
3518static bool tegra210_sfc_precious_reg(struct device *dev, unsigned int reg)
3519{
3520        switch (reg) {
3521        case TEGRA210_SFC_CFG_RAM_DATA:
3522                return true;
3523        default:
3524                return false;
3525        }
3526}
3527
3528static const struct regmap_config tegra210_sfc_regmap_config = {
3529        .reg_bits               = 32,
3530        .reg_stride             = 4,
3531        .val_bits               = 32,
3532        .max_register           = TEGRA210_SFC_CFG_RAM_DATA,
3533        .writeable_reg          = tegra210_sfc_wr_reg,
3534        .readable_reg           = tegra210_sfc_rd_reg,
3535        .volatile_reg           = tegra210_sfc_volatile_reg,
3536        .precious_reg           = tegra210_sfc_precious_reg,
3537        .reg_defaults           = tegra210_sfc_reg_defaults,
3538        .num_reg_defaults       = ARRAY_SIZE(tegra210_sfc_reg_defaults),
3539        .cache_type             = REGCACHE_FLAT,
3540};
3541
3542static const struct of_device_id tegra210_sfc_of_match[] = {
3543        { .compatible = "nvidia,tegra210-sfc" },
3544        {},
3545};
3546MODULE_DEVICE_TABLE(of, tegra210_sfc_of_match);
3547
3548static int tegra210_sfc_platform_probe(struct platform_device *pdev)
3549{
3550        struct device *dev = &pdev->dev;
3551        struct tegra210_sfc *sfc;
3552        void __iomem *regs;
3553        int err;
3554
3555        sfc = devm_kzalloc(dev, sizeof(*sfc), GFP_KERNEL);
3556        if (!sfc)
3557                return -ENOMEM;
3558
3559        dev_set_drvdata(dev, sfc);
3560
3561        regs = devm_platform_ioremap_resource(pdev, 0);
3562        if (IS_ERR(regs))
3563                return PTR_ERR(regs);
3564
3565        sfc->regmap = devm_regmap_init_mmio(dev, regs,
3566                                            &tegra210_sfc_regmap_config);
3567        if (IS_ERR(sfc->regmap)) {
3568                dev_err(dev, "regmap init failed\n");
3569                return PTR_ERR(sfc->regmap);
3570        }
3571
3572        regcache_cache_only(sfc->regmap, true);
3573
3574        err = devm_snd_soc_register_component(dev, &tegra210_sfc_cmpnt,
3575                                              tegra210_sfc_dais,
3576                                              ARRAY_SIZE(tegra210_sfc_dais));
3577        if (err) {
3578                dev_err(dev, "can't register SFC component, err: %d\n", err);
3579                return err;
3580        }
3581
3582        pm_runtime_enable(&pdev->dev);
3583
3584        return 0;
3585}
3586
3587static int tegra210_sfc_platform_remove(struct platform_device *pdev)
3588{
3589        pm_runtime_disable(&pdev->dev);
3590
3591        return 0;
3592}
3593
3594static const struct dev_pm_ops tegra210_sfc_pm_ops = {
3595        SET_RUNTIME_PM_OPS(tegra210_sfc_runtime_suspend,
3596                           tegra210_sfc_runtime_resume, NULL)
3597        SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
3598                                pm_runtime_force_resume)
3599};
3600
3601static struct platform_driver tegra210_sfc_driver = {
3602        .driver = {
3603                .name = "tegra210-sfc",
3604                .of_match_table = tegra210_sfc_of_match,
3605                .pm = &tegra210_sfc_pm_ops,
3606        },
3607        .probe = tegra210_sfc_platform_probe,
3608        .remove = tegra210_sfc_platform_remove,
3609};
3610module_platform_driver(tegra210_sfc_driver)
3611
3612MODULE_AUTHOR("Arun Shamanna Lakshmi <aruns@nvidia.com>");
3613MODULE_DESCRIPTION("Tegra210 SFC ASoC driver");
3614MODULE_LICENSE("GPL v2");
3615