1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16#undef DEBUG
17#undef DEBUG_IPI
18#undef DEBUG_IRQ
19#undef DEBUG_LOW
20
21#include <linux/types.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/irq.h>
25#include <linux/smp.h>
26#include <linux/interrupt.h>
27#include <linux/spinlock.h>
28#include <linux/pci.h>
29#include <linux/slab.h>
30#include <linux/syscore_ops.h>
31#include <linux/ratelimit.h>
32#include <linux/pgtable.h>
33
34#include <asm/ptrace.h>
35#include <asm/signal.h>
36#include <asm/io.h>
37#include <asm/irq.h>
38#include <asm/machdep.h>
39#include <asm/mpic.h>
40#include <asm/smp.h>
41
42#include "mpic.h"
43
44#ifdef DEBUG
45#define DBG(fmt...) printk(fmt)
46#else
47#define DBG(fmt...)
48#endif
49
50struct bus_type mpic_subsys = {
51 .name = "mpic",
52 .dev_name = "mpic",
53};
54EXPORT_SYMBOL_GPL(mpic_subsys);
55
56static struct mpic *mpics;
57static struct mpic *mpic_primary;
58static DEFINE_RAW_SPINLOCK(mpic_lock);
59
60#ifdef CONFIG_PPC32
61#ifdef CONFIG_IRQ_ALL_CPUS
62#define distribute_irqs (1)
63#else
64#define distribute_irqs (0)
65#endif
66#endif
67
68#ifdef CONFIG_MPIC_WEIRD
69static u32 mpic_infos[][MPIC_IDX_END] = {
70 [0] = {
71 MPIC_GREG_BASE,
72 MPIC_GREG_FEATURE_0,
73 MPIC_GREG_GLOBAL_CONF_0,
74 MPIC_GREG_VENDOR_ID,
75 MPIC_GREG_IPI_VECTOR_PRI_0,
76 MPIC_GREG_IPI_STRIDE,
77 MPIC_GREG_SPURIOUS,
78 MPIC_GREG_TIMER_FREQ,
79
80 MPIC_TIMER_BASE,
81 MPIC_TIMER_STRIDE,
82 MPIC_TIMER_CURRENT_CNT,
83 MPIC_TIMER_BASE_CNT,
84 MPIC_TIMER_VECTOR_PRI,
85 MPIC_TIMER_DESTINATION,
86
87 MPIC_CPU_BASE,
88 MPIC_CPU_STRIDE,
89 MPIC_CPU_IPI_DISPATCH_0,
90 MPIC_CPU_IPI_DISPATCH_STRIDE,
91 MPIC_CPU_CURRENT_TASK_PRI,
92 MPIC_CPU_WHOAMI,
93 MPIC_CPU_INTACK,
94 MPIC_CPU_EOI,
95 MPIC_CPU_MCACK,
96
97 MPIC_IRQ_BASE,
98 MPIC_IRQ_STRIDE,
99 MPIC_IRQ_VECTOR_PRI,
100 MPIC_VECPRI_VECTOR_MASK,
101 MPIC_VECPRI_POLARITY_POSITIVE,
102 MPIC_VECPRI_POLARITY_NEGATIVE,
103 MPIC_VECPRI_SENSE_LEVEL,
104 MPIC_VECPRI_SENSE_EDGE,
105 MPIC_VECPRI_POLARITY_MASK,
106 MPIC_VECPRI_SENSE_MASK,
107 MPIC_IRQ_DESTINATION
108 },
109 [1] = {
110 TSI108_GREG_BASE,
111 TSI108_GREG_FEATURE_0,
112 TSI108_GREG_GLOBAL_CONF_0,
113 TSI108_GREG_VENDOR_ID,
114 TSI108_GREG_IPI_VECTOR_PRI_0,
115 TSI108_GREG_IPI_STRIDE,
116 TSI108_GREG_SPURIOUS,
117 TSI108_GREG_TIMER_FREQ,
118
119 TSI108_TIMER_BASE,
120 TSI108_TIMER_STRIDE,
121 TSI108_TIMER_CURRENT_CNT,
122 TSI108_TIMER_BASE_CNT,
123 TSI108_TIMER_VECTOR_PRI,
124 TSI108_TIMER_DESTINATION,
125
126 TSI108_CPU_BASE,
127 TSI108_CPU_STRIDE,
128 TSI108_CPU_IPI_DISPATCH_0,
129 TSI108_CPU_IPI_DISPATCH_STRIDE,
130 TSI108_CPU_CURRENT_TASK_PRI,
131 TSI108_CPU_WHOAMI,
132 TSI108_CPU_INTACK,
133 TSI108_CPU_EOI,
134 TSI108_CPU_MCACK,
135
136 TSI108_IRQ_BASE,
137 TSI108_IRQ_STRIDE,
138 TSI108_IRQ_VECTOR_PRI,
139 TSI108_VECPRI_VECTOR_MASK,
140 TSI108_VECPRI_POLARITY_POSITIVE,
141 TSI108_VECPRI_POLARITY_NEGATIVE,
142 TSI108_VECPRI_SENSE_LEVEL,
143 TSI108_VECPRI_SENSE_EDGE,
144 TSI108_VECPRI_POLARITY_MASK,
145 TSI108_VECPRI_SENSE_MASK,
146 TSI108_IRQ_DESTINATION
147 },
148};
149
150#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
151
152#else
153
154#define MPIC_INFO(name) MPIC_##name
155
156#endif
157
158static inline unsigned int mpic_processor_id(struct mpic *mpic)
159{
160 unsigned int cpu = 0;
161
162 if (!(mpic->flags & MPIC_SECONDARY))
163 cpu = hard_smp_processor_id();
164
165 return cpu;
166}
167
168
169
170
171
172
173static inline u32 _mpic_read(enum mpic_reg_type type,
174 struct mpic_reg_bank *rb,
175 unsigned int reg)
176{
177 switch(type) {
178#ifdef CONFIG_PPC_DCR
179 case mpic_access_dcr:
180 return dcr_read(rb->dhost, reg);
181#endif
182 case mpic_access_mmio_be:
183 return in_be32(rb->base + (reg >> 2));
184 case mpic_access_mmio_le:
185 default:
186 return in_le32(rb->base + (reg >> 2));
187 }
188}
189
190static inline void _mpic_write(enum mpic_reg_type type,
191 struct mpic_reg_bank *rb,
192 unsigned int reg, u32 value)
193{
194 switch(type) {
195#ifdef CONFIG_PPC_DCR
196 case mpic_access_dcr:
197 dcr_write(rb->dhost, reg, value);
198 break;
199#endif
200 case mpic_access_mmio_be:
201 out_be32(rb->base + (reg >> 2), value);
202 break;
203 case mpic_access_mmio_le:
204 default:
205 out_le32(rb->base + (reg >> 2), value);
206 break;
207 }
208}
209
210static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
211{
212 enum mpic_reg_type type = mpic->reg_type;
213 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
214 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
215
216 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
217 type = mpic_access_mmio_be;
218 return _mpic_read(type, &mpic->gregs, offset);
219}
220
221static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
222{
223 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
224 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
225
226 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
227}
228
229static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
230{
231 return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE +
232 (tm & 3) * MPIC_INFO(TIMER_STRIDE);
233}
234
235static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
236{
237 unsigned int offset = mpic_tm_offset(mpic, tm) +
238 MPIC_INFO(TIMER_VECTOR_PRI);
239
240 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
241}
242
243static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
244{
245 unsigned int offset = mpic_tm_offset(mpic, tm) +
246 MPIC_INFO(TIMER_VECTOR_PRI);
247
248 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
249}
250
251static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
252{
253 unsigned int cpu = mpic_processor_id(mpic);
254
255 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
256}
257
258static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
259{
260 unsigned int cpu = mpic_processor_id(mpic);
261
262 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
263}
264
265static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
266{
267 unsigned int isu = src_no >> mpic->isu_shift;
268 unsigned int idx = src_no & mpic->isu_mask;
269 unsigned int val;
270
271 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
272 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
273#ifdef CONFIG_MPIC_BROKEN_REGREAD
274 if (reg == 0)
275 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
276 mpic->isu_reg0_shadow[src_no];
277#endif
278 return val;
279}
280
281static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
282 unsigned int reg, u32 value)
283{
284 unsigned int isu = src_no >> mpic->isu_shift;
285 unsigned int idx = src_no & mpic->isu_mask;
286
287 _mpic_write(mpic->reg_type, &mpic->isus[isu],
288 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
289
290#ifdef CONFIG_MPIC_BROKEN_REGREAD
291 if (reg == 0)
292 mpic->isu_reg0_shadow[src_no] =
293 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
294#endif
295}
296
297#define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
298#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
299#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
300#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
301#define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
302#define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
303#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
304#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
305#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
306#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
307
308
309
310
311
312
313
314static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
315 struct mpic_reg_bank *rb, unsigned int offset,
316 unsigned int size)
317{
318 rb->base = ioremap(phys_addr + offset, size);
319 BUG_ON(rb->base == NULL);
320}
321
322#ifdef CONFIG_PPC_DCR
323static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
324 unsigned int offset, unsigned int size)
325{
326 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
327 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
328 BUG_ON(!DCR_MAP_OK(rb->dhost));
329}
330
331static inline void mpic_map(struct mpic *mpic,
332 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
333 unsigned int offset, unsigned int size)
334{
335 if (mpic->flags & MPIC_USES_DCR)
336 _mpic_map_dcr(mpic, rb, offset, size);
337 else
338 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
339}
340#else
341#define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
342#endif
343
344
345
346
347
348
349static void __init mpic_test_broken_ipi(struct mpic *mpic)
350{
351 u32 r;
352
353 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
354 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
355
356 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
357 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
358 mpic->flags |= MPIC_BROKEN_IPI;
359 }
360}
361
362#ifdef CONFIG_MPIC_U3_HT_IRQS
363
364
365
366
367static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
368{
369 if (source >= 128 || !mpic->fixups)
370 return 0;
371 return mpic->fixups[source].base != NULL;
372}
373
374
375static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
376{
377 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
378
379 if (fixup->applebase) {
380 unsigned int soff = (fixup->index >> 3) & ~3;
381 unsigned int mask = 1U << (fixup->index & 0x1f);
382 writel(mask, fixup->applebase + soff);
383 } else {
384 raw_spin_lock(&mpic->fixup_lock);
385 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
386 writel(fixup->data, fixup->base + 4);
387 raw_spin_unlock(&mpic->fixup_lock);
388 }
389}
390
391static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
392 bool level)
393{
394 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
395 unsigned long flags;
396 u32 tmp;
397
398 if (fixup->base == NULL)
399 return;
400
401 DBG("startup_ht_interrupt(0x%x) index: %d\n",
402 source, fixup->index);
403 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
404
405 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
406 tmp = readl(fixup->base + 4);
407 tmp &= ~(0x23U);
408 if (level)
409 tmp |= 0x22;
410 writel(tmp, fixup->base + 4);
411 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
412
413#ifdef CONFIG_PM
414
415
416 mpic->save_data[source].fixup_data = tmp | 1;
417#endif
418}
419
420static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
421{
422 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
423 unsigned long flags;
424 u32 tmp;
425
426 if (fixup->base == NULL)
427 return;
428
429 DBG("shutdown_ht_interrupt(0x%x)\n", source);
430
431
432 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
433 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
434 tmp = readl(fixup->base + 4);
435 tmp |= 1;
436 writel(tmp, fixup->base + 4);
437 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
438
439#ifdef CONFIG_PM
440
441
442 mpic->save_data[source].fixup_data = tmp & ~1;
443#endif
444}
445
446#ifdef CONFIG_PCI_MSI
447static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
448 unsigned int devfn)
449{
450 u8 __iomem *base;
451 u8 pos, flags;
452 u64 addr = 0;
453
454 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
455 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
456 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
457 if (id == PCI_CAP_ID_HT) {
458 id = readb(devbase + pos + 3);
459 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
460 break;
461 }
462 }
463
464 if (pos == 0)
465 return;
466
467 base = devbase + pos;
468
469 flags = readb(base + HT_MSI_FLAGS);
470 if (!(flags & HT_MSI_FLAGS_FIXED)) {
471 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
472 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
473 }
474
475 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
476 PCI_SLOT(devfn), PCI_FUNC(devfn),
477 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
478
479 if (!(flags & HT_MSI_FLAGS_ENABLE))
480 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
481}
482#else
483static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
484 unsigned int devfn)
485{
486 return;
487}
488#endif
489
490static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
491 unsigned int devfn, u32 vdid)
492{
493 int i, irq, n;
494 u8 __iomem *base;
495 u32 tmp;
496 u8 pos;
497
498 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
499 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
500 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
501 if (id == PCI_CAP_ID_HT) {
502 id = readb(devbase + pos + 3);
503 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
504 break;
505 }
506 }
507 if (pos == 0)
508 return;
509
510 base = devbase + pos;
511 writeb(0x01, base + 2);
512 n = (readl(base + 4) >> 16) & 0xff;
513
514 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
515 " has %d irqs\n",
516 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
517
518 for (i = 0; i <= n; i++) {
519 writeb(0x10 + 2 * i, base + 2);
520 tmp = readl(base + 4);
521 irq = (tmp >> 16) & 0xff;
522 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
523
524 tmp |= 0x1;
525 writel(tmp, base + 4);
526 mpic->fixups[irq].index = i;
527 mpic->fixups[irq].base = base;
528
529 if ((vdid & 0xffff) == 0x106b)
530 mpic->fixups[irq].applebase = devbase + 0x60;
531 else
532 mpic->fixups[irq].applebase = NULL;
533 writeb(0x11 + 2 * i, base + 2);
534 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
535 }
536}
537
538
539static void __init mpic_scan_ht_pics(struct mpic *mpic)
540{
541 unsigned int devfn;
542 u8 __iomem *cfgspace;
543
544 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
545
546
547 mpic->fixups = kcalloc(128, sizeof(*mpic->fixups), GFP_KERNEL);
548 BUG_ON(mpic->fixups == NULL);
549
550
551 raw_spin_lock_init(&mpic->fixup_lock);
552
553
554
555
556 cfgspace = ioremap(0xf2000000, 0x10000);
557 BUG_ON(cfgspace == NULL);
558
559
560
561
562 for (devfn = 0; devfn < 0x100; devfn++) {
563 u8 __iomem *devbase = cfgspace + (devfn << 8);
564 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
565 u32 l = readl(devbase + PCI_VENDOR_ID);
566 u16 s;
567
568 DBG("devfn %x, l: %x\n", devfn, l);
569
570
571 if (l == 0xffffffff || l == 0x00000000 ||
572 l == 0x0000ffff || l == 0xffff0000)
573 goto next;
574
575 s = readw(devbase + PCI_STATUS);
576 if (!(s & PCI_STATUS_CAP_LIST))
577 goto next;
578
579 mpic_scan_ht_pic(mpic, devbase, devfn, l);
580 mpic_scan_ht_msi(mpic, devbase, devfn);
581
582 next:
583
584 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
585 devfn += 7;
586 }
587}
588
589#else
590
591static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
592{
593 return 0;
594}
595
596static void __init mpic_scan_ht_pics(struct mpic *mpic)
597{
598}
599
600#endif
601
602
603static struct mpic *mpic_find(unsigned int irq)
604{
605 if (irq < NR_IRQS_LEGACY)
606 return NULL;
607
608 return irq_get_chip_data(irq);
609}
610
611
612static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
613{
614 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
615}
616
617
618static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
619{
620 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
621}
622
623
624static inline u32 mpic_physmask(u32 cpumask)
625{
626 int i;
627 u32 mask = 0;
628
629 for (i = 0; i < min(32, NR_CPUS) && cpu_possible(i); ++i, cpumask >>= 1)
630 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
631 return mask;
632}
633
634#ifdef CONFIG_SMP
635
636static inline struct mpic * mpic_from_ipi(struct irq_data *d)
637{
638 return irq_data_get_irq_chip_data(d);
639}
640#endif
641
642
643static inline struct mpic * mpic_from_irq(unsigned int irq)
644{
645 return irq_get_chip_data(irq);
646}
647
648
649static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
650{
651 return irq_data_get_irq_chip_data(d);
652}
653
654
655static inline void mpic_eoi(struct mpic *mpic)
656{
657 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
658}
659
660
661
662
663
664
665void mpic_unmask_irq(struct irq_data *d)
666{
667 unsigned int loops = 100000;
668 struct mpic *mpic = mpic_from_irq_data(d);
669 unsigned int src = irqd_to_hwirq(d);
670
671 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
672
673 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
674 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
675 ~MPIC_VECPRI_MASK);
676
677 do {
678 if (!loops--) {
679 printk(KERN_ERR "%s: timeout on hwirq %u\n",
680 __func__, src);
681 break;
682 }
683 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
684}
685
686void mpic_mask_irq(struct irq_data *d)
687{
688 unsigned int loops = 100000;
689 struct mpic *mpic = mpic_from_irq_data(d);
690 unsigned int src = irqd_to_hwirq(d);
691
692 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
693
694 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
695 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
696 MPIC_VECPRI_MASK);
697
698
699 do {
700 if (!loops--) {
701 printk(KERN_ERR "%s: timeout on hwirq %u\n",
702 __func__, src);
703 break;
704 }
705 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
706}
707
708void mpic_end_irq(struct irq_data *d)
709{
710 struct mpic *mpic = mpic_from_irq_data(d);
711
712#ifdef DEBUG_IRQ
713 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
714#endif
715
716
717
718
719
720 mpic_eoi(mpic);
721}
722
723#ifdef CONFIG_MPIC_U3_HT_IRQS
724
725static void mpic_unmask_ht_irq(struct irq_data *d)
726{
727 struct mpic *mpic = mpic_from_irq_data(d);
728 unsigned int src = irqd_to_hwirq(d);
729
730 mpic_unmask_irq(d);
731
732 if (irqd_is_level_type(d))
733 mpic_ht_end_irq(mpic, src);
734}
735
736static unsigned int mpic_startup_ht_irq(struct irq_data *d)
737{
738 struct mpic *mpic = mpic_from_irq_data(d);
739 unsigned int src = irqd_to_hwirq(d);
740
741 mpic_unmask_irq(d);
742 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
743
744 return 0;
745}
746
747static void mpic_shutdown_ht_irq(struct irq_data *d)
748{
749 struct mpic *mpic = mpic_from_irq_data(d);
750 unsigned int src = irqd_to_hwirq(d);
751
752 mpic_shutdown_ht_interrupt(mpic, src);
753 mpic_mask_irq(d);
754}
755
756static void mpic_end_ht_irq(struct irq_data *d)
757{
758 struct mpic *mpic = mpic_from_irq_data(d);
759 unsigned int src = irqd_to_hwirq(d);
760
761#ifdef DEBUG_IRQ
762 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
763#endif
764
765
766
767
768
769 if (irqd_is_level_type(d))
770 mpic_ht_end_irq(mpic, src);
771 mpic_eoi(mpic);
772}
773#endif
774
775#ifdef CONFIG_SMP
776
777static void mpic_unmask_ipi(struct irq_data *d)
778{
779 struct mpic *mpic = mpic_from_ipi(d);
780 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
781
782 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
783 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
784}
785
786static void mpic_mask_ipi(struct irq_data *d)
787{
788
789}
790
791static void mpic_end_ipi(struct irq_data *d)
792{
793 struct mpic *mpic = mpic_from_ipi(d);
794
795
796
797
798
799
800 mpic_eoi(mpic);
801}
802
803#endif
804
805static void mpic_unmask_tm(struct irq_data *d)
806{
807 struct mpic *mpic = mpic_from_irq_data(d);
808 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
809
810 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
811 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
812 mpic_tm_read(src);
813}
814
815static void mpic_mask_tm(struct irq_data *d)
816{
817 struct mpic *mpic = mpic_from_irq_data(d);
818 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
819
820 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
821 mpic_tm_read(src);
822}
823
824int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
825 bool force)
826{
827 struct mpic *mpic = mpic_from_irq_data(d);
828 unsigned int src = irqd_to_hwirq(d);
829
830 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
831 int cpuid = irq_choose_cpu(cpumask);
832
833 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
834 } else {
835 u32 mask = cpumask_bits(cpumask)[0];
836
837 mask &= cpumask_bits(cpu_online_mask)[0];
838
839 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
840 mpic_physmask(mask));
841 }
842
843 return IRQ_SET_MASK_OK;
844}
845
846static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
847{
848
849 switch(type & IRQ_TYPE_SENSE_MASK) {
850 case IRQ_TYPE_EDGE_RISING:
851 return MPIC_INFO(VECPRI_SENSE_EDGE) |
852 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
853 case IRQ_TYPE_EDGE_FALLING:
854 case IRQ_TYPE_EDGE_BOTH:
855 return MPIC_INFO(VECPRI_SENSE_EDGE) |
856 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
857 case IRQ_TYPE_LEVEL_HIGH:
858 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
859 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
860 case IRQ_TYPE_LEVEL_LOW:
861 default:
862 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
863 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
864 }
865}
866
867int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
868{
869 struct mpic *mpic = mpic_from_irq_data(d);
870 unsigned int src = irqd_to_hwirq(d);
871 unsigned int vecpri, vold, vnew;
872
873 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
874 mpic, d->irq, src, flow_type);
875
876 if (src >= mpic->num_sources)
877 return -EINVAL;
878
879 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
880
881
882 if (flow_type == IRQ_TYPE_NONE)
883 flow_type = IRQ_TYPE_DEFAULT;
884
885
886 if (flow_type == IRQ_TYPE_DEFAULT) {
887 int vold_ps;
888
889 vold_ps = vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
890 MPIC_INFO(VECPRI_SENSE_MASK));
891
892 if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
893 MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
894 flow_type = IRQ_TYPE_EDGE_RISING;
895 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
896 MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
897 flow_type = IRQ_TYPE_EDGE_FALLING;
898 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
899 MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
900 flow_type = IRQ_TYPE_LEVEL_HIGH;
901 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
902 MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
903 flow_type = IRQ_TYPE_LEVEL_LOW;
904 else
905 WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold);
906 }
907
908
909 irqd_set_trigger_type(d, flow_type);
910
911
912 if (mpic_is_ht_interrupt(mpic, src))
913 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
914 MPIC_VECPRI_SENSE_EDGE;
915 else
916 vecpri = mpic_type_to_vecpri(mpic, flow_type);
917
918 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
919 MPIC_INFO(VECPRI_SENSE_MASK));
920 vnew |= vecpri;
921 if (vold != vnew)
922 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
923
924 return IRQ_SET_MASK_OK_NOCOPY;
925}
926
927void mpic_set_vector(unsigned int virq, unsigned int vector)
928{
929 struct mpic *mpic = mpic_from_irq(virq);
930 unsigned int src = virq_to_hw(virq);
931 unsigned int vecpri;
932
933 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
934 mpic, virq, src, vector);
935
936 if (src >= mpic->num_sources)
937 return;
938
939 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
940 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
941 vecpri |= vector;
942 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
943}
944
945static void mpic_set_destination(unsigned int virq, unsigned int cpuid)
946{
947 struct mpic *mpic = mpic_from_irq(virq);
948 unsigned int src = virq_to_hw(virq);
949
950 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
951 mpic, virq, src, cpuid);
952
953 if (src >= mpic->num_sources)
954 return;
955
956 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
957}
958
959static struct irq_chip mpic_irq_chip = {
960 .irq_mask = mpic_mask_irq,
961 .irq_unmask = mpic_unmask_irq,
962 .irq_eoi = mpic_end_irq,
963 .irq_set_type = mpic_set_irq_type,
964};
965
966#ifdef CONFIG_SMP
967static const struct irq_chip mpic_ipi_chip = {
968 .irq_mask = mpic_mask_ipi,
969 .irq_unmask = mpic_unmask_ipi,
970 .irq_eoi = mpic_end_ipi,
971};
972#endif
973
974static struct irq_chip mpic_tm_chip = {
975 .irq_mask = mpic_mask_tm,
976 .irq_unmask = mpic_unmask_tm,
977 .irq_eoi = mpic_end_irq,
978};
979
980#ifdef CONFIG_MPIC_U3_HT_IRQS
981static const struct irq_chip mpic_irq_ht_chip = {
982 .irq_startup = mpic_startup_ht_irq,
983 .irq_shutdown = mpic_shutdown_ht_irq,
984 .irq_mask = mpic_mask_irq,
985 .irq_unmask = mpic_unmask_ht_irq,
986 .irq_eoi = mpic_end_ht_irq,
987 .irq_set_type = mpic_set_irq_type,
988};
989#endif
990
991
992static int mpic_host_match(struct irq_domain *h, struct device_node *node,
993 enum irq_domain_bus_token bus_token)
994{
995
996 struct device_node *of_node = irq_domain_get_of_node(h);
997 return of_node == NULL || of_node == node;
998}
999
1000static int mpic_host_map(struct irq_domain *h, unsigned int virq,
1001 irq_hw_number_t hw)
1002{
1003 struct mpic *mpic = h->host_data;
1004 struct irq_chip *chip;
1005
1006 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1007
1008 if (hw == mpic->spurious_vec)
1009 return -EINVAL;
1010 if (mpic->protected && test_bit(hw, mpic->protected)) {
1011 pr_warn("mpic: Mapping of source 0x%x failed, source protected by firmware !\n",
1012 (unsigned int)hw);
1013 return -EPERM;
1014 }
1015
1016#ifdef CONFIG_SMP
1017 else if (hw >= mpic->ipi_vecs[0]) {
1018 WARN_ON(mpic->flags & MPIC_SECONDARY);
1019
1020 DBG("mpic: mapping as IPI\n");
1021 irq_set_chip_data(virq, mpic);
1022 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1023 handle_percpu_irq);
1024 return 0;
1025 }
1026#endif
1027
1028 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1029 WARN_ON(mpic->flags & MPIC_SECONDARY);
1030
1031 DBG("mpic: mapping as timer\n");
1032 irq_set_chip_data(virq, mpic);
1033 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1034 handle_fasteoi_irq);
1035 return 0;
1036 }
1037
1038 if (mpic_map_error_int(mpic, virq, hw))
1039 return 0;
1040
1041 if (hw >= mpic->num_sources) {
1042 pr_warn("mpic: Mapping of source 0x%x failed, source out of range !\n",
1043 (unsigned int)hw);
1044 return -EINVAL;
1045 }
1046
1047 mpic_msi_reserve_hwirq(mpic, hw);
1048
1049
1050 chip = &mpic->hc_irq;
1051
1052#ifdef CONFIG_MPIC_U3_HT_IRQS
1053
1054 if (mpic_is_ht_interrupt(mpic, hw))
1055 chip = &mpic->hc_ht_irq;
1056#endif
1057
1058 DBG("mpic: mapping to irq chip @%p\n", chip);
1059
1060 irq_set_chip_data(virq, mpic);
1061 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1062
1063
1064 irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
1065
1066
1067
1068
1069
1070 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1071 int cpu;
1072
1073 preempt_disable();
1074 cpu = mpic_processor_id(mpic);
1075 preempt_enable();
1076
1077 mpic_set_vector(virq, hw);
1078 mpic_set_destination(virq, cpu);
1079 mpic_irq_set_priority(virq, 8);
1080 }
1081
1082 return 0;
1083}
1084
1085static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
1086 const u32 *intspec, unsigned int intsize,
1087 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1088
1089{
1090 struct mpic *mpic = h->host_data;
1091 static unsigned char map_mpic_senses[4] = {
1092 IRQ_TYPE_EDGE_RISING,
1093 IRQ_TYPE_LEVEL_LOW,
1094 IRQ_TYPE_LEVEL_HIGH,
1095 IRQ_TYPE_EDGE_FALLING,
1096 };
1097
1098 *out_hwirq = intspec[0];
1099 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1100
1101
1102
1103
1104
1105
1106
1107 switch (intspec[2]) {
1108 case 0:
1109 break;
1110 case 1:
1111 if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
1112 break;
1113
1114 if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
1115 return -EINVAL;
1116
1117 *out_hwirq = mpic->err_int_vecs[intspec[3]];
1118
1119 break;
1120 case 2:
1121 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1122 return -EINVAL;
1123
1124 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1125 break;
1126 case 3:
1127 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1128 return -EINVAL;
1129
1130 *out_hwirq = mpic->timer_vecs[intspec[0]];
1131 break;
1132 default:
1133 pr_debug("%s: unknown irq type %u\n",
1134 __func__, intspec[2]);
1135 return -EINVAL;
1136 }
1137
1138 *out_flags = map_mpic_senses[intspec[1] & 3];
1139 } else if (intsize > 1) {
1140 u32 mask = 0x3;
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152 if (machine_is(powermac))
1153 mask = 0x1;
1154 *out_flags = map_mpic_senses[intspec[1] & mask];
1155 } else
1156 *out_flags = IRQ_TYPE_NONE;
1157
1158 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1159 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1160
1161 return 0;
1162}
1163
1164
1165static void mpic_cascade(struct irq_desc *desc)
1166{
1167 struct irq_chip *chip = irq_desc_get_chip(desc);
1168 struct mpic *mpic = irq_desc_get_handler_data(desc);
1169 unsigned int virq;
1170
1171 BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1172
1173 virq = mpic_get_one_irq(mpic);
1174 if (virq)
1175 generic_handle_irq(virq);
1176
1177 chip->irq_eoi(&desc->irq_data);
1178}
1179
1180static const struct irq_domain_ops mpic_host_ops = {
1181 .match = mpic_host_match,
1182 .map = mpic_host_map,
1183 .xlate = mpic_host_xlate,
1184};
1185
1186static u32 fsl_mpic_get_version(struct mpic *mpic)
1187{
1188 u32 brr1;
1189
1190 if (!(mpic->flags & MPIC_FSL))
1191 return 0;
1192
1193 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1194 MPIC_FSL_BRR1);
1195
1196 return brr1 & MPIC_FSL_BRR1_VER;
1197}
1198
1199
1200
1201
1202
1203u32 fsl_mpic_primary_get_version(void)
1204{
1205 struct mpic *mpic = mpic_primary;
1206
1207 if (mpic)
1208 return fsl_mpic_get_version(mpic);
1209
1210 return 0;
1211}
1212
1213struct mpic * __init mpic_alloc(struct device_node *node,
1214 phys_addr_t phys_addr,
1215 unsigned int flags,
1216 unsigned int isu_size,
1217 unsigned int irq_count,
1218 const char *name)
1219{
1220 int i, psize, intvec_top;
1221 struct mpic *mpic;
1222 u32 greg_feature;
1223 const char *vers;
1224 const u32 *psrc;
1225 u32 last_irq;
1226 u32 fsl_version = 0;
1227
1228
1229 static const struct of_device_id __initconst mpic_device_id[] = {
1230 { .type = "open-pic", },
1231 { .compatible = "open-pic", },
1232 {},
1233 };
1234
1235
1236
1237
1238
1239 if (node) {
1240 node = of_node_get(node);
1241 } else {
1242 node = of_find_matching_node(NULL, mpic_device_id);
1243 if (!node)
1244 return NULL;
1245 }
1246
1247
1248 if (!phys_addr) {
1249
1250 if (of_property_read_bool(node, "dcr-reg")) {
1251 flags |= MPIC_USES_DCR;
1252 } else {
1253 struct resource r;
1254 if (of_address_to_resource(node, 0, &r))
1255 goto err_of_node_put;
1256 phys_addr = r.start;
1257 }
1258 }
1259
1260
1261 if (of_get_property(node, "big-endian", NULL))
1262 flags |= MPIC_BIG_ENDIAN;
1263 if (of_get_property(node, "pic-no-reset", NULL))
1264 flags |= MPIC_NO_RESET;
1265 if (of_get_property(node, "single-cpu-affinity", NULL))
1266 flags |= MPIC_SINGLE_DEST_CPU;
1267 if (of_device_is_compatible(node, "fsl,mpic")) {
1268 flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
1269 mpic_irq_chip.flags |= IRQCHIP_SKIP_SET_WAKE;
1270 mpic_tm_chip.flags |= IRQCHIP_SKIP_SET_WAKE;
1271 }
1272
1273 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1274 if (mpic == NULL)
1275 goto err_of_node_put;
1276
1277 mpic->name = name;
1278 mpic->node = node;
1279 mpic->paddr = phys_addr;
1280 mpic->flags = flags;
1281
1282 mpic->hc_irq = mpic_irq_chip;
1283 mpic->hc_irq.name = name;
1284 if (!(mpic->flags & MPIC_SECONDARY))
1285 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1286#ifdef CONFIG_MPIC_U3_HT_IRQS
1287 mpic->hc_ht_irq = mpic_irq_ht_chip;
1288 mpic->hc_ht_irq.name = name;
1289 if (!(mpic->flags & MPIC_SECONDARY))
1290 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1291#endif
1292
1293#ifdef CONFIG_SMP
1294 mpic->hc_ipi = mpic_ipi_chip;
1295 mpic->hc_ipi.name = name;
1296#endif
1297
1298 mpic->hc_tm = mpic_tm_chip;
1299 mpic->hc_tm.name = name;
1300
1301 mpic->num_sources = 0;
1302
1303 if (mpic->flags & MPIC_LARGE_VECTORS)
1304 intvec_top = 2047;
1305 else
1306 intvec_top = 255;
1307
1308 mpic->timer_vecs[0] = intvec_top - 12;
1309 mpic->timer_vecs[1] = intvec_top - 11;
1310 mpic->timer_vecs[2] = intvec_top - 10;
1311 mpic->timer_vecs[3] = intvec_top - 9;
1312 mpic->timer_vecs[4] = intvec_top - 8;
1313 mpic->timer_vecs[5] = intvec_top - 7;
1314 mpic->timer_vecs[6] = intvec_top - 6;
1315 mpic->timer_vecs[7] = intvec_top - 5;
1316 mpic->ipi_vecs[0] = intvec_top - 4;
1317 mpic->ipi_vecs[1] = intvec_top - 3;
1318 mpic->ipi_vecs[2] = intvec_top - 2;
1319 mpic->ipi_vecs[3] = intvec_top - 1;
1320 mpic->spurious_vec = intvec_top;
1321
1322
1323 psrc = of_get_property(mpic->node, "protected-sources", &psize);
1324 if (psrc) {
1325
1326 mpic->protected = bitmap_zalloc(intvec_top + 1, GFP_KERNEL);
1327 BUG_ON(mpic->protected == NULL);
1328 for (i = 0; i < psize/sizeof(u32); i++) {
1329 if (psrc[i] > intvec_top)
1330 continue;
1331 __set_bit(psrc[i], mpic->protected);
1332 }
1333 }
1334
1335#ifdef CONFIG_MPIC_WEIRD
1336 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1337#endif
1338
1339
1340 if (mpic->flags & MPIC_BIG_ENDIAN)
1341 mpic->reg_type = mpic_access_mmio_be;
1342 else
1343 mpic->reg_type = mpic_access_mmio_le;
1344
1345
1346
1347
1348
1349#ifdef CONFIG_PPC_DCR
1350 if (mpic->flags & MPIC_USES_DCR)
1351 mpic->reg_type = mpic_access_dcr;
1352#else
1353 BUG_ON(mpic->flags & MPIC_USES_DCR);
1354#endif
1355
1356
1357 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1358 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1359
1360 if (mpic->flags & MPIC_FSL) {
1361 int ret;
1362
1363
1364
1365
1366
1367
1368 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
1369 MPIC_CPU_THISBASE, 0x1000);
1370
1371 fsl_version = fsl_mpic_get_version(mpic);
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386 if (fsl_version >= 0x401) {
1387 ret = mpic_setup_error_int(mpic, intvec_top - 13);
1388 if (ret)
1389 return NULL;
1390 }
1391
1392 }
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407 if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT))
1408 ppc_md.get_irq = mpic_get_irq;
1409
1410
1411
1412
1413
1414
1415 if (!(mpic->flags & MPIC_NO_RESET)) {
1416 printk(KERN_DEBUG "mpic: Resetting\n");
1417 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1418 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1419 | MPIC_GREG_GCONF_RESET);
1420 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1421 & MPIC_GREG_GCONF_RESET)
1422 mb();
1423 }
1424
1425
1426 if (mpic->flags & MPIC_ENABLE_COREINT)
1427 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1428 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1429 | MPIC_GREG_GCONF_COREINT);
1430
1431 if (mpic->flags & MPIC_ENABLE_MCK)
1432 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1433 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1434 | MPIC_GREG_GCONF_MCK);
1435
1436
1437
1438
1439
1440 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1441
1442
1443 for_each_possible_cpu(i) {
1444 unsigned int cpu = get_hard_smp_processor_id(i);
1445
1446 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1447 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1448 0x1000);
1449 }
1450
1451
1452
1453
1454
1455 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1456
1457
1458
1459
1460
1461
1462
1463 last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1464 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;
1465 if (isu_size)
1466 last_irq = isu_size * MPIC_MAX_ISU - 1;
1467 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1468 if (irq_count)
1469 last_irq = irq_count - 1;
1470
1471
1472 if (!isu_size) {
1473 isu_size = last_irq + 1;
1474 mpic->num_sources = isu_size;
1475 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1476 MPIC_INFO(IRQ_BASE),
1477 MPIC_INFO(IRQ_STRIDE) * isu_size);
1478 }
1479
1480 mpic->isu_size = isu_size;
1481 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1482 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1483
1484 mpic->irqhost = irq_domain_add_linear(mpic->node,
1485 intvec_top,
1486 &mpic_host_ops, mpic);
1487
1488
1489
1490
1491
1492 if (mpic->irqhost == NULL)
1493 return NULL;
1494
1495
1496 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1497 case 1:
1498 vers = "1.0";
1499 break;
1500 case 2:
1501 vers = "1.2";
1502 break;
1503 case 3:
1504 vers = "1.3";
1505 break;
1506 default:
1507 vers = "<unknown>";
1508 break;
1509 }
1510 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1511 " max %d CPUs\n",
1512 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1513 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1514 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1515
1516 mpic->next = mpics;
1517 mpics = mpic;
1518
1519 if (!(mpic->flags & MPIC_SECONDARY)) {
1520 mpic_primary = mpic;
1521 irq_set_default_host(mpic->irqhost);
1522 }
1523
1524 return mpic;
1525
1526err_of_node_put:
1527 of_node_put(node);
1528 return NULL;
1529}
1530
1531void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1532 phys_addr_t paddr)
1533{
1534 unsigned int isu_first = isu_num * mpic->isu_size;
1535
1536 BUG_ON(isu_num >= MPIC_MAX_ISU);
1537
1538 mpic_map(mpic,
1539 paddr, &mpic->isus[isu_num], 0,
1540 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1541
1542 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1543 mpic->num_sources = isu_first + mpic->isu_size;
1544}
1545
1546void __init mpic_init(struct mpic *mpic)
1547{
1548 int i, cpu;
1549 int num_timers = 4;
1550
1551 BUG_ON(mpic->num_sources == 0);
1552
1553 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1554
1555
1556 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1557
1558 if (mpic->flags & MPIC_FSL) {
1559 u32 version = fsl_mpic_get_version(mpic);
1560
1561
1562
1563
1564
1565
1566
1567 if (version >= 0x0301)
1568 num_timers = 8;
1569 }
1570
1571
1572 for (i = 0; i < num_timers; i++) {
1573 unsigned int offset = mpic_tm_offset(mpic, i);
1574
1575 mpic_write(mpic->tmregs,
1576 offset + MPIC_INFO(TIMER_DESTINATION),
1577 1 << hard_smp_processor_id());
1578 mpic_write(mpic->tmregs,
1579 offset + MPIC_INFO(TIMER_VECTOR_PRI),
1580 MPIC_VECPRI_MASK |
1581 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1582 (mpic->timer_vecs[0] + i));
1583 }
1584
1585
1586 mpic_test_broken_ipi(mpic);
1587 for (i = 0; i < 4; i++) {
1588 mpic_ipi_write(i,
1589 MPIC_VECPRI_MASK |
1590 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1591 (mpic->ipi_vecs[0] + i));
1592 }
1593
1594
1595 DBG("MPIC flags: %x\n", mpic->flags);
1596 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1597 mpic_scan_ht_pics(mpic);
1598 mpic_u3msi_init(mpic);
1599 }
1600
1601 mpic_pasemi_msi_init(mpic);
1602
1603 cpu = mpic_processor_id(mpic);
1604
1605 if (!(mpic->flags & MPIC_NO_RESET)) {
1606 for (i = 0; i < mpic->num_sources; i++) {
1607
1608 u32 vecpri = MPIC_VECPRI_MASK | i |
1609 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1610
1611
1612 if (mpic->protected && test_bit(i, mpic->protected))
1613 continue;
1614
1615 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1616 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1617 }
1618 }
1619
1620
1621 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1622
1623
1624 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1625 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1626 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1627 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1628
1629 if (mpic->flags & MPIC_NO_BIAS)
1630 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1631 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1632 | MPIC_GREG_GCONF_NO_BIAS);
1633
1634
1635 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1636
1637#ifdef CONFIG_PM
1638
1639 mpic->save_data = kmalloc_array(mpic->num_sources,
1640 sizeof(*mpic->save_data),
1641 GFP_KERNEL);
1642 BUG_ON(mpic->save_data == NULL);
1643#endif
1644
1645
1646 if (mpic->flags & MPIC_SECONDARY) {
1647 int virq = irq_of_parse_and_map(mpic->node, 0);
1648 if (virq) {
1649 printk(KERN_INFO "%pOF: hooking up to IRQ %d\n",
1650 mpic->node, virq);
1651 irq_set_handler_data(virq, mpic);
1652 irq_set_chained_handler(virq, &mpic_cascade);
1653 }
1654 }
1655
1656
1657 if (mpic->flags & MPIC_FSL_HAS_EIMR)
1658 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1659}
1660
1661void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1662{
1663 struct mpic *mpic = mpic_find(irq);
1664 unsigned int src = virq_to_hw(irq);
1665 unsigned long flags;
1666 u32 reg;
1667
1668 if (!mpic)
1669 return;
1670
1671 raw_spin_lock_irqsave(&mpic_lock, flags);
1672 if (mpic_is_ipi(mpic, src)) {
1673 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1674 ~MPIC_VECPRI_PRIORITY_MASK;
1675 mpic_ipi_write(src - mpic->ipi_vecs[0],
1676 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1677 } else if (mpic_is_tm(mpic, src)) {
1678 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1679 ~MPIC_VECPRI_PRIORITY_MASK;
1680 mpic_tm_write(src - mpic->timer_vecs[0],
1681 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1682 } else {
1683 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1684 & ~MPIC_VECPRI_PRIORITY_MASK;
1685 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1686 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1687 }
1688 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1689}
1690
1691void mpic_setup_this_cpu(void)
1692{
1693#ifdef CONFIG_SMP
1694 struct mpic *mpic = mpic_primary;
1695 unsigned long flags;
1696 u32 msk = 1 << hard_smp_processor_id();
1697 unsigned int i;
1698
1699 BUG_ON(mpic == NULL);
1700
1701 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1702
1703 raw_spin_lock_irqsave(&mpic_lock, flags);
1704
1705
1706
1707
1708
1709
1710 if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) {
1711 for (i = 0; i < mpic->num_sources ; i++)
1712 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1713 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1714 }
1715
1716
1717 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1718
1719 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1720#endif
1721}
1722
1723int mpic_cpu_get_priority(void)
1724{
1725 struct mpic *mpic = mpic_primary;
1726
1727 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1728}
1729
1730void mpic_cpu_set_priority(int prio)
1731{
1732 struct mpic *mpic = mpic_primary;
1733
1734 prio &= MPIC_CPU_TASKPRI_MASK;
1735 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1736}
1737
1738void mpic_teardown_this_cpu(int secondary)
1739{
1740 struct mpic *mpic = mpic_primary;
1741 unsigned long flags;
1742 u32 msk = 1 << hard_smp_processor_id();
1743 unsigned int i;
1744
1745 BUG_ON(mpic == NULL);
1746
1747 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1748 raw_spin_lock_irqsave(&mpic_lock, flags);
1749
1750
1751 for (i = 0; i < mpic->num_sources ; i++)
1752 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1753 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1754
1755
1756 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1757
1758
1759
1760 mpic_eoi(mpic);
1761
1762 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1763}
1764
1765
1766static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1767{
1768 u32 src;
1769
1770 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1771#ifdef DEBUG_LOW
1772 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1773#endif
1774 if (unlikely(src == mpic->spurious_vec)) {
1775 if (mpic->flags & MPIC_SPV_EOI)
1776 mpic_eoi(mpic);
1777 return 0;
1778 }
1779 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1780 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1781 mpic->name, (int)src);
1782 mpic_eoi(mpic);
1783 return 0;
1784 }
1785
1786 return irq_linear_revmap(mpic->irqhost, src);
1787}
1788
1789unsigned int mpic_get_one_irq(struct mpic *mpic)
1790{
1791 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1792}
1793
1794unsigned int mpic_get_irq(void)
1795{
1796 struct mpic *mpic = mpic_primary;
1797
1798 BUG_ON(mpic == NULL);
1799
1800 return mpic_get_one_irq(mpic);
1801}
1802
1803unsigned int mpic_get_coreint_irq(void)
1804{
1805#ifdef CONFIG_BOOKE
1806 struct mpic *mpic = mpic_primary;
1807 u32 src;
1808
1809 BUG_ON(mpic == NULL);
1810
1811 src = mfspr(SPRN_EPR);
1812
1813 if (unlikely(src == mpic->spurious_vec)) {
1814 if (mpic->flags & MPIC_SPV_EOI)
1815 mpic_eoi(mpic);
1816 return 0;
1817 }
1818 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1819 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1820 mpic->name, (int)src);
1821 return 0;
1822 }
1823
1824 return irq_linear_revmap(mpic->irqhost, src);
1825#else
1826 return 0;
1827#endif
1828}
1829
1830unsigned int mpic_get_mcirq(void)
1831{
1832 struct mpic *mpic = mpic_primary;
1833
1834 BUG_ON(mpic == NULL);
1835
1836 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1837}
1838
1839#ifdef CONFIG_SMP
1840void __init mpic_request_ipis(void)
1841{
1842 struct mpic *mpic = mpic_primary;
1843 int i;
1844 BUG_ON(mpic == NULL);
1845
1846 printk(KERN_INFO "mpic: requesting IPIs...\n");
1847
1848 for (i = 0; i < 4; i++) {
1849 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1850 mpic->ipi_vecs[0] + i);
1851 if (!vipi) {
1852 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1853 continue;
1854 }
1855 smp_request_message_ipi(vipi, i);
1856 }
1857}
1858
1859void smp_mpic_message_pass(int cpu, int msg)
1860{
1861 struct mpic *mpic = mpic_primary;
1862 u32 physmask;
1863
1864 BUG_ON(mpic == NULL);
1865
1866
1867 if ((unsigned int)msg > 3) {
1868 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1869 smp_processor_id(), msg);
1870 return;
1871 }
1872
1873#ifdef DEBUG_IPI
1874 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1875#endif
1876
1877 physmask = 1 << get_hard_smp_processor_id(cpu);
1878
1879 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1880 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1881}
1882
1883void __init smp_mpic_probe(void)
1884{
1885 int nr_cpus;
1886
1887 DBG("smp_mpic_probe()...\n");
1888
1889 nr_cpus = num_possible_cpus();
1890
1891 DBG("nr_cpus: %d\n", nr_cpus);
1892
1893 if (nr_cpus > 1)
1894 mpic_request_ipis();
1895}
1896
1897void smp_mpic_setup_cpu(int cpu)
1898{
1899 mpic_setup_this_cpu();
1900}
1901
1902void mpic_reset_core(int cpu)
1903{
1904 struct mpic *mpic = mpic_primary;
1905 u32 pir;
1906 int cpuid = get_hard_smp_processor_id(cpu);
1907 int i;
1908
1909
1910 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1911 pir |= (1 << cpuid);
1912 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1913 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1914
1915
1916 pir &= ~(1 << cpuid);
1917 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1918 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1919
1920
1921
1922 if (mpic->flags & MPIC_FSL) {
1923 for (i = 0; i < 15; i++) {
1924 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1925 MPIC_CPU_EOI, 0);
1926 }
1927 }
1928}
1929#endif
1930
1931#ifdef CONFIG_PM
1932static void mpic_suspend_one(struct mpic *mpic)
1933{
1934 int i;
1935
1936 for (i = 0; i < mpic->num_sources; i++) {
1937 mpic->save_data[i].vecprio =
1938 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1939 mpic->save_data[i].dest =
1940 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1941 }
1942}
1943
1944static int mpic_suspend(void)
1945{
1946 struct mpic *mpic = mpics;
1947
1948 while (mpic) {
1949 mpic_suspend_one(mpic);
1950 mpic = mpic->next;
1951 }
1952
1953 return 0;
1954}
1955
1956static void mpic_resume_one(struct mpic *mpic)
1957{
1958 int i;
1959
1960 for (i = 0; i < mpic->num_sources; i++) {
1961 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1962 mpic->save_data[i].vecprio);
1963 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1964 mpic->save_data[i].dest);
1965
1966#ifdef CONFIG_MPIC_U3_HT_IRQS
1967 if (mpic->fixups) {
1968 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1969
1970 if (fixup->base) {
1971
1972 if ((mpic->save_data[i].fixup_data & 1) == 0)
1973 continue;
1974
1975
1976 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1977
1978 writel(mpic->save_data[i].fixup_data & ~1,
1979 fixup->base + 4);
1980 }
1981 }
1982#endif
1983 }
1984}
1985
1986static void mpic_resume(void)
1987{
1988 struct mpic *mpic = mpics;
1989
1990 while (mpic) {
1991 mpic_resume_one(mpic);
1992 mpic = mpic->next;
1993 }
1994}
1995
1996static struct syscore_ops mpic_syscore_ops = {
1997 .resume = mpic_resume,
1998 .suspend = mpic_suspend,
1999};
2000
2001static int mpic_init_sys(void)
2002{
2003 int rc;
2004
2005 register_syscore_ops(&mpic_syscore_ops);
2006 rc = subsys_system_register(&mpic_subsys, NULL);
2007 if (rc) {
2008 unregister_syscore_ops(&mpic_syscore_ops);
2009 pr_err("mpic: Failed to register subsystem!\n");
2010 return rc;
2011 }
2012
2013 return 0;
2014}
2015
2016device_initcall(mpic_init_sys);
2017#endif
2018