1
2
3
4
5
6
7#include <linux/platform_device.h>
8#include <linux/init.h>
9#include <linux/serial.h>
10#include <linux/mm.h>
11#include <linux/serial_sci.h>
12#include <linux/uio_driver.h>
13#include <linux/usb/r8a66597.h>
14#include <linux/sh_timer.h>
15#include <linux/sh_intc.h>
16#include <linux/io.h>
17#include <asm/clock.h>
18#include <asm/mmzone.h>
19#include <asm/platform_early.h>
20#include <cpu/sh7723.h>
21
22
23static struct plat_sci_port scif0_platform_data = {
24 .scscr = SCSCR_REIE,
25 .type = PORT_SCIF,
26 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
27};
28
29static struct resource scif0_resources[] = {
30 DEFINE_RES_MEM(0xffe00000, 0x100),
31 DEFINE_RES_IRQ(evt2irq(0xc00)),
32};
33
34static struct platform_device scif0_device = {
35 .name = "sh-sci",
36 .id = 0,
37 .resource = scif0_resources,
38 .num_resources = ARRAY_SIZE(scif0_resources),
39 .dev = {
40 .platform_data = &scif0_platform_data,
41 },
42};
43
44static struct plat_sci_port scif1_platform_data = {
45 .scscr = SCSCR_REIE,
46 .type = PORT_SCIF,
47 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
48};
49
50static struct resource scif1_resources[] = {
51 DEFINE_RES_MEM(0xffe10000, 0x100),
52 DEFINE_RES_IRQ(evt2irq(0xc20)),
53};
54
55static struct platform_device scif1_device = {
56 .name = "sh-sci",
57 .id = 1,
58 .resource = scif1_resources,
59 .num_resources = ARRAY_SIZE(scif1_resources),
60 .dev = {
61 .platform_data = &scif1_platform_data,
62 },
63};
64
65static struct plat_sci_port scif2_platform_data = {
66 .scscr = SCSCR_REIE,
67 .type = PORT_SCIF,
68 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
69};
70
71static struct resource scif2_resources[] = {
72 DEFINE_RES_MEM(0xffe20000, 0x100),
73 DEFINE_RES_IRQ(evt2irq(0xc40)),
74};
75
76static struct platform_device scif2_device = {
77 .name = "sh-sci",
78 .id = 2,
79 .resource = scif2_resources,
80 .num_resources = ARRAY_SIZE(scif2_resources),
81 .dev = {
82 .platform_data = &scif2_platform_data,
83 },
84};
85
86static struct plat_sci_port scif3_platform_data = {
87 .sampling_rate = 8,
88 .type = PORT_SCIFA,
89};
90
91static struct resource scif3_resources[] = {
92 DEFINE_RES_MEM(0xa4e30000, 0x100),
93 DEFINE_RES_IRQ(evt2irq(0x900)),
94};
95
96static struct platform_device scif3_device = {
97 .name = "sh-sci",
98 .id = 3,
99 .resource = scif3_resources,
100 .num_resources = ARRAY_SIZE(scif3_resources),
101 .dev = {
102 .platform_data = &scif3_platform_data,
103 },
104};
105
106static struct plat_sci_port scif4_platform_data = {
107 .sampling_rate = 8,
108 .type = PORT_SCIFA,
109};
110
111static struct resource scif4_resources[] = {
112 DEFINE_RES_MEM(0xa4e40000, 0x100),
113 DEFINE_RES_IRQ(evt2irq(0xd00)),
114};
115
116static struct platform_device scif4_device = {
117 .name = "sh-sci",
118 .id = 4,
119 .resource = scif4_resources,
120 .num_resources = ARRAY_SIZE(scif4_resources),
121 .dev = {
122 .platform_data = &scif4_platform_data,
123 },
124};
125
126static struct plat_sci_port scif5_platform_data = {
127 .sampling_rate = 8,
128 .type = PORT_SCIFA,
129};
130
131static struct resource scif5_resources[] = {
132 DEFINE_RES_MEM(0xa4e50000, 0x100),
133 DEFINE_RES_IRQ(evt2irq(0xfa0)),
134};
135
136static struct platform_device scif5_device = {
137 .name = "sh-sci",
138 .id = 5,
139 .resource = scif5_resources,
140 .num_resources = ARRAY_SIZE(scif5_resources),
141 .dev = {
142 .platform_data = &scif5_platform_data,
143 },
144};
145
146static struct uio_info vpu_platform_data = {
147 .name = "VPU5",
148 .version = "0",
149 .irq = evt2irq(0x980),
150};
151
152static struct resource vpu_resources[] = {
153 [0] = {
154 .name = "VPU",
155 .start = 0xfe900000,
156 .end = 0xfe902807,
157 .flags = IORESOURCE_MEM,
158 },
159 [1] = {
160
161 },
162};
163
164static struct platform_device vpu_device = {
165 .name = "uio_pdrv_genirq",
166 .id = 0,
167 .dev = {
168 .platform_data = &vpu_platform_data,
169 },
170 .resource = vpu_resources,
171 .num_resources = ARRAY_SIZE(vpu_resources),
172};
173
174static struct uio_info veu0_platform_data = {
175 .name = "VEU2H",
176 .version = "0",
177 .irq = evt2irq(0x8c0),
178};
179
180static struct resource veu0_resources[] = {
181 [0] = {
182 .name = "VEU2H0",
183 .start = 0xfe920000,
184 .end = 0xfe92027b,
185 .flags = IORESOURCE_MEM,
186 },
187 [1] = {
188
189 },
190};
191
192static struct platform_device veu0_device = {
193 .name = "uio_pdrv_genirq",
194 .id = 1,
195 .dev = {
196 .platform_data = &veu0_platform_data,
197 },
198 .resource = veu0_resources,
199 .num_resources = ARRAY_SIZE(veu0_resources),
200};
201
202static struct uio_info veu1_platform_data = {
203 .name = "VEU2H",
204 .version = "0",
205 .irq = evt2irq(0x560),
206};
207
208static struct resource veu1_resources[] = {
209 [0] = {
210 .name = "VEU2H1",
211 .start = 0xfe924000,
212 .end = 0xfe92427b,
213 .flags = IORESOURCE_MEM,
214 },
215 [1] = {
216
217 },
218};
219
220static struct platform_device veu1_device = {
221 .name = "uio_pdrv_genirq",
222 .id = 2,
223 .dev = {
224 .platform_data = &veu1_platform_data,
225 },
226 .resource = veu1_resources,
227 .num_resources = ARRAY_SIZE(veu1_resources),
228};
229
230static struct sh_timer_config cmt_platform_data = {
231 .channels_mask = 0x20,
232};
233
234static struct resource cmt_resources[] = {
235 DEFINE_RES_MEM(0x044a0000, 0x70),
236 DEFINE_RES_IRQ(evt2irq(0xf00)),
237};
238
239static struct platform_device cmt_device = {
240 .name = "sh-cmt-32",
241 .id = 0,
242 .dev = {
243 .platform_data = &cmt_platform_data,
244 },
245 .resource = cmt_resources,
246 .num_resources = ARRAY_SIZE(cmt_resources),
247};
248
249static struct sh_timer_config tmu0_platform_data = {
250 .channels_mask = 7,
251};
252
253static struct resource tmu0_resources[] = {
254 DEFINE_RES_MEM(0xffd80000, 0x2c),
255 DEFINE_RES_IRQ(evt2irq(0x400)),
256 DEFINE_RES_IRQ(evt2irq(0x420)),
257 DEFINE_RES_IRQ(evt2irq(0x440)),
258};
259
260static struct platform_device tmu0_device = {
261 .name = "sh-tmu",
262 .id = 0,
263 .dev = {
264 .platform_data = &tmu0_platform_data,
265 },
266 .resource = tmu0_resources,
267 .num_resources = ARRAY_SIZE(tmu0_resources),
268};
269
270static struct sh_timer_config tmu1_platform_data = {
271 .channels_mask = 7,
272};
273
274static struct resource tmu1_resources[] = {
275 DEFINE_RES_MEM(0xffd90000, 0x2c),
276 DEFINE_RES_IRQ(evt2irq(0x920)),
277 DEFINE_RES_IRQ(evt2irq(0x940)),
278 DEFINE_RES_IRQ(evt2irq(0x960)),
279};
280
281static struct platform_device tmu1_device = {
282 .name = "sh-tmu",
283 .id = 1,
284 .dev = {
285 .platform_data = &tmu1_platform_data,
286 },
287 .resource = tmu1_resources,
288 .num_resources = ARRAY_SIZE(tmu1_resources),
289};
290
291static struct resource rtc_resources[] = {
292 [0] = {
293 .start = 0xa465fec0,
294 .end = 0xa465fec0 + 0x58 - 1,
295 .flags = IORESOURCE_IO,
296 },
297 [1] = {
298
299 .start = evt2irq(0xaa0),
300 .flags = IORESOURCE_IRQ,
301 },
302 [2] = {
303
304 .start = evt2irq(0xac0),
305 .flags = IORESOURCE_IRQ,
306 },
307 [3] = {
308
309 .start = evt2irq(0xa80),
310 .flags = IORESOURCE_IRQ,
311 },
312};
313
314static struct platform_device rtc_device = {
315 .name = "sh-rtc",
316 .id = -1,
317 .num_resources = ARRAY_SIZE(rtc_resources),
318 .resource = rtc_resources,
319};
320
321static struct r8a66597_platdata r8a66597_data = {
322 .on_chip = 1,
323};
324
325static struct resource sh7723_usb_host_resources[] = {
326 [0] = {
327 .start = 0xa4d80000,
328 .end = 0xa4d800ff,
329 .flags = IORESOURCE_MEM,
330 },
331 [1] = {
332 .start = evt2irq(0xa20),
333 .end = evt2irq(0xa20),
334 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
335 },
336};
337
338static struct platform_device sh7723_usb_host_device = {
339 .name = "r8a66597_hcd",
340 .id = 0,
341 .dev = {
342 .dma_mask = NULL,
343 .coherent_dma_mask = 0xffffffff,
344 .platform_data = &r8a66597_data,
345 },
346 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources),
347 .resource = sh7723_usb_host_resources,
348};
349
350static struct resource iic_resources[] = {
351 [0] = {
352 .name = "IIC",
353 .start = 0x04470000,
354 .end = 0x04470017,
355 .flags = IORESOURCE_MEM,
356 },
357 [1] = {
358 .start = evt2irq(0xe00),
359 .end = evt2irq(0xe60),
360 .flags = IORESOURCE_IRQ,
361 },
362};
363
364static struct platform_device iic_device = {
365 .name = "i2c-sh_mobile",
366 .id = 0,
367 .num_resources = ARRAY_SIZE(iic_resources),
368 .resource = iic_resources,
369};
370
371static struct platform_device *sh7723_devices[] __initdata = {
372 &scif0_device,
373 &scif1_device,
374 &scif2_device,
375 &scif3_device,
376 &scif4_device,
377 &scif5_device,
378 &cmt_device,
379 &tmu0_device,
380 &tmu1_device,
381 &rtc_device,
382 &iic_device,
383 &sh7723_usb_host_device,
384 &vpu_device,
385 &veu0_device,
386 &veu1_device,
387};
388
389static int __init sh7723_devices_setup(void)
390{
391 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
392 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
393 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
394
395 return platform_add_devices(sh7723_devices,
396 ARRAY_SIZE(sh7723_devices));
397}
398arch_initcall(sh7723_devices_setup);
399
400static struct platform_device *sh7723_early_devices[] __initdata = {
401 &scif0_device,
402 &scif1_device,
403 &scif2_device,
404 &scif3_device,
405 &scif4_device,
406 &scif5_device,
407 &cmt_device,
408 &tmu0_device,
409 &tmu1_device,
410};
411
412void __init plat_early_device_setup(void)
413{
414 sh_early_platform_add_devices(sh7723_early_devices,
415 ARRAY_SIZE(sh7723_early_devices));
416}
417
418#define RAMCR_CACHE_L2FC 0x0002
419#define RAMCR_CACHE_L2E 0x0001
420#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
421
422void l2_cache_init(void)
423{
424
425 __raw_writel(L2_CACHE_ENABLE, RAMCR);
426}
427
428enum {
429 UNUSED=0,
430 ENABLED,
431 DISABLED,
432
433
434 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
435 HUDI,
436 DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
437 _2DG_TRI,_2DG_INI,_2DG_CEI,
438 DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
439 VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
440 SCIFA_SCIFA0,
441 VPU_VPUI,
442 TPU_TPUI,
443 ADC_ADI,
444 USB_USI0,
445 RTC_ATI,RTC_PRI,RTC_CUI,
446 DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
447 DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
448 KEYSC_KEYI,
449 SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
450 MSIOF_MSIOFI0,MSIOF_MSIOFI1,
451 SCIFA_SCIFA1,
452 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
453 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
454 CMT_CMTI,
455 TSIF_TSIFI,
456 SIU_SIUI,
457 SCIFA_SCIFA2,
458 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
459 IRDA_IRDAI,
460 ATAPI_ATAPII,
461 VEU2H1_VEU2HI,
462 LCDC_LCDCI,
463 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
464
465
466 DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
467 SDHI1, RTC, DMAC1B, SDHI0,
468};
469
470static struct intc_vect vectors[] __initdata = {
471 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
472 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
473 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
474 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
475
476 INTC_VECT(DMAC1A_DEI0,0x700),
477 INTC_VECT(DMAC1A_DEI1,0x720),
478 INTC_VECT(DMAC1A_DEI2,0x740),
479 INTC_VECT(DMAC1A_DEI3,0x760),
480
481 INTC_VECT(_2DG_TRI, 0x780),
482 INTC_VECT(_2DG_INI, 0x7A0),
483 INTC_VECT(_2DG_CEI, 0x7C0),
484
485 INTC_VECT(DMAC0A_DEI0,0x800),
486 INTC_VECT(DMAC0A_DEI1,0x820),
487 INTC_VECT(DMAC0A_DEI2,0x840),
488 INTC_VECT(DMAC0A_DEI3,0x860),
489
490 INTC_VECT(VIO_CEUI,0x880),
491 INTC_VECT(VIO_BEUI,0x8A0),
492 INTC_VECT(VIO_VEU2HI,0x8C0),
493 INTC_VECT(VIO_VOUI,0x8E0),
494
495 INTC_VECT(SCIFA_SCIFA0,0x900),
496 INTC_VECT(VPU_VPUI,0x980),
497 INTC_VECT(TPU_TPUI,0x9A0),
498 INTC_VECT(ADC_ADI,0x9E0),
499 INTC_VECT(USB_USI0,0xA20),
500
501 INTC_VECT(RTC_ATI,0xA80),
502 INTC_VECT(RTC_PRI,0xAA0),
503 INTC_VECT(RTC_CUI,0xAC0),
504
505 INTC_VECT(DMAC1B_DEI4,0xB00),
506 INTC_VECT(DMAC1B_DEI5,0xB20),
507 INTC_VECT(DMAC1B_DADERR,0xB40),
508
509 INTC_VECT(DMAC0B_DEI4,0xB80),
510 INTC_VECT(DMAC0B_DEI5,0xBA0),
511 INTC_VECT(DMAC0B_DADERR,0xBC0),
512
513 INTC_VECT(KEYSC_KEYI,0xBE0),
514 INTC_VECT(SCIF_SCIF0,0xC00),
515 INTC_VECT(SCIF_SCIF1,0xC20),
516 INTC_VECT(SCIF_SCIF2,0xC40),
517 INTC_VECT(MSIOF_MSIOFI0,0xC80),
518 INTC_VECT(MSIOF_MSIOFI1,0xCA0),
519 INTC_VECT(SCIFA_SCIFA1,0xD00),
520
521 INTC_VECT(FLCTL_FLSTEI,0xD80),
522 INTC_VECT(FLCTL_FLTENDI,0xDA0),
523 INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
524 INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
525
526 INTC_VECT(I2C_ALI,0xE00),
527 INTC_VECT(I2C_TACKI,0xE20),
528 INTC_VECT(I2C_WAITI,0xE40),
529 INTC_VECT(I2C_DTEI,0xE60),
530
531 INTC_VECT(SDHI0, 0xE80),
532 INTC_VECT(SDHI0, 0xEA0),
533 INTC_VECT(SDHI0, 0xEC0),
534
535 INTC_VECT(CMT_CMTI,0xF00),
536 INTC_VECT(TSIF_TSIFI,0xF20),
537 INTC_VECT(SIU_SIUI,0xF80),
538 INTC_VECT(SCIFA_SCIFA2,0xFA0),
539
540 INTC_VECT(TMU0_TUNI0,0x400),
541 INTC_VECT(TMU0_TUNI1,0x420),
542 INTC_VECT(TMU0_TUNI2,0x440),
543
544 INTC_VECT(IRDA_IRDAI,0x480),
545 INTC_VECT(ATAPI_ATAPII,0x4A0),
546
547 INTC_VECT(SDHI1, 0x4E0),
548 INTC_VECT(SDHI1, 0x500),
549 INTC_VECT(SDHI1, 0x520),
550
551 INTC_VECT(VEU2H1_VEU2HI,0x560),
552 INTC_VECT(LCDC_LCDCI,0x580),
553
554 INTC_VECT(TMU1_TUNI0,0x920),
555 INTC_VECT(TMU1_TUNI1,0x940),
556 INTC_VECT(TMU1_TUNI2,0x960),
557
558};
559
560static struct intc_group groups[] __initdata = {
561 INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
562 INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
563 INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
564 INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
565 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
566 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
567 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
568 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
569 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
570};
571
572static struct intc_mask_reg mask_registers[] __initdata = {
573 { 0xa4080080, 0xa40800c0, 8,
574 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
575 0, ENABLED, ENABLED, ENABLED } },
576 { 0xa4080084, 0xa40800c4, 8,
577 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
578 { 0xa4080088, 0xa40800c8, 8,
579 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
580 { 0xa408008c, 0xa40800cc, 8,
581 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
582 { 0xa4080090, 0xa40800d0, 8,
583 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
584 { 0xa4080094, 0xa40800d4, 8,
585 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
586 { 0xa4080098, 0xa40800d8, 8,
587 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
588 { 0xa408009c, 0xa40800dc, 8,
589 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
590 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
591 { 0xa40800a0, 0xa40800e0, 8,
592 { 0, ENABLED, ENABLED, ENABLED,
593 0, 0, SCIFA_SCIFA2, SIU_SIUI } },
594 { 0xa40800a4, 0xa40800e4, 8,
595 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
596 { 0xa40800a8, 0xa40800e8, 8,
597 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
598 { 0xa40800ac, 0xa40800ec, 8,
599 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
600 { 0xa40800b0, 0xa40800f0, 8,
601 { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
602 { 0xa4140044, 0xa4140064, 8,
603 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
604};
605
606static struct intc_prio_reg prio_registers[] __initdata = {
607 { 0xa4080000, 0, 16, 4, { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
608 { 0xa4080004, 0, 16, 4, { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
609 { 0xa4080008, 0, 16, 4, { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
610 { 0xa408000c, 0, 16, 4, { } },
611 { 0xa4080010, 0, 16, 4, { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
612 { 0xa4080014, 0, 16, 4, { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
613 { 0xa4080018, 0, 16, 4, { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
614 { 0xa408001c, 0, 16, 4, { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
615 { 0xa4080020, 0, 16, 4, { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
616 { 0xa4080024, 0, 16, 4, { ADC_ADI,0,SIU_SIUI,SDHI1 } },
617 { 0xa4080028, 0, 16, 4, { RTC,DMAC1B,0,SDHI0 } },
618 { 0xa408002c, 0, 16, 4, { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
619 { 0xa4140010, 0, 32, 4,
620 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
621};
622
623static struct intc_sense_reg sense_registers[] __initdata = {
624 { 0xa414001c, 16, 2,
625 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
626};
627
628static struct intc_mask_reg ack_registers[] __initdata = {
629 { 0xa4140024, 0, 8,
630 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
631};
632
633static struct intc_desc intc_desc __initdata = {
634 .name = "sh7723",
635 .force_enable = ENABLED,
636 .force_disable = DISABLED,
637 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
638 prio_registers, sense_registers, ack_registers),
639};
640
641void __init plat_irq_setup(void)
642{
643 register_intc_controller(&intc_desc);
644}
645
