1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/dma-mapping.h>
26#include <linux/device.h>
27#include <linux/dmi.h>
28#include <linux/gfp.h>
29#include <linux/msi.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_cmnd.h>
32#include <linux/libata.h>
33#include <linux/ahci-remap.h>
34#include <linux/io-64-nonatomic-lo-hi.h>
35#include "ahci.h"
36
37#define DRV_NAME "ahci"
38#define DRV_VERSION "3.0"
39
40enum {
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_LOONGSON = 0,
44 AHCI_PCI_BAR_ENMOTUS = 2,
45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
46 AHCI_PCI_BAR_STANDARD = 5,
47};
48
49enum board_ids {
50
51 board_ahci,
52 board_ahci_ign_iferr,
53 board_ahci_low_power,
54 board_ahci_no_debounce_delay,
55 board_ahci_nomsi,
56 board_ahci_noncq,
57 board_ahci_nosntf,
58 board_ahci_yes_fbs,
59
60
61 board_ahci_al,
62 board_ahci_avn,
63 board_ahci_mcp65,
64 board_ahci_mcp77,
65 board_ahci_mcp89,
66 board_ahci_mv,
67 board_ahci_sb600,
68 board_ahci_sb700,
69 board_ahci_vt8251,
70
71
72
73
74
75 board_ahci_pcs7,
76
77
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
82};
83
84static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85static void ahci_remove_one(struct pci_dev *dev);
86static void ahci_shutdown_one(struct pci_dev *dev);
87static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
92static bool is_mcp89_apple(struct pci_dev *pdev);
93static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
94 unsigned long deadline);
95#ifdef CONFIG_PM
96static int ahci_pci_device_runtime_suspend(struct device *dev);
97static int ahci_pci_device_runtime_resume(struct device *dev);
98#ifdef CONFIG_PM_SLEEP
99static int ahci_pci_device_suspend(struct device *dev);
100static int ahci_pci_device_resume(struct device *dev);
101#endif
102#endif
103
104static struct scsi_host_template ahci_sht = {
105 AHCI_SHT("ahci"),
106};
107
108static struct ata_port_operations ahci_vt8251_ops = {
109 .inherits = &ahci_ops,
110 .hardreset = ahci_vt8251_hardreset,
111};
112
113static struct ata_port_operations ahci_p5wdh_ops = {
114 .inherits = &ahci_ops,
115 .hardreset = ahci_p5wdh_hardreset,
116};
117
118static struct ata_port_operations ahci_avn_ops = {
119 .inherits = &ahci_ops,
120 .hardreset = ahci_avn_hardreset,
121};
122
123static const struct ata_port_info ahci_port_info[] = {
124
125 [board_ahci] = {
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
131 [board_ahci_ign_iferr] = {
132 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
133 .flags = AHCI_FLAG_COMMON,
134 .pio_mask = ATA_PIO4,
135 .udma_mask = ATA_UDMA6,
136 .port_ops = &ahci_ops,
137 },
138 [board_ahci_low_power] = {
139 AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
145 [board_ahci_no_debounce_delay] = {
146 .flags = AHCI_FLAG_COMMON,
147 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
151 },
152 [board_ahci_nomsi] = {
153 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
158 },
159 [board_ahci_noncq] = {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_nosntf] = {
167 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
168 .flags = AHCI_FLAG_COMMON,
169 .pio_mask = ATA_PIO4,
170 .udma_mask = ATA_UDMA6,
171 .port_ops = &ahci_ops,
172 },
173 [board_ahci_yes_fbs] = {
174 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
175 .flags = AHCI_FLAG_COMMON,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
179 },
180
181 [board_ahci_al] = {
182 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
183 .flags = AHCI_FLAG_COMMON,
184 .pio_mask = ATA_PIO4,
185 .udma_mask = ATA_UDMA6,
186 .port_ops = &ahci_ops,
187 },
188 [board_ahci_avn] = {
189 .flags = AHCI_FLAG_COMMON,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_avn_ops,
193 },
194 [board_ahci_mcp65] = {
195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
196 AHCI_HFLAG_YES_NCQ),
197 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_ops,
201 },
202 [board_ahci_mcp77] = {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_ops,
208 },
209 [board_ahci_mcp89] = {
210 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
215 },
216 [board_ahci_mv] = {
217 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
218 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
219 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
222 .port_ops = &ahci_ops,
223 },
224 [board_ahci_sb600] = {
225 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
226 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
227 AHCI_HFLAG_32BIT_ONLY),
228 .flags = AHCI_FLAG_COMMON,
229 .pio_mask = ATA_PIO4,
230 .udma_mask = ATA_UDMA6,
231 .port_ops = &ahci_pmp_retry_srst_ops,
232 },
233 [board_ahci_sb700] = {
234 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
235 .flags = AHCI_FLAG_COMMON,
236 .pio_mask = ATA_PIO4,
237 .udma_mask = ATA_UDMA6,
238 .port_ops = &ahci_pmp_retry_srst_ops,
239 },
240 [board_ahci_vt8251] = {
241 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
242 .flags = AHCI_FLAG_COMMON,
243 .pio_mask = ATA_PIO4,
244 .udma_mask = ATA_UDMA6,
245 .port_ops = &ahci_vt8251_ops,
246 },
247 [board_ahci_pcs7] = {
248 .flags = AHCI_FLAG_COMMON,
249 .pio_mask = ATA_PIO4,
250 .udma_mask = ATA_UDMA6,
251 .port_ops = &ahci_ops,
252 },
253};
254
255static const struct pci_device_id ahci_pci_tbl[] = {
256
257 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci },
258 { PCI_VDEVICE(INTEL, 0x2652), board_ahci },
259 { PCI_VDEVICE(INTEL, 0x2653), board_ahci },
260 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci },
261 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci },
262 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci },
263 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr },
264 { PCI_VDEVICE(INTEL, 0x2681), board_ahci },
265 { PCI_VDEVICE(INTEL, 0x2682), board_ahci },
266 { PCI_VDEVICE(INTEL, 0x2683), board_ahci },
267 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci },
268 { PCI_VDEVICE(INTEL, 0x2821), board_ahci },
269 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf },
270 { PCI_VDEVICE(INTEL, 0x2824), board_ahci },
271 { PCI_VDEVICE(INTEL, 0x2829), board_ahci },
272 { PCI_VDEVICE(INTEL, 0x282a), board_ahci },
273 { PCI_VDEVICE(INTEL, 0x2922), board_ahci },
274 { PCI_VDEVICE(INTEL, 0x2923), board_ahci },
275 { PCI_VDEVICE(INTEL, 0x2924), board_ahci },
276 { PCI_VDEVICE(INTEL, 0x2925), board_ahci },
277 { PCI_VDEVICE(INTEL, 0x2927), board_ahci },
278 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power },
279 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power },
280 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power },
281 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power },
282 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power },
283 { PCI_VDEVICE(INTEL, 0x294d), board_ahci },
284 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power },
285 { PCI_VDEVICE(INTEL, 0x502a), board_ahci },
286 { PCI_VDEVICE(INTEL, 0x502b), board_ahci },
287 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci },
288 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci },
289 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci },
290 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci },
291 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci },
292 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci },
293 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci },
294 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power },
295 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci },
296 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power },
297 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci },
298 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 },
299 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 },
300 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 },
301 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 },
302 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 },
303 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 },
304 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 },
305 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 },
306 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 },
307 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 },
308 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 },
309 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 },
310 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 },
311 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 },
312 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 },
313 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 },
314 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 },
315 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 },
316 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 },
317 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 },
318 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci },
319 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power },
320 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci },
321 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power },
322 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci },
323 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci },
324 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci },
325 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci },
326 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci },
327 { PCI_VDEVICE(INTEL, 0x2826), board_ahci },
328 { PCI_VDEVICE(INTEL, 0x2323), board_ahci },
329 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci },
330 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power },
331 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci },
332 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci },
333 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci },
334 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power },
335 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci },
336 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci },
337 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power },
338 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci },
339 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power },
340 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci },
341 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power },
342 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci },
343 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power },
344 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power },
345 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power },
346 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power },
347 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power },
348 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power },
349 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power },
350 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power },
351 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power },
352 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power },
353 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci },
354 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci },
355 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci },
356 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci },
357 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci },
358 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci },
359 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci },
360 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci },
361 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn },
362 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn },
363 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn },
364 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn },
365 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn },
366 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn },
367 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn },
368 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn },
369 { PCI_VDEVICE(INTEL, 0x2823), board_ahci },
370 { PCI_VDEVICE(INTEL, 0x2827), board_ahci },
371 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci },
372 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci },
373 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci },
374 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci },
375 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci },
376 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci },
377 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci },
378 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci },
379 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci },
380 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci },
381 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci },
382 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci },
383 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci },
384 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power },
385 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power },
386 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power },
387 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power },
388 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci },
389 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power },
390 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci },
391 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power },
392 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci },
393 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power },
394 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci },
395 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power },
396 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power },
397 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power },
398 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power },
399 { PCI_VDEVICE(INTEL, 0xa102), board_ahci },
400 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power },
401 { PCI_VDEVICE(INTEL, 0xa105), board_ahci },
402 { PCI_VDEVICE(INTEL, 0xa106), board_ahci },
403 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power },
404 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci },
405 { PCI_VDEVICE(INTEL, 0xa182), board_ahci },
406 { PCI_VDEVICE(INTEL, 0xa186), board_ahci },
407 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci },
408 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci },
409 { PCI_VDEVICE(INTEL, 0xa202), board_ahci },
410 { PCI_VDEVICE(INTEL, 0xa206), board_ahci },
411 { PCI_VDEVICE(INTEL, 0xa252), board_ahci },
412 { PCI_VDEVICE(INTEL, 0xa256), board_ahci },
413 { PCI_VDEVICE(INTEL, 0xa356), board_ahci },
414 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci },
415 { PCI_VDEVICE(INTEL, 0xa386), board_ahci },
416 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power },
417 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power },
418 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power },
419 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power },
420 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power },
421 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power },
422 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power },
423
424
425 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
426 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
427
428 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
429 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
430
431
432
433 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 },
434 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 },
435 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 },
436 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 },
437 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 },
438 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 },
439 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 },
440
441
442 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
443 .class = PCI_CLASS_STORAGE_SATA_AHCI,
444 .class_mask = 0xffffff,
445 board_ahci_al },
446
447 { PCI_VDEVICE(AMD, 0x7800), board_ahci },
448 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay },
449 { PCI_VDEVICE(AMD, 0x7900), board_ahci },
450 { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power },
451
452 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
453 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
454
455
456 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
457 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
458
459
460 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 },
461 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 },
462
463
464 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },
465 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },
466 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },
467 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },
468 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },
469 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },
470 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },
471 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },
472 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },
473 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },
474 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },
475 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },
476 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },
477 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },
478 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },
479 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },
480 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },
481 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },
482 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },
483 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },
484 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },
485 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },
486 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },
487 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },
488 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },
489 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },
490 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },
491 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },
492 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },
493 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },
494 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },
495 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },
496 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },
497 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },
498 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },
499 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },
500 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },
501 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },
502 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },
503 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },
504 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },
505 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },
506 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },
507 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },
508 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },
509 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },
510 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },
511 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },
512 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },
513 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },
514 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },
515 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },
516 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },
517 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },
518 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },
519 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },
520 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },
521 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },
522 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },
523 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },
524 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },
525 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },
526 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },
527 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },
528 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },
529 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },
530 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },
531 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },
532 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },
533 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },
534 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },
535 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },
536 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },
537 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },
538 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },
539 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },
540 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },
541 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },
542 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },
543 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },
544 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },
545 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },
546 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },
547 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },
548
549
550 { PCI_VDEVICE(SI, 0x1184), board_ahci },
551 { PCI_VDEVICE(SI, 0x1185), board_ahci },
552 { PCI_VDEVICE(SI, 0x0186), board_ahci },
553
554
555 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },
556
557
558 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },
559 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },
560 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
561 .class = PCI_CLASS_STORAGE_SATA_AHCI,
562 .class_mask = 0xffffff,
563 .driver_data = board_ahci_yes_fbs },
564 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
565 .driver_data = board_ahci_yes_fbs },
566 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
567 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
568 .driver_data = board_ahci_yes_fbs },
569 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
570 .driver_data = board_ahci_yes_fbs },
571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
572 .driver_data = board_ahci_yes_fbs },
573 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
574 .driver_data = board_ahci_yes_fbs },
575 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
576 .driver_data = board_ahci_yes_fbs },
577 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
578 .driver_data = board_ahci_yes_fbs },
579 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2),
580 .driver_data = board_ahci_yes_fbs },
581 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
582 .driver_data = board_ahci_yes_fbs },
583 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
584 .driver_data = board_ahci_yes_fbs },
585 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
586 .driver_data = board_ahci_no_debounce_delay },
587 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
588 .driver_data = board_ahci_yes_fbs },
589 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645),
590 .driver_data = board_ahci_yes_fbs },
591
592
593 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },
594 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci },
595
596
597 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },
598 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },
599 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },
600 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },
601 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci },
602 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci },
603 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci },
604
605
606
607
608
609 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
610 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
611
612
613 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
614
615
616 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
617
618
619 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
620 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
621
622 { }
623};
624
625static const struct dev_pm_ops ahci_pci_pm_ops = {
626 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
627 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
628 ahci_pci_device_runtime_resume, NULL)
629};
630
631static struct pci_driver ahci_pci_driver = {
632 .name = DRV_NAME,
633 .id_table = ahci_pci_tbl,
634 .probe = ahci_init_one,
635 .remove = ahci_remove_one,
636 .shutdown = ahci_shutdown_one,
637 .driver = {
638 .pm = &ahci_pci_pm_ops,
639 },
640};
641
642#if IS_ENABLED(CONFIG_PATA_MARVELL)
643static int marvell_enable;
644#else
645static int marvell_enable = 1;
646#endif
647module_param(marvell_enable, int, 0644);
648MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
649
650static int mobile_lpm_policy = -1;
651module_param(mobile_lpm_policy, int, 0644);
652MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
653
654static void ahci_pci_save_initial_config(struct pci_dev *pdev,
655 struct ahci_host_priv *hpriv)
656{
657 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
658 dev_info(&pdev->dev, "JMB361 has only one port\n");
659 hpriv->force_port_map = 1;
660 }
661
662
663
664
665
666
667 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
668 if (pdev->device == 0x6121)
669 hpriv->mask_port_map = 0x3;
670 else
671 hpriv->mask_port_map = 0xf;
672 dev_info(&pdev->dev,
673 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
674 }
675
676 ahci_save_initial_config(&pdev->dev, hpriv);
677}
678
679static void ahci_pci_init_controller(struct ata_host *host)
680{
681 struct ahci_host_priv *hpriv = host->private_data;
682 struct pci_dev *pdev = to_pci_dev(host->dev);
683 void __iomem *port_mmio;
684 u32 tmp;
685 int mv;
686
687 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
688 if (pdev->device == 0x6121)
689 mv = 2;
690 else
691 mv = 4;
692 port_mmio = __ahci_port_base(host, mv);
693
694 writel(0, port_mmio + PORT_IRQ_MASK);
695
696
697 tmp = readl(port_mmio + PORT_IRQ_STAT);
698 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
699 if (tmp)
700 writel(tmp, port_mmio + PORT_IRQ_STAT);
701 }
702
703 ahci_init_controller(host);
704}
705
706static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
707 unsigned long deadline)
708{
709 struct ata_port *ap = link->ap;
710 struct ahci_host_priv *hpriv = ap->host->private_data;
711 bool online;
712 int rc;
713
714 hpriv->stop_engine(ap);
715
716 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
717 deadline, &online, NULL);
718
719 hpriv->start_engine(ap);
720
721
722
723
724 return online ? -EAGAIN : rc;
725}
726
727static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
728 unsigned long deadline)
729{
730 struct ata_port *ap = link->ap;
731 struct ahci_port_priv *pp = ap->private_data;
732 struct ahci_host_priv *hpriv = ap->host->private_data;
733 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
734 struct ata_taskfile tf;
735 bool online;
736 int rc;
737
738 hpriv->stop_engine(ap);
739
740
741 ata_tf_init(link->device, &tf);
742 tf.status = ATA_BUSY;
743 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
744
745 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
746 deadline, &online, NULL);
747
748 hpriv->start_engine(ap);
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763 if (online) {
764 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
765 ahci_check_ready);
766 if (rc)
767 ahci_kick_engine(ap);
768 }
769 return rc;
770}
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
788 unsigned long deadline)
789{
790 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
791 struct ata_port *ap = link->ap;
792 struct ahci_port_priv *pp = ap->private_data;
793 struct ahci_host_priv *hpriv = ap->host->private_data;
794 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
795 unsigned long tmo = deadline - jiffies;
796 struct ata_taskfile tf;
797 bool online;
798 int rc, i;
799
800 hpriv->stop_engine(ap);
801
802 for (i = 0; i < 2; i++) {
803 u16 val;
804 u32 sstatus;
805 int port = ap->port_no;
806 struct ata_host *host = ap->host;
807 struct pci_dev *pdev = to_pci_dev(host->dev);
808
809
810 ata_tf_init(link->device, &tf);
811 tf.status = ATA_BUSY;
812 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
813
814 rc = sata_link_hardreset(link, timing, deadline, &online,
815 ahci_check_ready);
816
817 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
818 (sstatus & 0xf) != 1)
819 break;
820
821 ata_link_info(link, "avn bounce port%d\n", port);
822
823 pci_read_config_word(pdev, 0x92, &val);
824 val &= ~(1 << port);
825 pci_write_config_word(pdev, 0x92, val);
826 ata_msleep(ap, 1000);
827 val |= 1 << port;
828 pci_write_config_word(pdev, 0x92, val);
829 deadline += tmo;
830 }
831
832 hpriv->start_engine(ap);
833
834 if (online)
835 *class = ahci_dev_classify(ap);
836
837 return rc;
838}
839
840
841#ifdef CONFIG_PM
842static void ahci_pci_disable_interrupts(struct ata_host *host)
843{
844 struct ahci_host_priv *hpriv = host->private_data;
845 void __iomem *mmio = hpriv->mmio;
846 u32 ctl;
847
848
849
850
851
852 ctl = readl(mmio + HOST_CTL);
853 ctl &= ~HOST_IRQ_EN;
854 writel(ctl, mmio + HOST_CTL);
855 readl(mmio + HOST_CTL);
856}
857
858static int ahci_pci_device_runtime_suspend(struct device *dev)
859{
860 struct pci_dev *pdev = to_pci_dev(dev);
861 struct ata_host *host = pci_get_drvdata(pdev);
862
863 ahci_pci_disable_interrupts(host);
864 return 0;
865}
866
867static int ahci_pci_device_runtime_resume(struct device *dev)
868{
869 struct pci_dev *pdev = to_pci_dev(dev);
870 struct ata_host *host = pci_get_drvdata(pdev);
871 int rc;
872
873 rc = ahci_reset_controller(host);
874 if (rc)
875 return rc;
876 ahci_pci_init_controller(host);
877 return 0;
878}
879
880#ifdef CONFIG_PM_SLEEP
881static int ahci_pci_device_suspend(struct device *dev)
882{
883 struct pci_dev *pdev = to_pci_dev(dev);
884 struct ata_host *host = pci_get_drvdata(pdev);
885 struct ahci_host_priv *hpriv = host->private_data;
886
887 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
888 dev_err(&pdev->dev,
889 "BIOS update required for suspend/resume\n");
890 return -EIO;
891 }
892
893 ahci_pci_disable_interrupts(host);
894 ata_host_suspend(host, PMSG_SUSPEND);
895 return 0;
896}
897
898static int ahci_pci_device_resume(struct device *dev)
899{
900 struct pci_dev *pdev = to_pci_dev(dev);
901 struct ata_host *host = pci_get_drvdata(pdev);
902 int rc;
903
904
905 if (is_mcp89_apple(pdev))
906 ahci_mcp89_apple_enable(pdev);
907
908 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
909 rc = ahci_reset_controller(host);
910 if (rc)
911 return rc;
912
913 ahci_pci_init_controller(host);
914 }
915
916 ata_host_resume(host);
917
918 return 0;
919}
920#endif
921
922#endif
923
924static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
925{
926 const int dma_bits = using_dac ? 64 : 32;
927 int rc;
928
929
930
931
932
933
934
935
936 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
937 return 0;
938
939 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
940 if (rc)
941 dev_err(&pdev->dev, "DMA enable failed\n");
942 return rc;
943}
944
945static void ahci_pci_print_info(struct ata_host *host)
946{
947 struct pci_dev *pdev = to_pci_dev(host->dev);
948 u16 cc;
949 const char *scc_s;
950
951 pci_read_config_word(pdev, 0x0a, &cc);
952 if (cc == PCI_CLASS_STORAGE_IDE)
953 scc_s = "IDE";
954 else if (cc == PCI_CLASS_STORAGE_SATA)
955 scc_s = "SATA";
956 else if (cc == PCI_CLASS_STORAGE_RAID)
957 scc_s = "RAID";
958 else
959 scc_s = "unknown";
960
961 ahci_print_info(host, scc_s);
962}
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982static void ahci_p5wdh_workaround(struct ata_host *host)
983{
984 static const struct dmi_system_id sysids[] = {
985 {
986 .ident = "P5W DH Deluxe",
987 .matches = {
988 DMI_MATCH(DMI_SYS_VENDOR,
989 "ASUSTEK COMPUTER INC"),
990 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
991 },
992 },
993 { }
994 };
995 struct pci_dev *pdev = to_pci_dev(host->dev);
996
997 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
998 dmi_check_system(sysids)) {
999 struct ata_port *ap = host->ports[1];
1000
1001 dev_info(&pdev->dev,
1002 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1003
1004 ap->ops = &ahci_p5wdh_ops;
1005 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1006 }
1007}
1008
1009
1010
1011
1012
1013static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1014{
1015 u32 val;
1016
1017 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1018
1019 pci_read_config_dword(pdev, 0xf8, &val);
1020 val |= 1 << 0x1b;
1021
1022
1023 pci_write_config_dword(pdev, 0xf8, val);
1024
1025 pci_read_config_dword(pdev, 0x54c, &val);
1026 val |= 1 << 0xc;
1027 pci_write_config_dword(pdev, 0x54c, val);
1028
1029 pci_read_config_dword(pdev, 0x4a4, &val);
1030 val &= 0xff;
1031 val |= 0x01060100;
1032 pci_write_config_dword(pdev, 0x4a4, val);
1033
1034 pci_read_config_dword(pdev, 0x54c, &val);
1035 val &= ~(1 << 0xc);
1036 pci_write_config_dword(pdev, 0x54c, val);
1037
1038 pci_read_config_dword(pdev, 0xf8, &val);
1039 val &= ~(1 << 0x1b);
1040 pci_write_config_dword(pdev, 0xf8, val);
1041}
1042
1043static bool is_mcp89_apple(struct pci_dev *pdev)
1044{
1045 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1046 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1047 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1048 pdev->subsystem_device == 0xcb89;
1049}
1050
1051
1052static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1053{
1054 static const struct dmi_system_id sysids[] = {
1055
1056
1057
1058
1059
1060
1061
1062 {
1063 .ident = "ASUS M2A-VM",
1064 .matches = {
1065 DMI_MATCH(DMI_BOARD_VENDOR,
1066 "ASUSTeK Computer INC."),
1067 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1068 },
1069 .driver_data = "20071026",
1070 },
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087 {
1088 .ident = "MSI K9A2 Platinum",
1089 .matches = {
1090 DMI_MATCH(DMI_BOARD_VENDOR,
1091 "MICRO-STAR INTER"),
1092 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1093 },
1094 },
1095
1096
1097
1098
1099
1100
1101
1102
1103 {
1104 .ident = "MSI K9AGM2",
1105 .matches = {
1106 DMI_MATCH(DMI_BOARD_VENDOR,
1107 "MICRO-STAR INTER"),
1108 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1109 },
1110 },
1111
1112
1113
1114
1115 {
1116 .ident = "ASUS M3A",
1117 .matches = {
1118 DMI_MATCH(DMI_BOARD_VENDOR,
1119 "ASUSTeK Computer INC."),
1120 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1121 },
1122 },
1123 { }
1124 };
1125 const struct dmi_system_id *match;
1126 int year, month, date;
1127 char buf[9];
1128
1129 match = dmi_first_match(sysids);
1130 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1131 !match)
1132 return false;
1133
1134 if (!match->driver_data)
1135 goto enable_64bit;
1136
1137 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1138 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1139
1140 if (strcmp(buf, match->driver_data) >= 0)
1141 goto enable_64bit;
1142 else {
1143 dev_warn(&pdev->dev,
1144 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1145 match->ident);
1146 return false;
1147 }
1148
1149enable_64bit:
1150 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1151 return true;
1152}
1153
1154static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1155{
1156 static const struct dmi_system_id broken_systems[] = {
1157 {
1158 .ident = "HP Compaq nx6310",
1159 .matches = {
1160 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1161 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1162 },
1163
1164 .driver_data = (void *)0x1FUL,
1165 },
1166 {
1167 .ident = "HP Compaq 6720s",
1168 .matches = {
1169 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1170 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1171 },
1172
1173 .driver_data = (void *)0x1FUL,
1174 },
1175
1176 { }
1177 };
1178 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1179
1180 if (dmi) {
1181 unsigned long slot = (unsigned long)dmi->driver_data;
1182
1183 return slot == PCI_SLOT(pdev->devfn);
1184 }
1185
1186 return false;
1187}
1188
1189static bool ahci_broken_suspend(struct pci_dev *pdev)
1190{
1191 static const struct dmi_system_id sysids[] = {
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205 {
1206 .ident = "dv4",
1207 .matches = {
1208 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1209 DMI_MATCH(DMI_PRODUCT_NAME,
1210 "HP Pavilion dv4 Notebook PC"),
1211 },
1212 .driver_data = "20090105",
1213 },
1214 {
1215 .ident = "dv5",
1216 .matches = {
1217 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1218 DMI_MATCH(DMI_PRODUCT_NAME,
1219 "HP Pavilion dv5 Notebook PC"),
1220 },
1221 .driver_data = "20090506",
1222 },
1223 {
1224 .ident = "dv6",
1225 .matches = {
1226 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1227 DMI_MATCH(DMI_PRODUCT_NAME,
1228 "HP Pavilion dv6 Notebook PC"),
1229 },
1230 .driver_data = "20090423",
1231 },
1232 {
1233 .ident = "HDX18",
1234 .matches = {
1235 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1236 DMI_MATCH(DMI_PRODUCT_NAME,
1237 "HP HDX18 Notebook PC"),
1238 },
1239 .driver_data = "20090430",
1240 },
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250 {
1251 .ident = "G725",
1252 .matches = {
1253 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1254 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1255 },
1256 .driver_data = "20091216",
1257 },
1258 { }
1259 };
1260 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1261 int year, month, date;
1262 char buf[9];
1263
1264 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1265 return false;
1266
1267 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1268 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1269
1270 return strcmp(buf, dmi->driver_data) < 0;
1271}
1272
1273static bool ahci_broken_lpm(struct pci_dev *pdev)
1274{
1275 static const struct dmi_system_id sysids[] = {
1276
1277 {
1278 .matches = {
1279 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1280 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1281 },
1282 .driver_data = "20180406",
1283 },
1284 {
1285 .matches = {
1286 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1287 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1288 },
1289 .driver_data = "20180420",
1290 },
1291 {
1292 .matches = {
1293 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1294 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1295 },
1296 .driver_data = "20180315",
1297 },
1298 {
1299 .matches = {
1300 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1301 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1302 },
1303
1304
1305
1306
1307
1308
1309 .driver_data = "20180310",
1310 },
1311 { }
1312 };
1313 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1314 int year, month, date;
1315 char buf[9];
1316
1317 if (!dmi)
1318 return false;
1319
1320 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1321 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1322
1323 return strcmp(buf, dmi->driver_data) < 0;
1324}
1325
1326static bool ahci_broken_online(struct pci_dev *pdev)
1327{
1328#define ENCODE_BUSDEVFN(bus, slot, func) \
1329 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1330 static const struct dmi_system_id sysids[] = {
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344 {
1345 .ident = "EP45-DQ6",
1346 .matches = {
1347 DMI_MATCH(DMI_BOARD_VENDOR,
1348 "Gigabyte Technology Co., Ltd."),
1349 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1350 },
1351 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1352 },
1353 {
1354 .ident = "EP45-DS5",
1355 .matches = {
1356 DMI_MATCH(DMI_BOARD_VENDOR,
1357 "Gigabyte Technology Co., Ltd."),
1358 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1359 },
1360 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1361 },
1362 { }
1363 };
1364#undef ENCODE_BUSDEVFN
1365 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1366 unsigned int val;
1367
1368 if (!dmi)
1369 return false;
1370
1371 val = (unsigned long)dmi->driver_data;
1372
1373 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1374}
1375
1376static bool ahci_broken_devslp(struct pci_dev *pdev)
1377{
1378
1379 static const struct pci_device_id ids[] = {
1380 { PCI_VDEVICE(INTEL, 0x0f23)},
1381 {}
1382 };
1383
1384 return pci_match_id(ids, pdev);
1385}
1386
1387#ifdef CONFIG_ATA_ACPI
1388static void ahci_gtf_filter_workaround(struct ata_host *host)
1389{
1390 static const struct dmi_system_id sysids[] = {
1391
1392
1393
1394
1395
1396
1397
1398
1399 {
1400 .ident = "Aspire 3810T",
1401 .matches = {
1402 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1403 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1404 },
1405 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1406 },
1407 { }
1408 };
1409 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1410 unsigned int filter;
1411 int i;
1412
1413 if (!dmi)
1414 return;
1415
1416 filter = (unsigned long)dmi->driver_data;
1417 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1418 filter, dmi->ident);
1419
1420 for (i = 0; i < host->n_ports; i++) {
1421 struct ata_port *ap = host->ports[i];
1422 struct ata_link *link;
1423 struct ata_device *dev;
1424
1425 ata_for_each_link(link, ap, EDGE)
1426 ata_for_each_dev(dev, link, ALL)
1427 dev->gtf_filter |= filter;
1428 }
1429}
1430#else
1431static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1432{}
1433#endif
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1447 struct pci_dev *pdev)
1448{
1449 static const struct dmi_system_id sysids[] = {
1450 {
1451 .ident = "Acer Switch Alpha 12",
1452 .matches = {
1453 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1454 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1455 },
1456 },
1457 { }
1458 };
1459
1460 if (dmi_check_system(sysids)) {
1461 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1462 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1463 hpriv->port_map = 0x7;
1464 hpriv->cap = 0xC734FF02;
1465 }
1466 }
1467}
1468
1469#ifdef CONFIG_ARM64
1470
1471
1472
1473
1474
1475static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1476{
1477 struct ata_host *host = dev_instance;
1478 struct ahci_host_priv *hpriv;
1479 unsigned int rc = 0;
1480 void __iomem *mmio;
1481 u32 irq_stat, irq_masked;
1482 unsigned int handled = 1;
1483
1484 hpriv = host->private_data;
1485 mmio = hpriv->mmio;
1486 irq_stat = readl(mmio + HOST_IRQ_STAT);
1487 if (!irq_stat)
1488 return IRQ_NONE;
1489
1490 do {
1491 irq_masked = irq_stat & hpriv->port_map;
1492 spin_lock(&host->lock);
1493 rc = ahci_handle_port_intr(host, irq_masked);
1494 if (!rc)
1495 handled = 0;
1496 writel(irq_stat, mmio + HOST_IRQ_STAT);
1497 irq_stat = readl(mmio + HOST_IRQ_STAT);
1498 spin_unlock(&host->lock);
1499 } while (irq_stat);
1500
1501 return IRQ_RETVAL(handled);
1502}
1503#endif
1504
1505static void ahci_remap_check(struct pci_dev *pdev, int bar,
1506 struct ahci_host_priv *hpriv)
1507{
1508 int i;
1509 u32 cap;
1510
1511
1512
1513
1514 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1515 pci_resource_len(pdev, bar) < SZ_512K ||
1516 bar != AHCI_PCI_BAR_STANDARD ||
1517 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1518 return;
1519
1520 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1521 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1522 if ((cap & (1 << i)) == 0)
1523 continue;
1524 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1525 != PCI_CLASS_STORAGE_EXPRESS)
1526 continue;
1527
1528
1529 hpriv->remapped_nvme++;
1530 }
1531
1532 if (!hpriv->remapped_nvme)
1533 return;
1534
1535 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1536 hpriv->remapped_nvme);
1537 dev_warn(&pdev->dev,
1538 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1539
1540
1541
1542
1543
1544 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1545}
1546
1547static int ahci_get_irq_vector(struct ata_host *host, int port)
1548{
1549 return pci_irq_vector(to_pci_dev(host->dev), port);
1550}
1551
1552static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1553 struct ahci_host_priv *hpriv)
1554{
1555 int nvec;
1556
1557 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1558 return -ENODEV;
1559
1560
1561
1562
1563
1564
1565 if (n_ports > 1) {
1566 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1567 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1568 if (nvec > 0) {
1569 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1570 hpriv->get_irq_vector = ahci_get_irq_vector;
1571 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1572 return nvec;
1573 }
1574
1575
1576
1577
1578
1579 printk(KERN_INFO
1580 "ahci: MRSM is on, fallback to single MSI\n");
1581 pci_free_irq_vectors(pdev);
1582 }
1583 }
1584
1585
1586
1587
1588
1589 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1590 if (nvec == 1)
1591 return nvec;
1592 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1593}
1594
1595static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1596 struct ahci_host_priv *hpriv)
1597{
1598 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1599
1600
1601
1602 if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY))
1603 return;
1604
1605
1606 if (mobile_lpm_policy != -1) {
1607 policy = mobile_lpm_policy;
1608 goto update_policy;
1609 }
1610
1611#ifdef CONFIG_ACPI
1612 if (policy > ATA_LPM_MED_POWER &&
1613 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1614 if (hpriv->cap & HOST_CAP_PART)
1615 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1616 else if (hpriv->cap & HOST_CAP_SSC)
1617 policy = ATA_LPM_MIN_POWER;
1618 }
1619#endif
1620
1621update_policy:
1622 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1623 ap->target_lpm_policy = policy;
1624}
1625
1626static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1627{
1628 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1629 u16 tmp16;
1630
1631
1632
1633
1634 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1635 return;
1636
1637
1638 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1639 return;
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649 pci_read_config_word(pdev, PCS_6, &tmp16);
1650 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1651 tmp16 |= hpriv->port_map;
1652 pci_write_config_word(pdev, PCS_6, tmp16);
1653 }
1654}
1655
1656static ssize_t remapped_nvme_show(struct device *dev,
1657 struct device_attribute *attr,
1658 char *buf)
1659{
1660 struct ata_host *host = dev_get_drvdata(dev);
1661 struct ahci_host_priv *hpriv = host->private_data;
1662
1663 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
1664}
1665
1666static DEVICE_ATTR_RO(remapped_nvme);
1667
1668static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1669{
1670 unsigned int board_id = ent->driver_data;
1671 struct ata_port_info pi = ahci_port_info[board_id];
1672 const struct ata_port_info *ppi[] = { &pi, NULL };
1673 struct device *dev = &pdev->dev;
1674 struct ahci_host_priv *hpriv;
1675 struct ata_host *host;
1676 int n_ports, i, rc;
1677 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1678
1679 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1680
1681 ata_print_version_once(&pdev->dev, DRV_VERSION);
1682
1683
1684
1685
1686 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1687 return -ENODEV;
1688
1689
1690 if (is_mcp89_apple(pdev))
1691 ahci_mcp89_apple_enable(pdev);
1692
1693
1694
1695
1696
1697 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1698 dev_info(&pdev->dev,
1699 "PDC42819 can only drive SATA devices with this driver\n");
1700
1701
1702 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1703 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1704 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1705 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1706 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1707 if (pdev->device == 0xa01c)
1708 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1709 if (pdev->device == 0xa084)
1710 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1711 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1712 if (pdev->device == 0x7a08)
1713 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1714 }
1715
1716
1717 rc = pcim_enable_device(pdev);
1718 if (rc)
1719 return rc;
1720
1721 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1722 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1723 u8 map;
1724
1725
1726
1727
1728
1729 pci_read_config_byte(pdev, ICH_MAP, &map);
1730 if (map & 0x3) {
1731 dev_info(&pdev->dev,
1732 "controller is in combined mode, can't enable AHCI mode\n");
1733 return -ENODEV;
1734 }
1735 }
1736
1737
1738
1739
1740 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1741 if (rc == -EBUSY)
1742 pcim_pin_device(pdev);
1743 if (rc)
1744 return rc;
1745
1746 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1747 if (!hpriv)
1748 return -ENOMEM;
1749 hpriv->flags |= (unsigned long)pi.private_data;
1750
1751
1752 if (board_id == board_ahci_mcp65 &&
1753 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1754 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1755
1756
1757 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1758 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1759
1760
1761 if (ahci_sb600_enable_64bit(pdev))
1762 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1763
1764 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1765
1766
1767 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1768
1769 sysfs_add_file_to_group(&pdev->dev.kobj,
1770 &dev_attr_remapped_nvme.attr,
1771 NULL);
1772
1773
1774 if (ahci_broken_devslp(pdev))
1775 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1776
1777#ifdef CONFIG_ARM64
1778 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1779 pdev->device == 0xa235 &&
1780 pdev->revision < 0x30)
1781 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1782
1783 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1784 hpriv->irq_handler = ahci_thunderx_irq_handler;
1785#endif
1786
1787
1788 ahci_pci_save_initial_config(pdev, hpriv);
1789
1790
1791
1792
1793
1794 ahci_intel_pcs_quirk(pdev, hpriv);
1795
1796
1797 if (hpriv->cap & HOST_CAP_NCQ) {
1798 pi.flags |= ATA_FLAG_NCQ;
1799
1800
1801
1802
1803
1804
1805 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1806 pi.flags |= ATA_FLAG_FPDMA_AA;
1807
1808
1809
1810
1811
1812
1813
1814 pi.flags |= ATA_FLAG_FPDMA_AUX;
1815 }
1816
1817 if (hpriv->cap & HOST_CAP_PMP)
1818 pi.flags |= ATA_FLAG_PMP;
1819
1820 ahci_set_em_messages(hpriv, &pi);
1821
1822 if (ahci_broken_system_poweroff(pdev)) {
1823 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1824 dev_info(&pdev->dev,
1825 "quirky BIOS, skipping spindown on poweroff\n");
1826 }
1827
1828 if (ahci_broken_lpm(pdev)) {
1829 pi.flags |= ATA_FLAG_NO_LPM;
1830 dev_warn(&pdev->dev,
1831 "BIOS update required for Link Power Management support\n");
1832 }
1833
1834 if (ahci_broken_suspend(pdev)) {
1835 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1836 dev_warn(&pdev->dev,
1837 "BIOS update required for suspend/resume\n");
1838 }
1839
1840 if (ahci_broken_online(pdev)) {
1841 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1842 dev_info(&pdev->dev,
1843 "online status unreliable, applying workaround\n");
1844 }
1845
1846
1847
1848 acer_sa5_271_workaround(hpriv, pdev);
1849
1850
1851
1852
1853
1854
1855 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1856
1857 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1858 if (!host)
1859 return -ENOMEM;
1860 host->private_data = hpriv;
1861
1862 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1863
1864 pci_intx(pdev, 1);
1865 }
1866 hpriv->irq = pci_irq_vector(pdev, 0);
1867
1868 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1869 host->flags |= ATA_HOST_PARALLEL_SCAN;
1870 else
1871 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1872
1873 if (pi.flags & ATA_FLAG_EM)
1874 ahci_reset_em(host);
1875
1876 for (i = 0; i < host->n_ports; i++) {
1877 struct ata_port *ap = host->ports[i];
1878
1879 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1880 ata_port_pbar_desc(ap, ahci_pci_bar,
1881 0x100 + ap->port_no * 0x80, "port");
1882
1883
1884 if (ap->flags & ATA_FLAG_EM)
1885 ap->em_message_type = hpriv->em_msg_type;
1886
1887 ahci_update_initial_lpm_policy(ap, hpriv);
1888
1889
1890 if (!(hpriv->port_map & (1 << i)))
1891 ap->ops = &ata_dummy_port_ops;
1892 }
1893
1894
1895 ahci_p5wdh_workaround(host);
1896
1897
1898 ahci_gtf_filter_workaround(host);
1899
1900
1901 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1902 if (rc)
1903 return rc;
1904
1905 rc = ahci_reset_controller(host);
1906 if (rc)
1907 return rc;
1908
1909 ahci_pci_init_controller(host);
1910 ahci_pci_print_info(host);
1911
1912 pci_set_master(pdev);
1913
1914 rc = ahci_host_activate(host, &ahci_sht);
1915 if (rc)
1916 return rc;
1917
1918 pm_runtime_put_noidle(&pdev->dev);
1919 return 0;
1920}
1921
1922static void ahci_shutdown_one(struct pci_dev *pdev)
1923{
1924 ata_pci_shutdown_one(pdev);
1925}
1926
1927static void ahci_remove_one(struct pci_dev *pdev)
1928{
1929 sysfs_remove_file_from_group(&pdev->dev.kobj,
1930 &dev_attr_remapped_nvme.attr,
1931 NULL);
1932 pm_runtime_get_noresume(&pdev->dev);
1933 ata_pci_remove_one(pdev);
1934}
1935
1936module_pci_driver(ahci_pci_driver);
1937
1938MODULE_AUTHOR("Jeff Garzik");
1939MODULE_DESCRIPTION("AHCI SATA low-level driver");
1940MODULE_LICENSE("GPL");
1941MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1942MODULE_VERSION(DRV_VERSION);
1943