1
2
3
4
5
6
7
8
9
10
11
12
13
14#include "tpm.h"
15#include <crypto/hash_info.h>
16
17static struct tpm2_hash tpm2_hash_map[] = {
18 {HASH_ALGO_SHA1, TPM_ALG_SHA1},
19 {HASH_ALGO_SHA256, TPM_ALG_SHA256},
20 {HASH_ALGO_SHA384, TPM_ALG_SHA384},
21 {HASH_ALGO_SHA512, TPM_ALG_SHA512},
22 {HASH_ALGO_SM3_256, TPM_ALG_SM3_256},
23};
24
25int tpm2_get_timeouts(struct tpm_chip *chip)
26{
27
28 chip->timeout_a = msecs_to_jiffies(TPM2_TIMEOUT_A);
29 chip->timeout_b = msecs_to_jiffies(TPM2_TIMEOUT_B);
30 chip->timeout_c = msecs_to_jiffies(TPM2_TIMEOUT_C);
31 chip->timeout_d = msecs_to_jiffies(TPM2_TIMEOUT_D);
32
33
34 chip->duration[TPM_SHORT] = msecs_to_jiffies(TPM2_DURATION_SHORT);
35 chip->duration[TPM_MEDIUM] = msecs_to_jiffies(TPM2_DURATION_MEDIUM);
36 chip->duration[TPM_LONG] = msecs_to_jiffies(TPM2_DURATION_LONG);
37
38
39 chip->duration[TPM_LONG_LONG] =
40 msecs_to_jiffies(TPM2_DURATION_LONG_LONG);
41
42 chip->flags |= TPM_CHIP_FLAG_HAVE_TIMEOUTS;
43
44 return 0;
45}
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67static u8 tpm2_ordinal_duration_index(u32 ordinal)
68{
69 switch (ordinal) {
70
71 case TPM2_CC_STARTUP:
72 return TPM_MEDIUM;
73
74 case TPM2_CC_SELF_TEST:
75 return TPM_LONG;
76
77 case TPM2_CC_GET_RANDOM:
78 return TPM_LONG;
79
80 case TPM2_CC_SEQUENCE_UPDATE:
81 return TPM_MEDIUM;
82 case TPM2_CC_SEQUENCE_COMPLETE:
83 return TPM_MEDIUM;
84 case TPM2_CC_EVENT_SEQUENCE_COMPLETE:
85 return TPM_MEDIUM;
86 case TPM2_CC_HASH_SEQUENCE_START:
87 return TPM_MEDIUM;
88
89 case TPM2_CC_VERIFY_SIGNATURE:
90 return TPM_LONG_LONG;
91
92 case TPM2_CC_PCR_EXTEND:
93 return TPM_MEDIUM;
94
95 case TPM2_CC_HIERARCHY_CONTROL:
96 return TPM_LONG;
97 case TPM2_CC_HIERARCHY_CHANGE_AUTH:
98 return TPM_LONG;
99
100 case TPM2_CC_GET_CAPABILITY:
101 return TPM_MEDIUM;
102
103 case TPM2_CC_NV_READ:
104 return TPM_LONG;
105
106 case TPM2_CC_CREATE_PRIMARY:
107 return TPM_LONG_LONG;
108 case TPM2_CC_CREATE:
109 return TPM_LONG_LONG;
110 case TPM2_CC_CREATE_LOADED:
111 return TPM_LONG_LONG;
112
113 default:
114 return TPM_UNDEFINED;
115 }
116}
117
118
119
120
121
122
123
124
125
126
127
128unsigned long tpm2_calc_ordinal_duration(struct tpm_chip *chip, u32 ordinal)
129{
130 unsigned int index;
131
132 index = tpm2_ordinal_duration_index(ordinal);
133
134 if (index != TPM_UNDEFINED)
135 return chip->duration[index];
136 else
137 return msecs_to_jiffies(TPM2_DURATION_DEFAULT);
138}
139
140
141struct tpm2_pcr_read_out {
142 __be32 update_cnt;
143 __be32 pcr_selects_cnt;
144 __be16 hash_alg;
145 u8 pcr_select_size;
146 u8 pcr_select[TPM2_PCR_SELECT_MIN];
147 __be32 digests_cnt;
148 __be16 digest_size;
149 u8 digest[];
150} __packed;
151
152
153
154
155
156
157
158
159
160
161int tpm2_pcr_read(struct tpm_chip *chip, u32 pcr_idx,
162 struct tpm_digest *digest, u16 *digest_size_ptr)
163{
164 int i;
165 int rc;
166 struct tpm_buf buf;
167 struct tpm2_pcr_read_out *out;
168 u8 pcr_select[TPM2_PCR_SELECT_MIN] = {0};
169 u16 digest_size;
170 u16 expected_digest_size = 0;
171
172 if (pcr_idx >= TPM2_PLATFORM_PCR)
173 return -EINVAL;
174
175 if (!digest_size_ptr) {
176 for (i = 0; i < chip->nr_allocated_banks &&
177 chip->allocated_banks[i].alg_id != digest->alg_id; i++)
178 ;
179
180 if (i == chip->nr_allocated_banks)
181 return -EINVAL;
182
183 expected_digest_size = chip->allocated_banks[i].digest_size;
184 }
185
186 rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_PCR_READ);
187 if (rc)
188 return rc;
189
190 pcr_select[pcr_idx >> 3] = 1 << (pcr_idx & 0x7);
191
192 tpm_buf_append_u32(&buf, 1);
193 tpm_buf_append_u16(&buf, digest->alg_id);
194 tpm_buf_append_u8(&buf, TPM2_PCR_SELECT_MIN);
195 tpm_buf_append(&buf, (const unsigned char *)pcr_select,
196 sizeof(pcr_select));
197
198 rc = tpm_transmit_cmd(chip, &buf, 0, "attempting to read a pcr value");
199 if (rc)
200 goto out;
201
202 out = (struct tpm2_pcr_read_out *)&buf.data[TPM_HEADER_SIZE];
203 digest_size = be16_to_cpu(out->digest_size);
204 if (digest_size > sizeof(digest->digest) ||
205 (!digest_size_ptr && digest_size != expected_digest_size)) {
206 rc = -EINVAL;
207 goto out;
208 }
209
210 if (digest_size_ptr)
211 *digest_size_ptr = digest_size;
212
213 memcpy(digest->digest, out->digest, digest_size);
214out:
215 tpm_buf_destroy(&buf);
216 return rc;
217}
218
219struct tpm2_null_auth_area {
220 __be32 handle;
221 __be16 nonce_size;
222 u8 attributes;
223 __be16 auth_size;
224} __packed;
225
226
227
228
229
230
231
232
233
234
235int tpm2_pcr_extend(struct tpm_chip *chip, u32 pcr_idx,
236 struct tpm_digest *digests)
237{
238 struct tpm_buf buf;
239 struct tpm2_null_auth_area auth_area;
240 int rc;
241 int i;
242
243 rc = tpm_buf_init(&buf, TPM2_ST_SESSIONS, TPM2_CC_PCR_EXTEND);
244 if (rc)
245 return rc;
246
247 tpm_buf_append_u32(&buf, pcr_idx);
248
249 auth_area.handle = cpu_to_be32(TPM2_RS_PW);
250 auth_area.nonce_size = 0;
251 auth_area.attributes = 0;
252 auth_area.auth_size = 0;
253
254 tpm_buf_append_u32(&buf, sizeof(struct tpm2_null_auth_area));
255 tpm_buf_append(&buf, (const unsigned char *)&auth_area,
256 sizeof(auth_area));
257 tpm_buf_append_u32(&buf, chip->nr_allocated_banks);
258
259 for (i = 0; i < chip->nr_allocated_banks; i++) {
260 tpm_buf_append_u16(&buf, digests[i].alg_id);
261 tpm_buf_append(&buf, (const unsigned char *)&digests[i].digest,
262 chip->allocated_banks[i].digest_size);
263 }
264
265 rc = tpm_transmit_cmd(chip, &buf, 0, "attempting extend a PCR value");
266
267 tpm_buf_destroy(&buf);
268
269 return rc;
270}
271
272struct tpm2_get_random_out {
273 __be16 size;
274 u8 buffer[TPM_MAX_RNG_DATA];
275} __packed;
276
277
278
279
280
281
282
283
284
285
286
287
288int tpm2_get_random(struct tpm_chip *chip, u8 *dest, size_t max)
289{
290 struct tpm2_get_random_out *out;
291 struct tpm_buf buf;
292 u32 recd;
293 u32 num_bytes = max;
294 int err;
295 int total = 0;
296 int retries = 5;
297 u8 *dest_ptr = dest;
298
299 if (!num_bytes || max > TPM_MAX_RNG_DATA)
300 return -EINVAL;
301
302 err = tpm_buf_init(&buf, 0, 0);
303 if (err)
304 return err;
305
306 do {
307 tpm_buf_reset(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_RANDOM);
308 tpm_buf_append_u16(&buf, num_bytes);
309 err = tpm_transmit_cmd(chip, &buf,
310 offsetof(struct tpm2_get_random_out,
311 buffer),
312 "attempting get random");
313 if (err) {
314 if (err > 0)
315 err = -EIO;
316 goto out;
317 }
318
319 out = (struct tpm2_get_random_out *)
320 &buf.data[TPM_HEADER_SIZE];
321 recd = min_t(u32, be16_to_cpu(out->size), num_bytes);
322 if (tpm_buf_length(&buf) <
323 TPM_HEADER_SIZE +
324 offsetof(struct tpm2_get_random_out, buffer) +
325 recd) {
326 err = -EFAULT;
327 goto out;
328 }
329 memcpy(dest_ptr, out->buffer, recd);
330
331 dest_ptr += recd;
332 total += recd;
333 num_bytes -= recd;
334 } while (retries-- && total < max);
335
336 tpm_buf_destroy(&buf);
337 return total ? total : -EIO;
338out:
339 tpm_buf_destroy(&buf);
340 return err;
341}
342
343
344
345
346
347
348void tpm2_flush_context(struct tpm_chip *chip, u32 handle)
349{
350 struct tpm_buf buf;
351 int rc;
352
353 rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_FLUSH_CONTEXT);
354 if (rc) {
355 dev_warn(&chip->dev, "0x%08x was not flushed, out of memory\n",
356 handle);
357 return;
358 }
359
360 tpm_buf_append_u32(&buf, handle);
361
362 tpm_transmit_cmd(chip, &buf, 0, "flushing context");
363 tpm_buf_destroy(&buf);
364}
365EXPORT_SYMBOL_GPL(tpm2_flush_context);
366
367struct tpm2_get_cap_out {
368 u8 more_data;
369 __be32 subcap_id;
370 __be32 property_cnt;
371 __be32 property_id;
372 __be32 value;
373} __packed;
374
375
376
377
378
379
380
381
382
383
384
385
386ssize_t tpm2_get_tpm_pt(struct tpm_chip *chip, u32 property_id, u32 *value,
387 const char *desc)
388{
389 struct tpm2_get_cap_out *out;
390 struct tpm_buf buf;
391 int rc;
392
393 rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_CAPABILITY);
394 if (rc)
395 return rc;
396 tpm_buf_append_u32(&buf, TPM2_CAP_TPM_PROPERTIES);
397 tpm_buf_append_u32(&buf, property_id);
398 tpm_buf_append_u32(&buf, 1);
399 rc = tpm_transmit_cmd(chip, &buf, 0, NULL);
400 if (!rc) {
401 out = (struct tpm2_get_cap_out *)
402 &buf.data[TPM_HEADER_SIZE];
403 *value = be32_to_cpu(out->value);
404 }
405 tpm_buf_destroy(&buf);
406 return rc;
407}
408EXPORT_SYMBOL_GPL(tpm2_get_tpm_pt);
409
410
411
412
413
414
415
416
417
418
419
420void tpm2_shutdown(struct tpm_chip *chip, u16 shutdown_type)
421{
422 struct tpm_buf buf;
423 int rc;
424
425 rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_SHUTDOWN);
426 if (rc)
427 return;
428 tpm_buf_append_u16(&buf, shutdown_type);
429 tpm_transmit_cmd(chip, &buf, 0, "stopping the TPM");
430 tpm_buf_destroy(&buf);
431}
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446static int tpm2_do_selftest(struct tpm_chip *chip)
447{
448 struct tpm_buf buf;
449 int full;
450 int rc;
451
452 for (full = 0; full < 2; full++) {
453 rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_SELF_TEST);
454 if (rc)
455 return rc;
456
457 tpm_buf_append_u8(&buf, full);
458 rc = tpm_transmit_cmd(chip, &buf, 0,
459 "attempting the self test");
460 tpm_buf_destroy(&buf);
461
462 if (rc == TPM2_RC_TESTING)
463 rc = TPM2_RC_SUCCESS;
464 if (rc == TPM2_RC_INITIALIZE || rc == TPM2_RC_SUCCESS)
465 return rc;
466 }
467
468 return rc;
469}
470
471
472
473
474
475
476
477
478
479
480
481
482
483int tpm2_probe(struct tpm_chip *chip)
484{
485 struct tpm_header *out;
486 struct tpm_buf buf;
487 int rc;
488
489 rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_CAPABILITY);
490 if (rc)
491 return rc;
492 tpm_buf_append_u32(&buf, TPM2_CAP_TPM_PROPERTIES);
493 tpm_buf_append_u32(&buf, TPM_PT_TOTAL_COMMANDS);
494 tpm_buf_append_u32(&buf, 1);
495 rc = tpm_transmit_cmd(chip, &buf, 0, NULL);
496
497 if (rc >= 0) {
498 out = (struct tpm_header *)buf.data;
499 if (be16_to_cpu(out->tag) == TPM2_ST_NO_SESSIONS)
500 chip->flags |= TPM_CHIP_FLAG_TPM2;
501 }
502 tpm_buf_destroy(&buf);
503 return 0;
504}
505EXPORT_SYMBOL_GPL(tpm2_probe);
506
507static int tpm2_init_bank_info(struct tpm_chip *chip, u32 bank_index)
508{
509 struct tpm_bank_info *bank = chip->allocated_banks + bank_index;
510 struct tpm_digest digest = { .alg_id = bank->alg_id };
511 int i;
512
513
514
515
516
517 for (i = 0; i < ARRAY_SIZE(tpm2_hash_map); i++) {
518 enum hash_algo crypto_algo = tpm2_hash_map[i].crypto_id;
519
520 if (bank->alg_id != tpm2_hash_map[i].tpm_id)
521 continue;
522
523 bank->digest_size = hash_digest_size[crypto_algo];
524 bank->crypto_id = crypto_algo;
525 return 0;
526 }
527
528 bank->crypto_id = HASH_ALGO__LAST;
529
530 return tpm2_pcr_read(chip, 0, &digest, &bank->digest_size);
531}
532
533struct tpm2_pcr_selection {
534 __be16 hash_alg;
535 u8 size_of_select;
536 u8 pcr_select[3];
537} __packed;
538
539ssize_t tpm2_get_pcr_allocation(struct tpm_chip *chip)
540{
541 struct tpm2_pcr_selection pcr_selection;
542 struct tpm_buf buf;
543 void *marker;
544 void *end;
545 void *pcr_select_offset;
546 u32 sizeof_pcr_selection;
547 u32 nr_possible_banks;
548 u32 nr_alloc_banks = 0;
549 u16 hash_alg;
550 u32 rsp_len;
551 int rc;
552 int i = 0;
553
554 rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_CAPABILITY);
555 if (rc)
556 return rc;
557
558 tpm_buf_append_u32(&buf, TPM2_CAP_PCRS);
559 tpm_buf_append_u32(&buf, 0);
560 tpm_buf_append_u32(&buf, 1);
561
562 rc = tpm_transmit_cmd(chip, &buf, 9, "get tpm pcr allocation");
563 if (rc)
564 goto out;
565
566 nr_possible_banks = be32_to_cpup(
567 (__be32 *)&buf.data[TPM_HEADER_SIZE + 5]);
568
569 chip->allocated_banks = kcalloc(nr_possible_banks,
570 sizeof(*chip->allocated_banks),
571 GFP_KERNEL);
572 if (!chip->allocated_banks) {
573 rc = -ENOMEM;
574 goto out;
575 }
576
577 marker = &buf.data[TPM_HEADER_SIZE + 9];
578
579 rsp_len = be32_to_cpup((__be32 *)&buf.data[2]);
580 end = &buf.data[rsp_len];
581
582 for (i = 0; i < nr_possible_banks; i++) {
583 pcr_select_offset = marker +
584 offsetof(struct tpm2_pcr_selection, size_of_select);
585 if (pcr_select_offset >= end) {
586 rc = -EFAULT;
587 break;
588 }
589
590 memcpy(&pcr_selection, marker, sizeof(pcr_selection));
591 hash_alg = be16_to_cpu(pcr_selection.hash_alg);
592
593 pcr_select_offset = memchr_inv(pcr_selection.pcr_select, 0,
594 pcr_selection.size_of_select);
595 if (pcr_select_offset) {
596 chip->allocated_banks[nr_alloc_banks].alg_id = hash_alg;
597
598 rc = tpm2_init_bank_info(chip, nr_alloc_banks);
599 if (rc < 0)
600 break;
601
602 nr_alloc_banks++;
603 }
604
605 sizeof_pcr_selection = sizeof(pcr_selection.hash_alg) +
606 sizeof(pcr_selection.size_of_select) +
607 pcr_selection.size_of_select;
608 marker = marker + sizeof_pcr_selection;
609 }
610
611 chip->nr_allocated_banks = nr_alloc_banks;
612out:
613 tpm_buf_destroy(&buf);
614
615 return rc;
616}
617
618int tpm2_get_cc_attrs_tbl(struct tpm_chip *chip)
619{
620 struct tpm_buf buf;
621 u32 nr_commands;
622 __be32 *attrs;
623 u32 cc;
624 int i;
625 int rc;
626
627 rc = tpm2_get_tpm_pt(chip, TPM_PT_TOTAL_COMMANDS, &nr_commands, NULL);
628 if (rc)
629 goto out;
630
631 if (nr_commands > 0xFFFFF) {
632 rc = -EFAULT;
633 goto out;
634 }
635
636 chip->cc_attrs_tbl = devm_kcalloc(&chip->dev, 4, nr_commands,
637 GFP_KERNEL);
638 if (!chip->cc_attrs_tbl) {
639 rc = -ENOMEM;
640 goto out;
641 }
642
643 rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_CAPABILITY);
644 if (rc)
645 goto out;
646
647 tpm_buf_append_u32(&buf, TPM2_CAP_COMMANDS);
648 tpm_buf_append_u32(&buf, TPM2_CC_FIRST);
649 tpm_buf_append_u32(&buf, nr_commands);
650
651 rc = tpm_transmit_cmd(chip, &buf, 9 + 4 * nr_commands, NULL);
652 if (rc) {
653 tpm_buf_destroy(&buf);
654 goto out;
655 }
656
657 if (nr_commands !=
658 be32_to_cpup((__be32 *)&buf.data[TPM_HEADER_SIZE + 5])) {
659 rc = -EFAULT;
660 tpm_buf_destroy(&buf);
661 goto out;
662 }
663
664 chip->nr_commands = nr_commands;
665
666 attrs = (__be32 *)&buf.data[TPM_HEADER_SIZE + 9];
667 for (i = 0; i < nr_commands; i++, attrs++) {
668 chip->cc_attrs_tbl[i] = be32_to_cpup(attrs);
669 cc = chip->cc_attrs_tbl[i] & 0xFFFF;
670
671 if (cc == TPM2_CC_CONTEXT_SAVE || cc == TPM2_CC_FLUSH_CONTEXT) {
672 chip->cc_attrs_tbl[i] &=
673 ~(GENMASK(2, 0) << TPM2_CC_ATTR_CHANDLES);
674 chip->cc_attrs_tbl[i] |= 1 << TPM2_CC_ATTR_CHANDLES;
675 }
676 }
677
678 tpm_buf_destroy(&buf);
679
680out:
681 if (rc > 0)
682 rc = -ENODEV;
683 return rc;
684}
685EXPORT_SYMBOL_GPL(tpm2_get_cc_attrs_tbl);
686
687
688
689
690
691
692
693
694
695
696
697
698static int tpm2_startup(struct tpm_chip *chip)
699{
700 struct tpm_buf buf;
701 int rc;
702
703 dev_info(&chip->dev, "starting up the TPM manually\n");
704
705 rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_STARTUP);
706 if (rc < 0)
707 return rc;
708
709 tpm_buf_append_u16(&buf, TPM2_SU_CLEAR);
710 rc = tpm_transmit_cmd(chip, &buf, 0, "attempting to start the TPM");
711 tpm_buf_destroy(&buf);
712
713 return rc;
714}
715
716
717
718
719
720
721
722
723int tpm2_auto_startup(struct tpm_chip *chip)
724{
725 int rc;
726
727 rc = tpm2_get_timeouts(chip);
728 if (rc)
729 goto out;
730
731 rc = tpm2_do_selftest(chip);
732 if (rc && rc != TPM2_RC_INITIALIZE)
733 goto out;
734
735 if (rc == TPM2_RC_INITIALIZE) {
736 rc = tpm2_startup(chip);
737 if (rc)
738 goto out;
739
740 rc = tpm2_do_selftest(chip);
741 if (rc)
742 goto out;
743 }
744
745 rc = tpm2_get_cc_attrs_tbl(chip);
746
747out:
748 if (rc == TPM2_RC_UPGRADE) {
749 dev_info(&chip->dev, "TPM in field upgrade mode, requires firmware upgrade\n");
750 chip->flags |= TPM_CHIP_FLAG_FIRMWARE_UPGRADE;
751 rc = 0;
752 }
753
754 if (rc > 0)
755 rc = -ENODEV;
756 return rc;
757}
758
759int tpm2_find_cc(struct tpm_chip *chip, u32 cc)
760{
761 int i;
762
763 for (i = 0; i < chip->nr_commands; i++)
764 if (cc == (chip->cc_attrs_tbl[i] & GENMASK(15, 0)))
765 return i;
766
767 return -1;
768}
769