linux/drivers/gpio/gpio-xilinx.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Xilinx gpio driver for xps/axi_gpio IP.
   4 *
   5 * Copyright 2008 - 2013 Xilinx, Inc.
   6 */
   7
   8#include <linux/bitmap.h>
   9#include <linux/bitops.h>
  10#include <linux/clk.h>
  11#include <linux/errno.h>
  12#include <linux/gpio/driver.h>
  13#include <linux/init.h>
  14#include <linux/interrupt.h>
  15#include <linux/io.h>
  16#include <linux/irq.h>
  17#include <linux/module.h>
  18#include <linux/of_device.h>
  19#include <linux/of_platform.h>
  20#include <linux/pm_runtime.h>
  21#include <linux/slab.h>
  22
  23/* Register Offset Definitions */
  24#define XGPIO_DATA_OFFSET   (0x0)       /* Data register  */
  25#define XGPIO_TRI_OFFSET    (0x4)       /* I/O direction register  */
  26
  27#define XGPIO_CHANNEL0_OFFSET   0x0
  28#define XGPIO_CHANNEL1_OFFSET   0x8
  29
  30#define XGPIO_GIER_OFFSET       0x11c /* Global Interrupt Enable */
  31#define XGPIO_GIER_IE           BIT(31)
  32#define XGPIO_IPISR_OFFSET      0x120 /* IP Interrupt Status */
  33#define XGPIO_IPIER_OFFSET      0x128 /* IP Interrupt Enable */
  34
  35/* Read/Write access to the GPIO registers */
  36#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
  37# define xgpio_readreg(offset)          readl(offset)
  38# define xgpio_writereg(offset, val)    writel(val, offset)
  39#else
  40# define xgpio_readreg(offset)          __raw_readl(offset)
  41# define xgpio_writereg(offset, val)    __raw_writel(val, offset)
  42#endif
  43
  44/**
  45 * struct xgpio_instance - Stores information about GPIO device
  46 * @gc: GPIO chip
  47 * @regs: register block
  48 * @hw_map: GPIO pin mapping on hardware side
  49 * @sw_map: GPIO pin mapping on software side
  50 * @state: GPIO write state shadow register
  51 * @last_irq_read: GPIO read state register from last interrupt
  52 * @dir: GPIO direction shadow register
  53 * @gpio_lock: Lock used for synchronization
  54 * @irq: IRQ used by GPIO device
  55 * @irqchip: IRQ chip
  56 * @enable: GPIO IRQ enable/disable bitfield
  57 * @rising_edge: GPIO IRQ rising edge enable/disable bitfield
  58 * @falling_edge: GPIO IRQ falling edge enable/disable bitfield
  59 * @clk: clock resource for this driver
  60 */
  61struct xgpio_instance {
  62        struct gpio_chip gc;
  63        void __iomem *regs;
  64        DECLARE_BITMAP(hw_map, 64);
  65        DECLARE_BITMAP(sw_map, 64);
  66        DECLARE_BITMAP(state, 64);
  67        DECLARE_BITMAP(last_irq_read, 64);
  68        DECLARE_BITMAP(dir, 64);
  69        spinlock_t gpio_lock;   /* For serializing operations */
  70        int irq;
  71        struct irq_chip irqchip;
  72        DECLARE_BITMAP(enable, 64);
  73        DECLARE_BITMAP(rising_edge, 64);
  74        DECLARE_BITMAP(falling_edge, 64);
  75        struct clk *clk;
  76};
  77
  78static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit)
  79{
  80        return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64);
  81}
  82
  83static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio)
  84{
  85        return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64);
  86}
  87
  88static inline u32 xgpio_get_value32(const unsigned long *map, int bit)
  89{
  90        const size_t index = BIT_WORD(bit);
  91        const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
  92
  93        return (map[index] >> offset) & 0xFFFFFFFFul;
  94}
  95
  96static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v)
  97{
  98        const size_t index = BIT_WORD(bit);
  99        const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
 100
 101        map[index] &= ~(0xFFFFFFFFul << offset);
 102        map[index] |= v << offset;
 103}
 104
 105static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch)
 106{
 107        switch (ch) {
 108        case 0:
 109                return XGPIO_CHANNEL0_OFFSET;
 110        case 1:
 111                return XGPIO_CHANNEL1_OFFSET;
 112        default:
 113                return -EINVAL;
 114        }
 115}
 116
 117static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
 118{
 119        void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
 120        xgpio_set_value32(a, bit, xgpio_readreg(addr));
 121}
 122
 123static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
 124{
 125        void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
 126        xgpio_writereg(addr, xgpio_get_value32(a, bit));
 127}
 128
 129static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
 130{
 131        int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
 132
 133        for (bit = 0; bit <= lastbit ; bit += 32)
 134                xgpio_read_ch(chip, reg, bit, a);
 135}
 136
 137static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
 138{
 139        int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
 140
 141        for (bit = 0; bit <= lastbit ; bit += 32)
 142                xgpio_write_ch(chip, reg, bit, a);
 143}
 144
 145/**
 146 * xgpio_get - Read the specified signal of the GPIO device.
 147 * @gc:     Pointer to gpio_chip device structure.
 148 * @gpio:   GPIO signal number.
 149 *
 150 * This function reads the specified signal of the GPIO device.
 151 *
 152 * Return:
 153 * 0 if direction of GPIO signals is set as input otherwise it
 154 * returns negative error value.
 155 */
 156static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
 157{
 158        struct xgpio_instance *chip = gpiochip_get_data(gc);
 159        int bit = xgpio_to_bit(chip, gpio);
 160        DECLARE_BITMAP(state, 64);
 161
 162        xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state);
 163
 164        return test_bit(bit, state);
 165}
 166
 167/**
 168 * xgpio_set - Write the specified signal of the GPIO device.
 169 * @gc:     Pointer to gpio_chip device structure.
 170 * @gpio:   GPIO signal number.
 171 * @val:    Value to be written to specified signal.
 172 *
 173 * This function writes the specified value in to the specified signal of the
 174 * GPIO device.
 175 */
 176static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 177{
 178        unsigned long flags;
 179        struct xgpio_instance *chip = gpiochip_get_data(gc);
 180        int bit = xgpio_to_bit(chip, gpio);
 181
 182        spin_lock_irqsave(&chip->gpio_lock, flags);
 183
 184        /* Write to GPIO signal and set its direction to output */
 185        __assign_bit(bit, chip->state, val);
 186
 187        xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
 188
 189        spin_unlock_irqrestore(&chip->gpio_lock, flags);
 190}
 191
 192/**
 193 * xgpio_set_multiple - Write the specified signals of the GPIO device.
 194 * @gc:     Pointer to gpio_chip device structure.
 195 * @mask:   Mask of the GPIOS to modify.
 196 * @bits:   Value to be wrote on each GPIO
 197 *
 198 * This function writes the specified values into the specified signals of the
 199 * GPIO devices.
 200 */
 201static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
 202                               unsigned long *bits)
 203{
 204        DECLARE_BITMAP(hw_mask, 64);
 205        DECLARE_BITMAP(hw_bits, 64);
 206        DECLARE_BITMAP(state, 64);
 207        unsigned long flags;
 208        struct xgpio_instance *chip = gpiochip_get_data(gc);
 209
 210        bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64);
 211        bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64);
 212
 213        spin_lock_irqsave(&chip->gpio_lock, flags);
 214
 215        bitmap_replace(state, chip->state, hw_bits, hw_mask, 64);
 216
 217        xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state);
 218
 219        bitmap_copy(chip->state, state, 64);
 220
 221        spin_unlock_irqrestore(&chip->gpio_lock, flags);
 222}
 223
 224/**
 225 * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
 226 * @gc:     Pointer to gpio_chip device structure.
 227 * @gpio:   GPIO signal number.
 228 *
 229 * Return:
 230 * 0 - if direction of GPIO signals is set as input
 231 * otherwise it returns negative error value.
 232 */
 233static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 234{
 235        unsigned long flags;
 236        struct xgpio_instance *chip = gpiochip_get_data(gc);
 237        int bit = xgpio_to_bit(chip, gpio);
 238
 239        spin_lock_irqsave(&chip->gpio_lock, flags);
 240
 241        /* Set the GPIO bit in shadow register and set direction as input */
 242        __set_bit(bit, chip->dir);
 243        xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
 244
 245        spin_unlock_irqrestore(&chip->gpio_lock, flags);
 246
 247        return 0;
 248}
 249
 250/**
 251 * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
 252 * @gc:     Pointer to gpio_chip device structure.
 253 * @gpio:   GPIO signal number.
 254 * @val:    Value to be written to specified signal.
 255 *
 256 * This function sets the direction of specified GPIO signal as output.
 257 *
 258 * Return:
 259 * If all GPIO signals of GPIO chip is configured as input then it returns
 260 * error otherwise it returns 0.
 261 */
 262static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 263{
 264        unsigned long flags;
 265        struct xgpio_instance *chip = gpiochip_get_data(gc);
 266        int bit = xgpio_to_bit(chip, gpio);
 267
 268        spin_lock_irqsave(&chip->gpio_lock, flags);
 269
 270        /* Write state of GPIO signal */
 271        __assign_bit(bit, chip->state, val);
 272        xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
 273
 274        /* Clear the GPIO bit in shadow register and set direction as output */
 275        __clear_bit(bit, chip->dir);
 276        xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
 277
 278        spin_unlock_irqrestore(&chip->gpio_lock, flags);
 279
 280        return 0;
 281}
 282
 283/**
 284 * xgpio_save_regs - Set initial values of GPIO pins
 285 * @chip: Pointer to GPIO instance
 286 */
 287static void xgpio_save_regs(struct xgpio_instance *chip)
 288{
 289        xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state);
 290        xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir);
 291}
 292
 293static int xgpio_request(struct gpio_chip *chip, unsigned int offset)
 294{
 295        int ret;
 296
 297        ret = pm_runtime_get_sync(chip->parent);
 298        /*
 299         * If the device is already active pm_runtime_get() will return 1 on
 300         * success, but gpio_request still needs to return 0.
 301         */
 302        return ret < 0 ? ret : 0;
 303}
 304
 305static void xgpio_free(struct gpio_chip *chip, unsigned int offset)
 306{
 307        pm_runtime_put(chip->parent);
 308}
 309
 310static int __maybe_unused xgpio_suspend(struct device *dev)
 311{
 312        struct xgpio_instance *gpio = dev_get_drvdata(dev);
 313        struct irq_data *data = irq_get_irq_data(gpio->irq);
 314
 315        if (!data) {
 316                dev_dbg(dev, "IRQ not connected\n");
 317                return pm_runtime_force_suspend(dev);
 318        }
 319
 320        if (!irqd_is_wakeup_set(data))
 321                return pm_runtime_force_suspend(dev);
 322
 323        return 0;
 324}
 325
 326/**
 327 * xgpio_remove - Remove method for the GPIO device.
 328 * @pdev: pointer to the platform device
 329 *
 330 * This function remove gpiochips and frees all the allocated resources.
 331 *
 332 * Return: 0 always
 333 */
 334static int xgpio_remove(struct platform_device *pdev)
 335{
 336        struct xgpio_instance *gpio = platform_get_drvdata(pdev);
 337
 338        pm_runtime_get_sync(&pdev->dev);
 339        pm_runtime_put_noidle(&pdev->dev);
 340        pm_runtime_disable(&pdev->dev);
 341        clk_disable_unprepare(gpio->clk);
 342
 343        return 0;
 344}
 345
 346/**
 347 * xgpio_irq_ack - Acknowledge a child GPIO interrupt.
 348 * @irq_data: per IRQ and chip data passed down to chip functions
 349 * This currently does nothing, but irq_ack is unconditionally called by
 350 * handle_edge_irq and therefore must be defined.
 351 */
 352static void xgpio_irq_ack(struct irq_data *irq_data)
 353{
 354}
 355
 356static int __maybe_unused xgpio_resume(struct device *dev)
 357{
 358        struct xgpio_instance *gpio = dev_get_drvdata(dev);
 359        struct irq_data *data = irq_get_irq_data(gpio->irq);
 360
 361        if (!data) {
 362                dev_dbg(dev, "IRQ not connected\n");
 363                return pm_runtime_force_resume(dev);
 364        }
 365
 366        if (!irqd_is_wakeup_set(data))
 367                return pm_runtime_force_resume(dev);
 368
 369        return 0;
 370}
 371
 372static int __maybe_unused xgpio_runtime_suspend(struct device *dev)
 373{
 374        struct xgpio_instance *gpio = dev_get_drvdata(dev);
 375
 376        clk_disable(gpio->clk);
 377
 378        return 0;
 379}
 380
 381static int __maybe_unused xgpio_runtime_resume(struct device *dev)
 382{
 383        struct xgpio_instance *gpio = dev_get_drvdata(dev);
 384
 385        return clk_enable(gpio->clk);
 386}
 387
 388static const struct dev_pm_ops xgpio_dev_pm_ops = {
 389        SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume)
 390        SET_RUNTIME_PM_OPS(xgpio_runtime_suspend,
 391                           xgpio_runtime_resume, NULL)
 392};
 393
 394/**
 395 * xgpio_irq_mask - Write the specified signal of the GPIO device.
 396 * @irq_data: per IRQ and chip data passed down to chip functions
 397 */
 398static void xgpio_irq_mask(struct irq_data *irq_data)
 399{
 400        unsigned long flags;
 401        struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
 402        int irq_offset = irqd_to_hwirq(irq_data);
 403        int bit = xgpio_to_bit(chip, irq_offset);
 404        u32 mask = BIT(bit / 32), temp;
 405
 406        spin_lock_irqsave(&chip->gpio_lock, flags);
 407
 408        __clear_bit(bit, chip->enable);
 409
 410        if (xgpio_get_value32(chip->enable, bit) == 0) {
 411                /* Disable per channel interrupt */
 412                temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
 413                temp &= ~mask;
 414                xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);
 415        }
 416        spin_unlock_irqrestore(&chip->gpio_lock, flags);
 417}
 418
 419/**
 420 * xgpio_irq_unmask - Write the specified signal of the GPIO device.
 421 * @irq_data: per IRQ and chip data passed down to chip functions
 422 */
 423static void xgpio_irq_unmask(struct irq_data *irq_data)
 424{
 425        unsigned long flags;
 426        struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
 427        int irq_offset = irqd_to_hwirq(irq_data);
 428        int bit = xgpio_to_bit(chip, irq_offset);
 429        u32 old_enable = xgpio_get_value32(chip->enable, bit);
 430        u32 mask = BIT(bit / 32), val;
 431
 432        spin_lock_irqsave(&chip->gpio_lock, flags);
 433
 434        __set_bit(bit, chip->enable);
 435
 436        if (old_enable == 0) {
 437                /* Clear any existing per-channel interrupts */
 438                val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
 439                val &= mask;
 440                xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);
 441
 442                /* Update GPIO IRQ read data before enabling interrupt*/
 443                xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read);
 444
 445                /* Enable per channel interrupt */
 446                val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
 447                val |= mask;
 448                xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);
 449        }
 450
 451        spin_unlock_irqrestore(&chip->gpio_lock, flags);
 452}
 453
 454/**
 455 * xgpio_set_irq_type - Write the specified signal of the GPIO device.
 456 * @irq_data: Per IRQ and chip data passed down to chip functions
 457 * @type: Interrupt type that is to be set for the gpio pin
 458 *
 459 * Return:
 460 * 0 if interrupt type is supported otherwise -EINVAL
 461 */
 462static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
 463{
 464        struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
 465        int irq_offset = irqd_to_hwirq(irq_data);
 466        int bit = xgpio_to_bit(chip, irq_offset);
 467
 468        /*
 469         * The Xilinx GPIO hardware provides a single interrupt status
 470         * indication for any state change in a given GPIO channel (bank).
 471         * Therefore, only rising edge or falling edge triggers are
 472         * supported.
 473         */
 474        switch (type & IRQ_TYPE_SENSE_MASK) {
 475        case IRQ_TYPE_EDGE_BOTH:
 476                __set_bit(bit, chip->rising_edge);
 477                __set_bit(bit, chip->falling_edge);
 478                break;
 479        case IRQ_TYPE_EDGE_RISING:
 480                __set_bit(bit, chip->rising_edge);
 481                __clear_bit(bit, chip->falling_edge);
 482                break;
 483        case IRQ_TYPE_EDGE_FALLING:
 484                __clear_bit(bit, chip->rising_edge);
 485                __set_bit(bit, chip->falling_edge);
 486                break;
 487        default:
 488                return -EINVAL;
 489        }
 490
 491        irq_set_handler_locked(irq_data, handle_edge_irq);
 492        return 0;
 493}
 494
 495/**
 496 * xgpio_irqhandler - Gpio interrupt service routine
 497 * @desc: Pointer to interrupt description
 498 */
 499static void xgpio_irqhandler(struct irq_desc *desc)
 500{
 501        struct xgpio_instance *chip = irq_desc_get_handler_data(desc);
 502        struct gpio_chip *gc = &chip->gc;
 503        struct irq_chip *irqchip = irq_desc_get_chip(desc);
 504        DECLARE_BITMAP(rising, 64);
 505        DECLARE_BITMAP(falling, 64);
 506        DECLARE_BITMAP(all, 64);
 507        int irq_offset;
 508        u32 status;
 509        u32 bit;
 510
 511        status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
 512        xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);
 513
 514        chained_irq_enter(irqchip, desc);
 515
 516        spin_lock(&chip->gpio_lock);
 517
 518        xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all);
 519
 520        bitmap_complement(rising, chip->last_irq_read, 64);
 521        bitmap_and(rising, rising, all, 64);
 522        bitmap_and(rising, rising, chip->enable, 64);
 523        bitmap_and(rising, rising, chip->rising_edge, 64);
 524
 525        bitmap_complement(falling, all, 64);
 526        bitmap_and(falling, falling, chip->last_irq_read, 64);
 527        bitmap_and(falling, falling, chip->enable, 64);
 528        bitmap_and(falling, falling, chip->falling_edge, 64);
 529
 530        bitmap_copy(chip->last_irq_read, all, 64);
 531        bitmap_or(all, rising, falling, 64);
 532
 533        spin_unlock(&chip->gpio_lock);
 534
 535        dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);
 536
 537        for_each_set_bit(bit, all, 64) {
 538                irq_offset = xgpio_from_bit(chip, bit);
 539                generic_handle_domain_irq(gc->irq.domain, irq_offset);
 540        }
 541
 542        chained_irq_exit(irqchip, desc);
 543}
 544
 545/**
 546 * xgpio_probe - Probe method for the GPIO device.
 547 * @pdev: pointer to the platform device
 548 *
 549 * Return:
 550 * It returns 0, if the driver is bound to the GPIO device, or
 551 * a negative value if there is an error.
 552 */
 553static int xgpio_probe(struct platform_device *pdev)
 554{
 555        struct xgpio_instance *chip;
 556        int status = 0;
 557        struct device_node *np = pdev->dev.of_node;
 558        u32 is_dual = 0;
 559        u32 cells = 2;
 560        u32 width[2];
 561        u32 state[2];
 562        u32 dir[2];
 563        struct gpio_irq_chip *girq;
 564        u32 temp;
 565
 566        chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
 567        if (!chip)
 568                return -ENOMEM;
 569
 570        platform_set_drvdata(pdev, chip);
 571
 572        /* First, check if the device is dual-channel */
 573        of_property_read_u32(np, "xlnx,is-dual", &is_dual);
 574
 575        /* Setup defaults */
 576        memset32(width, 0, ARRAY_SIZE(width));
 577        memset32(state, 0, ARRAY_SIZE(state));
 578        memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir));
 579
 580        /* Update GPIO state shadow register with default value */
 581        of_property_read_u32(np, "xlnx,dout-default", &state[0]);
 582        of_property_read_u32(np, "xlnx,dout-default-2", &state[1]);
 583
 584        bitmap_from_arr32(chip->state, state, 64);
 585
 586        /* Update GPIO direction shadow register with default value */
 587        of_property_read_u32(np, "xlnx,tri-default", &dir[0]);
 588        of_property_read_u32(np, "xlnx,tri-default-2", &dir[1]);
 589
 590        bitmap_from_arr32(chip->dir, dir, 64);
 591
 592        /* Update cells with gpio-cells value */
 593        if (of_property_read_u32(np, "#gpio-cells", &cells))
 594                dev_dbg(&pdev->dev, "Missing gpio-cells property\n");
 595
 596        if (cells != 2) {
 597                dev_err(&pdev->dev, "#gpio-cells mismatch\n");
 598                return -EINVAL;
 599        }
 600
 601        /*
 602         * Check device node and parent device node for device width
 603         * and assume default width of 32
 604         */
 605        if (of_property_read_u32(np, "xlnx,gpio-width", &width[0]))
 606                width[0] = 32;
 607
 608        if (width[0] > 32)
 609                return -EINVAL;
 610
 611        if (is_dual && of_property_read_u32(np, "xlnx,gpio2-width", &width[1]))
 612                width[1] = 32;
 613
 614        if (width[1] > 32)
 615                return -EINVAL;
 616
 617        /* Setup software pin mapping */
 618        bitmap_set(chip->sw_map, 0, width[0] + width[1]);
 619
 620        /* Setup hardware pin mapping */
 621        bitmap_set(chip->hw_map,  0, width[0]);
 622        bitmap_set(chip->hw_map, 32, width[1]);
 623
 624        spin_lock_init(&chip->gpio_lock);
 625
 626        chip->gc.base = -1;
 627        chip->gc.ngpio = bitmap_weight(chip->hw_map, 64);
 628        chip->gc.parent = &pdev->dev;
 629        chip->gc.direction_input = xgpio_dir_in;
 630        chip->gc.direction_output = xgpio_dir_out;
 631        chip->gc.of_gpio_n_cells = cells;
 632        chip->gc.get = xgpio_get;
 633        chip->gc.set = xgpio_set;
 634        chip->gc.request = xgpio_request;
 635        chip->gc.free = xgpio_free;
 636        chip->gc.set_multiple = xgpio_set_multiple;
 637
 638        chip->gc.label = dev_name(&pdev->dev);
 639
 640        chip->regs = devm_platform_ioremap_resource(pdev, 0);
 641        if (IS_ERR(chip->regs)) {
 642                dev_err(&pdev->dev, "failed to ioremap memory resource\n");
 643                return PTR_ERR(chip->regs);
 644        }
 645
 646        chip->clk = devm_clk_get_optional(&pdev->dev, NULL);
 647        if (IS_ERR(chip->clk))
 648                return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n");
 649
 650        status = clk_prepare_enable(chip->clk);
 651        if (status < 0) {
 652                dev_err(&pdev->dev, "Failed to prepare clk\n");
 653                return status;
 654        }
 655        pm_runtime_get_noresume(&pdev->dev);
 656        pm_runtime_set_active(&pdev->dev);
 657        pm_runtime_enable(&pdev->dev);
 658
 659        xgpio_save_regs(chip);
 660
 661        chip->irq = platform_get_irq_optional(pdev, 0);
 662        if (chip->irq <= 0)
 663                goto skip_irq;
 664
 665        chip->irqchip.name = "gpio-xilinx";
 666        chip->irqchip.irq_ack = xgpio_irq_ack;
 667        chip->irqchip.irq_mask = xgpio_irq_mask;
 668        chip->irqchip.irq_unmask = xgpio_irq_unmask;
 669        chip->irqchip.irq_set_type = xgpio_set_irq_type;
 670
 671        /* Disable per-channel interrupts */
 672        xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0);
 673        /* Clear any existing per-channel interrupts */
 674        temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
 675        xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp);
 676        /* Enable global interrupts */
 677        xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);
 678
 679        girq = &chip->gc.irq;
 680        girq->chip = &chip->irqchip;
 681        girq->parent_handler = xgpio_irqhandler;
 682        girq->num_parents = 1;
 683        girq->parents = devm_kcalloc(&pdev->dev, 1,
 684                                     sizeof(*girq->parents),
 685                                     GFP_KERNEL);
 686        if (!girq->parents) {
 687                status = -ENOMEM;
 688                goto err_pm_put;
 689        }
 690        girq->parents[0] = chip->irq;
 691        girq->default_type = IRQ_TYPE_NONE;
 692        girq->handler = handle_bad_irq;
 693
 694skip_irq:
 695        status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
 696        if (status) {
 697                dev_err(&pdev->dev, "failed to add GPIO chip\n");
 698                goto err_pm_put;
 699        }
 700
 701        pm_runtime_put(&pdev->dev);
 702        return 0;
 703
 704err_pm_put:
 705        pm_runtime_disable(&pdev->dev);
 706        pm_runtime_put_noidle(&pdev->dev);
 707        clk_disable_unprepare(chip->clk);
 708        return status;
 709}
 710
 711static const struct of_device_id xgpio_of_match[] = {
 712        { .compatible = "xlnx,xps-gpio-1.00.a", },
 713        { /* end of list */ },
 714};
 715
 716MODULE_DEVICE_TABLE(of, xgpio_of_match);
 717
 718static struct platform_driver xgpio_plat_driver = {
 719        .probe          = xgpio_probe,
 720        .remove         = xgpio_remove,
 721        .driver         = {
 722                        .name = "gpio-xilinx",
 723                        .of_match_table = xgpio_of_match,
 724                        .pm = &xgpio_dev_pm_ops,
 725        },
 726};
 727
 728static int __init xgpio_init(void)
 729{
 730        return platform_driver_register(&xgpio_plat_driver);
 731}
 732
 733subsys_initcall(xgpio_init);
 734
 735static void __exit xgpio_exit(void)
 736{
 737        platform_driver_unregister(&xgpio_plat_driver);
 738}
 739module_exit(xgpio_exit);
 740
 741MODULE_AUTHOR("Xilinx, Inc.");
 742MODULE_DESCRIPTION("Xilinx GPIO driver");
 743MODULE_LICENSE("GPL");
 744