LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#ifndef __AMDGPU_CTX_H__
  24#define __AMDGPU_CTX_H__
  25
  26#include "amdgpu_ring.h"
  27
  28struct drm_device;
  29struct drm_file;
  30struct amdgpu_fpriv;
  31
  32#define AMDGPU_MAX_ENTITY_NUM 4
  33#define AMDGPU_CTX_FENCE_USAGE_MIN_RATIO(max, total) ((max) > 16384ULL*(total))
  34
  35struct amdgpu_ctx_entity {
  36        uint64_t                sequence;
  37        struct drm_sched_entity entity;
  38        struct dma_fence        *fences[];
  39};
  40
  41struct amdgpu_ctx {
  42        struct kref                     refcount;
  43        struct amdgpu_device            *adev;
  44        unsigned                        reset_counter;
  45        unsigned                        reset_counter_query;
  46        uint32_t                        vram_lost_counter;
  47        spinlock_t                      ring_lock;
  48        struct amdgpu_ctx_entity        *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM];
  49        bool                            preamble_presented;
  50        int32_t                         init_priority;
  51        int32_t                         override_priority;
  52        struct mutex                    lock;
  53        atomic_t                        guilty;
  54        unsigned long                   ras_counter_ce;
  55        unsigned long                   ras_counter_ue;
  56        uint32_t                        stable_pstate;
  57};
  58
  59struct amdgpu_ctx_mgr {
  60        struct amdgpu_device    *adev;
  61        struct mutex            lock;
  62        /* protected by lock */
  63        struct idr              ctx_handles;
  64};
  65
  66extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM];
  67
  68struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
  69int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
  70
  71int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,
  72                          u32 ring, struct drm_sched_entity **entity);
  73void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
  74                          struct drm_sched_entity *entity,
  75                          struct dma_fence *fence, uint64_t *seq);
  76struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
  77                                       struct drm_sched_entity *entity,
  78                                       uint64_t seq);
  79bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio);
  80void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, int32_t ctx_prio);
  81
  82int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
  83                     struct drm_file *filp);
  84
  85int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
  86                               struct drm_sched_entity *entity);
  87
  88void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
  89void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
  90long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
  91void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
  92ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
  93                uint32_t idx, uint64_t *elapsed);
  94#endif
  95