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24#ifndef __AMDGPU_RING_H__
25#define __AMDGPU_RING_H__
26
27#include <drm/amdgpu_drm.h>
28#include <drm/gpu_scheduler.h>
29#include <drm/drm_print.h>
30
31struct amdgpu_device;
32struct amdgpu_ring;
33struct amdgpu_ib;
34struct amdgpu_cs_parser;
35struct amdgpu_job;
36struct amdgpu_vm;
37
38
39#define AMDGPU_MAX_RINGS 28
40#define AMDGPU_MAX_HWIP_RINGS 8
41#define AMDGPU_MAX_GFX_RINGS 2
42#define AMDGPU_MAX_COMPUTE_RINGS 8
43#define AMDGPU_MAX_VCE_RINGS 3
44#define AMDGPU_MAX_UVD_ENC_RINGS 2
45
46enum amdgpu_ring_priority_level {
47 AMDGPU_RING_PRIO_0,
48 AMDGPU_RING_PRIO_1,
49 AMDGPU_RING_PRIO_DEFAULT = 1,
50 AMDGPU_RING_PRIO_2,
51 AMDGPU_RING_PRIO_MAX
52};
53
54
55#define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul)
56#define AMDGPU_FENCE_OWNER_VM ((void *)1ul)
57#define AMDGPU_FENCE_OWNER_KFD ((void *)2ul)
58
59#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
60#define AMDGPU_FENCE_FLAG_INT (1 << 1)
61#define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
62
63#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
64
65#define AMDGPU_IB_POOL_SIZE (1024 * 1024)
66
67enum amdgpu_ring_type {
68 AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX,
69 AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE,
70 AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA,
71 AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD,
72 AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE,
73 AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC,
74 AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC,
75 AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC,
76 AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG,
77 AMDGPU_RING_TYPE_KIQ,
78 AMDGPU_RING_TYPE_MES
79};
80
81enum amdgpu_ib_pool_type {
82
83 AMDGPU_IB_POOL_DELAYED,
84
85 AMDGPU_IB_POOL_IMMEDIATE,
86
87 AMDGPU_IB_POOL_DIRECT,
88
89 AMDGPU_IB_POOL_MAX
90};
91
92struct amdgpu_ib {
93 struct amdgpu_sa_bo *sa_bo;
94 uint32_t length_dw;
95 uint64_t gpu_addr;
96 uint32_t *ptr;
97 uint32_t flags;
98};
99
100struct amdgpu_sched {
101 u32 num_scheds;
102 struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS];
103};
104
105
106
107
108struct amdgpu_fence_driver {
109 uint64_t gpu_addr;
110 volatile uint32_t *cpu_addr;
111
112 uint32_t sync_seq;
113 atomic_t last_seq;
114 bool initialized;
115 struct amdgpu_irq_src *irq_src;
116 unsigned irq_type;
117 struct timer_list fallback_timer;
118 unsigned num_fences_mask;
119 spinlock_t lock;
120 struct dma_fence **fences;
121};
122
123extern const struct drm_sched_backend_ops amdgpu_sched_ops;
124
125void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
126void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
127
128int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
129int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
130 struct amdgpu_irq_src *irq_src,
131 unsigned irq_type);
132void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev);
133void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev);
134int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev);
135void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev);
136int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, struct amdgpu_job *job,
137 unsigned flags);
138int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
139 uint32_t timeout);
140bool amdgpu_fence_process(struct amdgpu_ring *ring);
141int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
142signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
143 uint32_t wait_seq,
144 signed long timeout);
145unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
146
147
148
149
150
151
152struct amdgpu_ring_funcs {
153 enum amdgpu_ring_type type;
154 uint32_t align_mask;
155 u32 nop;
156 bool support_64bit_ptrs;
157 bool no_user_fence;
158 bool secure_submission_supported;
159 unsigned vmhub;
160 unsigned extra_dw;
161
162
163 u64 (*get_rptr)(struct amdgpu_ring *ring);
164 u64 (*get_wptr)(struct amdgpu_ring *ring);
165 void (*set_wptr)(struct amdgpu_ring *ring);
166
167 int (*parse_cs)(struct amdgpu_cs_parser *p,
168 struct amdgpu_job *job,
169 struct amdgpu_ib *ib);
170 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p,
171 struct amdgpu_job *job,
172 struct amdgpu_ib *ib);
173
174 unsigned emit_frame_size;
175 unsigned emit_ib_size;
176
177 void (*emit_ib)(struct amdgpu_ring *ring,
178 struct amdgpu_job *job,
179 struct amdgpu_ib *ib,
180 uint32_t flags);
181 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
182 uint64_t seq, unsigned flags);
183 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
184 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
185 uint64_t pd_addr);
186 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
187 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
188 uint32_t gds_base, uint32_t gds_size,
189 uint32_t gws_base, uint32_t gws_size,
190 uint32_t oa_base, uint32_t oa_size);
191
192 int (*test_ring)(struct amdgpu_ring *ring);
193 int (*test_ib)(struct amdgpu_ring *ring, long timeout);
194
195 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
196 void (*insert_start)(struct amdgpu_ring *ring);
197 void (*insert_end)(struct amdgpu_ring *ring);
198
199 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
200 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
201 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
202
203 void (*begin_use)(struct amdgpu_ring *ring);
204 void (*end_use)(struct amdgpu_ring *ring);
205 void (*emit_switch_buffer) (struct amdgpu_ring *ring);
206 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
207 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
208 uint32_t reg_val_offs);
209 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
210 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
211 uint32_t val, uint32_t mask);
212 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
213 uint32_t reg0, uint32_t reg1,
214 uint32_t ref, uint32_t mask);
215 void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start,
216 bool secure);
217
218 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
219 int (*preempt_ib)(struct amdgpu_ring *ring);
220 void (*emit_mem_sync)(struct amdgpu_ring *ring);
221 void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
222};
223
224struct amdgpu_ring {
225 struct amdgpu_device *adev;
226 const struct amdgpu_ring_funcs *funcs;
227 struct amdgpu_fence_driver fence_drv;
228 struct drm_gpu_scheduler sched;
229
230 struct amdgpu_bo *ring_obj;
231 volatile uint32_t *ring;
232 unsigned rptr_offs;
233 u64 wptr;
234 u64 wptr_old;
235 unsigned ring_size;
236 unsigned max_dw;
237 int count_dw;
238 uint64_t gpu_addr;
239 uint64_t ptr_mask;
240 uint32_t buf_mask;
241 u32 idx;
242 u32 me;
243 u32 pipe;
244 u32 queue;
245 struct amdgpu_bo *mqd_obj;
246 uint64_t mqd_gpu_addr;
247 void *mqd_ptr;
248 uint64_t eop_gpu_addr;
249 u32 doorbell_index;
250 bool use_doorbell;
251 bool use_pollmem;
252 unsigned wptr_offs;
253 unsigned fence_offs;
254 uint64_t current_ctx;
255 char name[16];
256 u32 trail_seq;
257 unsigned trail_fence_offs;
258 u64 trail_fence_gpu_addr;
259 volatile u32 *trail_fence_cpu_addr;
260 unsigned cond_exe_offs;
261 u64 cond_exe_gpu_addr;
262 volatile u32 *cond_exe_cpu_addr;
263 unsigned vm_inv_eng;
264 struct dma_fence *vmid_wait;
265 bool has_compute_vm_bug;
266 bool no_scheduler;
267 int hw_prio;
268 unsigned num_hw_submission;
269 atomic_t *sched_score;
270};
271
272#define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))
273#define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib)))
274#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
275#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
276#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
277#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
278#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
279#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
280#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
281#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
282#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
283#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
284#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
285#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
286#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
287#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
288#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
289#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
290#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
291#define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
292#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
293#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
294#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
295#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
296
297int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
298void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
299void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
300void amdgpu_ring_commit(struct amdgpu_ring *ring);
301void amdgpu_ring_undo(struct amdgpu_ring *ring);
302int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
303 unsigned int max_dw, struct amdgpu_irq_src *irq_src,
304 unsigned int irq_type, unsigned int hw_prio,
305 atomic_t *sched_score);
306void amdgpu_ring_fini(struct amdgpu_ring *ring);
307void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
308 uint32_t reg0, uint32_t val0,
309 uint32_t reg1, uint32_t val1);
310bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
311 struct dma_fence *fence);
312
313static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
314 bool cond_exec)
315{
316 *ring->cond_exe_cpu_addr = cond_exec;
317}
318
319static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
320{
321 int i = 0;
322 while (i <= ring->buf_mask)
323 ring->ring[i++] = ring->funcs->nop;
324
325}
326
327static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
328{
329 if (ring->count_dw <= 0)
330 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
331 ring->ring[ring->wptr++ & ring->buf_mask] = v;
332 ring->wptr &= ring->ptr_mask;
333 ring->count_dw--;
334}
335
336static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
337 void *src, int count_dw)
338{
339 unsigned occupied, chunk1, chunk2;
340 void *dst;
341
342 if (unlikely(ring->count_dw < count_dw))
343 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
344
345 occupied = ring->wptr & ring->buf_mask;
346 dst = (void *)&ring->ring[occupied];
347 chunk1 = ring->buf_mask + 1 - occupied;
348 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
349 chunk2 = count_dw - chunk1;
350 chunk1 <<= 2;
351 chunk2 <<= 2;
352
353 if (chunk1)
354 memcpy(dst, src, chunk1);
355
356 if (chunk2) {
357 src += chunk1;
358 dst = (void *)ring->ring;
359 memcpy(dst, src, chunk2);
360 }
361
362 ring->wptr += count_dw;
363 ring->wptr &= ring->ptr_mask;
364 ring->count_dw -= count_dw;
365}
366
367int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
368
369void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
370 struct amdgpu_ring *ring);
371
372static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx)
373{
374 return ib->ptr[idx];
375}
376
377static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx,
378 uint32_t value)
379{
380 ib->ptr[idx] = value;
381}
382
383int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
384 unsigned size,
385 enum amdgpu_ib_pool_type pool,
386 struct amdgpu_ib *ib);
387void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
388 struct dma_fence *f);
389int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
390 struct amdgpu_ib *ibs, struct amdgpu_job *job,
391 struct dma_fence **f);
392int amdgpu_ib_pool_init(struct amdgpu_device *adev);
393void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
394int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
395
396#endif
397
