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26#ifndef __AMDGPU_DM_H__
27#define __AMDGPU_DM_H__
28
29#include <drm/drm_atomic.h>
30#include <drm/drm_connector.h>
31#include <drm/drm_crtc.h>
32#include <drm/dp/drm_dp_mst_helper.h>
33#include <drm/drm_plane.h>
34
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43
44
45#define AMDGPU_DM_MAX_DISPLAY_INDEX 31
46
47#define AMDGPU_DM_MAX_CRTC 6
48
49#define AMDGPU_DM_MAX_NUM_EDP 2
50
51#define AMDGPU_DMUB_NOTIFICATION_MAX 5
52
53
54
55
56#define DMUB_ASYNC_TO_SYNC_ACCESS_FAIL 1
57#define DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT 2
58#define DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS 3
59
60
61
62
63
64#include "irq_types.h"
65#include "signal_types.h"
66#include "amdgpu_dm_crc.h"
67struct aux_payload;
68enum aux_return_code_type;
69
70
71struct amdgpu_device;
72struct amdgpu_crtc;
73struct drm_device;
74struct dc;
75struct amdgpu_bo;
76struct dmub_srv;
77struct dc_plane_state;
78struct dmub_notification;
79
80struct common_irq_params {
81 struct amdgpu_device *adev;
82 enum dc_irq_source irq_src;
83 atomic64_t previous_timestamp;
84};
85
86
87
88
89
90
91
92struct dm_compressor_info {
93 void *cpu_addr;
94 struct amdgpu_bo *bo_ptr;
95 uint64_t gpu_addr;
96};
97
98typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify);
99
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103
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105
106
107struct dmub_hpd_work {
108 struct work_struct handle_hpd_work;
109 struct dmub_notification *dmub_notify;
110 struct amdgpu_device *adev;
111};
112
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119
120
121struct vblank_control_work {
122 struct work_struct work;
123 struct amdgpu_display_manager *dm;
124 struct amdgpu_crtc *acrtc;
125 struct dc_stream_state *stream;
126 bool enable;
127};
128
129
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131
132
133
134struct amdgpu_dm_backlight_caps {
135
136
137
138
139 union dpcd_sink_ext_caps *ext_caps;
140
141
142
143 u32 aux_min_input_signal;
144
145
146
147
148 u32 aux_max_input_signal;
149
150
151
152 int min_input_signal;
153
154
155
156 int max_input_signal;
157
158
159
160 bool caps_valid;
161
162
163
164 bool aux_support;
165};
166
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172
173
174struct dal_allocation {
175 struct list_head list;
176 struct amdgpu_bo *bo;
177 void *cpu_ptr;
178 u64 gpu_addr;
179};
180
181
182
183
184
185struct hpd_rx_irq_offload_work_queue {
186
187
188
189 struct workqueue_struct *wq;
190
191
192
193 spinlock_t offload_lock;
194
195
196
197
198 bool is_handling_link_loss;
199
200
201
202 struct amdgpu_dm_connector *aconnector;
203};
204
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206
207
208struct hpd_rx_irq_offload_work {
209
210
211
212 struct work_struct work;
213
214
215
216 union hpd_irq_data data;
217
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220 struct hpd_rx_irq_offload_work_queue *offload_wq;
221};
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245
246struct amdgpu_display_manager {
247
248 struct dc *dc;
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256
257 struct dmub_srv *dmub_srv;
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264
265 struct dmub_notification *dmub_notify;
266
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272
273 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX];
274
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281 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX];
282
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287
288 struct dmub_srv_fb_info *dmub_fb_info;
289
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294
295 const struct firmware *dmub_fw;
296
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301
302 struct amdgpu_bo *dmub_bo;
303
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309 u64 dmub_bo_gpu_addr;
310
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316 void *dmub_bo_cpu_addr;
317
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321
322
323 uint32_t dmcub_fw_version;
324
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330
331 struct cgs_device *cgs_device;
332
333 struct amdgpu_device *adev;
334 struct drm_device *ddev;
335 u16 display_indexes_num;
336
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343
344 struct drm_private_obj atomic_obj;
345
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351
352 struct mutex dc_lock;
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358
359 struct mutex audio_lock;
360
361#if defined(CONFIG_DRM_AMD_DC_DCN)
362
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366
367 spinlock_t vblank_lock;
368#endif
369
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374
375 struct drm_audio_component *audio_component;
376
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382
383 bool audio_registered;
384
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396
397 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
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407 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
408
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414
415 struct common_irq_params
416 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
417
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423
424 struct common_irq_params
425 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
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432
433 struct common_irq_params
434 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1];
435
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441
442 struct common_irq_params
443 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
444
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448
449
450
451 struct common_irq_params
452 dmub_trace_params[1];
453
454 struct common_irq_params
455 dmub_outbox_params[1];
456
457 spinlock_t irq_handler_list_table_lock;
458
459 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP];
460
461 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP];
462
463 uint8_t num_of_edps;
464
465 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP];
466
467 struct mod_freesync *freesync_module;
468#ifdef CONFIG_DRM_AMD_DC_HDCP
469 struct hdcp_workqueue *hdcp_workqueue;
470#endif
471
472#if defined(CONFIG_DRM_AMD_DC_DCN)
473
474
475
476
477
478 struct workqueue_struct *vblank_control_workqueue;
479#endif
480
481 struct drm_atomic_state *cached_state;
482 struct dc_state *cached_dc_state;
483
484 struct dm_compressor_info compressor;
485
486 const struct firmware *fw_dmcu;
487 uint32_t dmcu_fw_version;
488
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493
494 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
495
496#if defined(CONFIG_DRM_AMD_DC_DCN)
497
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501
502 uint32_t active_vblank_irq_count;
503#endif
504
505#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
506
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509
510
511 struct crc_rd_work *crc_rd_wrk;
512#endif
513
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518 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq;
519
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524 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
525 bool force_timing_sync;
526 bool disable_hpd_irq;
527 bool dmcub_trace_event_en;
528
529
530
531
532
533 struct list_head da_list;
534 struct completion dmub_aux_transfer_done;
535 struct workqueue_struct *delayed_hpd_wq;
536
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541
542 u32 brightness[AMDGPU_DM_MAX_NUM_EDP];
543
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548 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP];
549};
550
551enum dsc_clock_force_state {
552 DSC_CLK_FORCE_DEFAULT = 0,
553 DSC_CLK_FORCE_ENABLE,
554 DSC_CLK_FORCE_DISABLE,
555};
556
557struct dsc_preferred_settings {
558 enum dsc_clock_force_state dsc_force_enable;
559 uint32_t dsc_num_slices_v;
560 uint32_t dsc_num_slices_h;
561 uint32_t dsc_bits_per_pixel;
562 bool dsc_force_disable_passthrough;
563};
564
565struct amdgpu_dm_connector {
566
567 struct drm_connector base;
568 uint32_t connector_id;
569
570
571
572 struct edid *edid;
573
574
575 struct amdgpu_hpd hpd;
576
577
578 int num_modes;
579
580
581
582 struct dc_sink *dc_sink;
583 struct dc_link *dc_link;
584 struct dc_sink *dc_em_sink;
585
586
587 struct drm_dp_mst_topology_mgr mst_mgr;
588 struct amdgpu_dm_dp_aux dm_dp_aux;
589 struct drm_dp_mst_port *port;
590 struct amdgpu_dm_connector *mst_port;
591 struct drm_dp_aux *dsc_aux;
592
593
594 struct amdgpu_i2c_adapter *i2c;
595
596
597 int min_vfreq ;
598 int max_vfreq ;
599 int pixel_clock_mhz;
600
601
602 int audio_inst;
603
604 struct mutex hpd_lock;
605
606 bool fake_enable;
607#ifdef CONFIG_DEBUG_FS
608 uint32_t debugfs_dpcd_address;
609 uint32_t debugfs_dpcd_size;
610#endif
611 bool force_yuv420_output;
612 struct dsc_preferred_settings dsc_settings;
613 union dp_downstream_port_present mst_downstream_port_present;
614
615 struct drm_display_mode freesync_vid_base;
616
617 int psr_skip_count;
618};
619
620#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
621
622extern const struct amdgpu_ip_block_version dm_ip_block;
623
624struct dm_plane_state {
625 struct drm_plane_state base;
626 struct dc_plane_state *dc_state;
627};
628
629struct dm_crtc_state {
630 struct drm_crtc_state base;
631 struct dc_stream_state *stream;
632
633 bool cm_has_degamma;
634 bool cm_is_degamma_srgb;
635
636 bool mpo_requested;
637
638 int update_type;
639 int active_planes;
640
641 int crc_skip_count;
642
643 bool freesync_timing_changed;
644 bool freesync_vrr_info_changed;
645
646 bool dsc_force_changed;
647 bool vrr_supported;
648
649 bool force_dpms_off;
650 struct mod_freesync_config freesync_config;
651 struct dc_info_packet vrr_infopacket;
652
653 int abm_level;
654};
655
656#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
657
658struct dm_atomic_state {
659 struct drm_private_state base;
660
661 struct dc_state *context;
662};
663
664#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
665
666struct dm_connector_state {
667 struct drm_connector_state base;
668
669 enum amdgpu_rmx_type scaling;
670 uint8_t underscan_vborder;
671 uint8_t underscan_hborder;
672 bool underscan_enable;
673 bool freesync_capable;
674#ifdef CONFIG_DRM_AMD_DC_HDCP
675 bool update_hdcp;
676#endif
677 uint8_t abm_level;
678 int vcpi_slots;
679 uint64_t pbn;
680};
681
682struct amdgpu_hdmi_vsdb_info {
683 unsigned int amd_vsdb_version;
684 bool freesync_supported;
685 unsigned int min_refresh_rate_hz;
686 unsigned int max_refresh_rate_hz;
687};
688
689
690#define to_dm_connector_state(x)\
691 container_of((x), struct dm_connector_state, base)
692
693void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
694struct drm_connector_state *
695amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
696int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
697 struct drm_connector_state *state,
698 struct drm_property *property,
699 uint64_t val);
700
701int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
702 const struct drm_connector_state *state,
703 struct drm_property *property,
704 uint64_t *val);
705
706int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
707
708void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
709 struct amdgpu_dm_connector *aconnector,
710 int connector_type,
711 struct dc_link *link,
712 int link_index);
713
714enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
715 struct drm_display_mode *mode);
716
717void dm_restore_drm_connector_state(struct drm_device *dev,
718 struct drm_connector *connector);
719
720void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
721 struct edid *edid);
722
723void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
724
725#define MAX_COLOR_LUT_ENTRIES 4096
726
727#define MAX_COLOR_LEGACY_LUT_ENTRIES 256
728
729void amdgpu_dm_init_color_mod(void);
730int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
731int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
732int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
733 struct dc_plane_state *dc_plane_state);
734
735void amdgpu_dm_update_connector_after_detect(
736 struct amdgpu_dm_connector *aconnector);
737
738extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
739
740int amdgpu_dm_process_dmub_aux_transfer_sync(bool is_cmd_aux,
741 struct dc_context *ctx, unsigned int link_index,
742 void *payload, void *operation_result);
743
744bool check_seamless_boot_capability(struct amdgpu_device *adev);
745
746struct dc_stream_state *
747 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
748 const struct drm_display_mode *drm_mode,
749 const struct dm_connector_state *dm_state,
750 const struct dc_stream_state *old_stream);
751
752int dm_atomic_get_state(struct drm_atomic_state *state,
753 struct dm_atomic_state **dm_state);
754
755struct amdgpu_dm_connector *
756amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
757 struct drm_crtc *crtc);
758#endif
759