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8#include <linux/debugfs.h>
9#include <linux/delay.h>
10#include <linux/gpio/consumer.h>
11#include <linux/module.h>
12#include <linux/regulator/consumer.h>
13#include <linux/spi/spi.h>
14
15#include <drm/drm_connector.h>
16#include <drm/drm_damage_helper.h>
17#include <drm/drm_drv.h>
18#include <drm/drm_file.h>
19#include <drm/drm_format_helper.h>
20#include <drm/drm_fourcc.h>
21#include <drm/drm_gem.h>
22#include <drm/drm_gem_framebuffer_helper.h>
23#include <drm/drm_mipi_dbi.h>
24#include <drm/drm_modes.h>
25#include <drm/drm_probe_helper.h>
26#include <drm/drm_rect.h>
27#include <video/mipi_display.h>
28
29#define MIPI_DBI_MAX_SPI_READ_SPEED 2000000
30
31#define DCS_POWER_MODE_DISPLAY BIT(2)
32#define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3)
33#define DCS_POWER_MODE_SLEEP_MODE BIT(4)
34#define DCS_POWER_MODE_PARTIAL_MODE BIT(5)
35#define DCS_POWER_MODE_IDLE_MODE BIT(6)
36#define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7))
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67#define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
68({ \
69 if (!len) \
70 DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
71 else if (len <= 32) \
72 DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\
73 else \
74 DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
75})
76
77static const u8 mipi_dbi_dcs_read_commands[] = {
78 MIPI_DCS_GET_DISPLAY_ID,
79 MIPI_DCS_GET_RED_CHANNEL,
80 MIPI_DCS_GET_GREEN_CHANNEL,
81 MIPI_DCS_GET_BLUE_CHANNEL,
82 MIPI_DCS_GET_DISPLAY_STATUS,
83 MIPI_DCS_GET_POWER_MODE,
84 MIPI_DCS_GET_ADDRESS_MODE,
85 MIPI_DCS_GET_PIXEL_FORMAT,
86 MIPI_DCS_GET_DISPLAY_MODE,
87 MIPI_DCS_GET_SIGNAL_MODE,
88 MIPI_DCS_GET_DIAGNOSTIC_RESULT,
89 MIPI_DCS_READ_MEMORY_START,
90 MIPI_DCS_READ_MEMORY_CONTINUE,
91 MIPI_DCS_GET_SCANLINE,
92 MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
93 MIPI_DCS_GET_CONTROL_DISPLAY,
94 MIPI_DCS_GET_POWER_SAVE,
95 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
96 MIPI_DCS_READ_DDB_START,
97 MIPI_DCS_READ_DDB_CONTINUE,
98 0,
99};
100
101static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd)
102{
103 unsigned int i;
104
105 if (!dbi->read_commands)
106 return false;
107
108 for (i = 0; i < 0xff; i++) {
109 if (!dbi->read_commands[i])
110 return false;
111 if (cmd == dbi->read_commands[i])
112 return true;
113 }
114
115 return false;
116}
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128
129int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val)
130{
131 if (!dbi->read_commands)
132 return -EACCES;
133
134 if (!mipi_dbi_command_is_read(dbi, cmd))
135 return -EINVAL;
136
137 return mipi_dbi_command_buf(dbi, cmd, val, 1);
138}
139EXPORT_SYMBOL(mipi_dbi_command_read);
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151int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
152{
153 u8 *cmdbuf;
154 int ret;
155
156
157 cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL);
158 if (!cmdbuf)
159 return -ENOMEM;
160
161 mutex_lock(&dbi->cmdlock);
162 ret = dbi->command(dbi, cmdbuf, data, len);
163 mutex_unlock(&dbi->cmdlock);
164
165 kfree(cmdbuf);
166
167 return ret;
168}
169EXPORT_SYMBOL(mipi_dbi_command_buf);
170
171
172int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data,
173 size_t len)
174{
175 u8 *buf;
176 int ret;
177
178 buf = kmemdup(data, len, GFP_KERNEL);
179 if (!buf)
180 return -ENOMEM;
181
182 ret = mipi_dbi_command_buf(dbi, cmd, buf, len);
183
184 kfree(buf);
185
186 return ret;
187}
188EXPORT_SYMBOL(mipi_dbi_command_stackbuf);
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199
200int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
201 struct drm_rect *clip, bool swap)
202{
203 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
204 struct iosys_map map[DRM_FORMAT_MAX_PLANES];
205 struct iosys_map data[DRM_FORMAT_MAX_PLANES];
206 void *src;
207 int ret;
208
209 ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
210 if (ret)
211 return ret;
212
213 ret = drm_gem_fb_vmap(fb, map, data);
214 if (ret)
215 goto out_drm_gem_fb_end_cpu_access;
216 src = data[0].vaddr;
217
218 switch (fb->format->format) {
219 case DRM_FORMAT_RGB565:
220 if (swap)
221 drm_fb_swab(dst, 0, src, fb, clip, !gem->import_attach);
222 else
223 drm_fb_memcpy(dst, 0, src, fb, clip);
224 break;
225 case DRM_FORMAT_XRGB8888:
226 drm_fb_xrgb8888_to_rgb565(dst, 0, src, fb, clip, swap);
227 break;
228 default:
229 drm_err_once(fb->dev, "Format is not supported: %p4cc\n",
230 &fb->format->format);
231 ret = -EINVAL;
232 }
233
234 drm_gem_fb_vunmap(fb, map);
235out_drm_gem_fb_end_cpu_access:
236 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
237
238 return ret;
239}
240EXPORT_SYMBOL(mipi_dbi_buf_copy);
241
242static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev,
243 unsigned int xs, unsigned int xe,
244 unsigned int ys, unsigned int ye)
245{
246 struct mipi_dbi *dbi = &dbidev->dbi;
247
248 xs += dbidev->left_offset;
249 xe += dbidev->left_offset;
250 ys += dbidev->top_offset;
251 ye += dbidev->top_offset;
252
253 mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff,
254 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff);
255 mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff,
256 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff);
257}
258
259static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
260{
261 struct iosys_map map[DRM_FORMAT_MAX_PLANES];
262 struct iosys_map data[DRM_FORMAT_MAX_PLANES];
263 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
264 unsigned int height = rect->y2 - rect->y1;
265 unsigned int width = rect->x2 - rect->x1;
266 struct mipi_dbi *dbi = &dbidev->dbi;
267 bool swap = dbi->swap_bytes;
268 int idx, ret = 0;
269 bool full;
270 void *tr;
271
272 if (WARN_ON(!fb))
273 return;
274
275 if (!drm_dev_enter(fb->dev, &idx))
276 return;
277
278 ret = drm_gem_fb_vmap(fb, map, data);
279 if (ret)
280 goto err_drm_dev_exit;
281
282 full = width == fb->width && height == fb->height;
283
284 DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
285
286 if (!dbi->dc || !full || swap ||
287 fb->format->format == DRM_FORMAT_XRGB8888) {
288 tr = dbidev->tx_buf;
289 ret = mipi_dbi_buf_copy(dbidev->tx_buf, fb, rect, swap);
290 if (ret)
291 goto err_msg;
292 } else {
293 tr = data[0].vaddr;
294 }
295
296 mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1,
297 rect->y2 - 1);
298
299 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr,
300 width * height * 2);
301err_msg:
302 if (ret)
303 drm_err_once(fb->dev, "Failed to update display %d\n", ret);
304
305 drm_gem_fb_vunmap(fb, map);
306
307err_drm_dev_exit:
308 drm_dev_exit(idx);
309}
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318
319void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
320 struct drm_plane_state *old_state)
321{
322 struct drm_plane_state *state = pipe->plane.state;
323 struct drm_rect rect;
324
325 if (!pipe->crtc.state->active)
326 return;
327
328 if (drm_atomic_helper_damage_merged(old_state, state, &rect))
329 mipi_dbi_fb_dirty(state->fb, &rect);
330}
331EXPORT_SYMBOL(mipi_dbi_pipe_update);
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345
346void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
347 struct drm_crtc_state *crtc_state,
348 struct drm_plane_state *plane_state)
349{
350 struct drm_framebuffer *fb = plane_state->fb;
351 struct drm_rect rect = {
352 .x1 = 0,
353 .x2 = fb->width,
354 .y1 = 0,
355 .y2 = fb->height,
356 };
357 int idx;
358
359 if (!drm_dev_enter(&dbidev->drm, &idx))
360 return;
361
362 mipi_dbi_fb_dirty(fb, &rect);
363 backlight_enable(dbidev->backlight);
364
365 drm_dev_exit(idx);
366}
367EXPORT_SYMBOL(mipi_dbi_enable_flush);
368
369static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev)
370{
371 struct drm_device *drm = &dbidev->drm;
372 u16 height = drm->mode_config.min_height;
373 u16 width = drm->mode_config.min_width;
374 struct mipi_dbi *dbi = &dbidev->dbi;
375 size_t len = width * height * 2;
376 int idx;
377
378 if (!drm_dev_enter(drm, &idx))
379 return;
380
381 memset(dbidev->tx_buf, 0, len);
382
383 mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1);
384 mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
385 (u8 *)dbidev->tx_buf, len);
386
387 drm_dev_exit(idx);
388}
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397
398void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
399{
400 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
401
402 DRM_DEBUG_KMS("\n");
403
404 if (dbidev->backlight)
405 backlight_disable(dbidev->backlight);
406 else
407 mipi_dbi_blank(dbidev);
408
409 if (dbidev->regulator)
410 regulator_disable(dbidev->regulator);
411}
412EXPORT_SYMBOL(mipi_dbi_pipe_disable);
413
414static int mipi_dbi_connector_get_modes(struct drm_connector *connector)
415{
416 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev);
417 struct drm_display_mode *mode;
418
419 mode = drm_mode_duplicate(connector->dev, &dbidev->mode);
420 if (!mode) {
421 DRM_ERROR("Failed to duplicate mode\n");
422 return 0;
423 }
424
425 if (mode->name[0] == '\0')
426 drm_mode_set_name(mode);
427
428 mode->type |= DRM_MODE_TYPE_PREFERRED;
429 drm_mode_probed_add(connector, mode);
430
431 if (mode->width_mm) {
432 connector->display_info.width_mm = mode->width_mm;
433 connector->display_info.height_mm = mode->height_mm;
434 }
435
436 return 1;
437}
438
439static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = {
440 .get_modes = mipi_dbi_connector_get_modes,
441};
442
443static const struct drm_connector_funcs mipi_dbi_connector_funcs = {
444 .reset = drm_atomic_helper_connector_reset,
445 .fill_modes = drm_helper_probe_single_connector_modes,
446 .destroy = drm_connector_cleanup,
447 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
448 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
449};
450
451static int mipi_dbi_rotate_mode(struct drm_display_mode *mode,
452 unsigned int rotation)
453{
454 if (rotation == 0 || rotation == 180) {
455 return 0;
456 } else if (rotation == 90 || rotation == 270) {
457 swap(mode->hdisplay, mode->vdisplay);
458 swap(mode->hsync_start, mode->vsync_start);
459 swap(mode->hsync_end, mode->vsync_end);
460 swap(mode->htotal, mode->vtotal);
461 swap(mode->width_mm, mode->height_mm);
462 return 0;
463 } else {
464 return -EINVAL;
465 }
466}
467
468static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = {
469 .fb_create = drm_gem_fb_create_with_dirty,
470 .atomic_check = drm_atomic_helper_check,
471 .atomic_commit = drm_atomic_helper_commit,
472};
473
474static const uint32_t mipi_dbi_formats[] = {
475 DRM_FORMAT_RGB565,
476 DRM_FORMAT_XRGB8888,
477};
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502int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
503 const struct drm_simple_display_pipe_funcs *funcs,
504 const uint32_t *formats, unsigned int format_count,
505 const struct drm_display_mode *mode,
506 unsigned int rotation, size_t tx_buf_size)
507{
508 static const uint64_t modifiers[] = {
509 DRM_FORMAT_MOD_LINEAR,
510 DRM_FORMAT_MOD_INVALID
511 };
512 struct drm_device *drm = &dbidev->drm;
513 int ret;
514
515 if (!dbidev->dbi.command)
516 return -EINVAL;
517
518 ret = drmm_mode_config_init(drm);
519 if (ret)
520 return ret;
521
522 dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL);
523 if (!dbidev->tx_buf)
524 return -ENOMEM;
525
526 drm_mode_copy(&dbidev->mode, mode);
527 ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation);
528 if (ret) {
529 DRM_ERROR("Illegal rotation value %u\n", rotation);
530 return -EINVAL;
531 }
532
533 drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs);
534 ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs,
535 DRM_MODE_CONNECTOR_SPI);
536 if (ret)
537 return ret;
538
539 ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count,
540 modifiers, &dbidev->connector);
541 if (ret)
542 return ret;
543
544 drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane);
545
546 drm->mode_config.funcs = &mipi_dbi_mode_config_funcs;
547 drm->mode_config.min_width = dbidev->mode.hdisplay;
548 drm->mode_config.max_width = dbidev->mode.hdisplay;
549 drm->mode_config.min_height = dbidev->mode.vdisplay;
550 drm->mode_config.max_height = dbidev->mode.vdisplay;
551 dbidev->rotation = rotation;
552
553 DRM_DEBUG_KMS("rotation = %u\n", rotation);
554
555 return 0;
556}
557EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats);
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576int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
577 const struct drm_simple_display_pipe_funcs *funcs,
578 const struct drm_display_mode *mode, unsigned int rotation)
579{
580 size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16);
581
582 dbidev->drm.mode_config.preferred_depth = 16;
583
584 return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats,
585 ARRAY_SIZE(mipi_dbi_formats), mode,
586 rotation, bufsize);
587}
588EXPORT_SYMBOL(mipi_dbi_dev_init);
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595
596void mipi_dbi_hw_reset(struct mipi_dbi *dbi)
597{
598 if (!dbi->reset)
599 return;
600
601 gpiod_set_value_cansleep(dbi->reset, 0);
602 usleep_range(20, 1000);
603 gpiod_set_value_cansleep(dbi->reset, 1);
604 msleep(120);
605}
606EXPORT_SYMBOL(mipi_dbi_hw_reset);
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620bool mipi_dbi_display_is_on(struct mipi_dbi *dbi)
621{
622 u8 val;
623
624 if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val))
625 return false;
626
627 val &= ~DCS_POWER_MODE_RESERVED_MASK;
628
629
630 if (val != (DCS_POWER_MODE_DISPLAY |
631 DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
632 return false;
633
634 DRM_DEBUG_DRIVER("Display is ON\n");
635
636 return true;
637}
638EXPORT_SYMBOL(mipi_dbi_display_is_on);
639
640static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond)
641{
642 struct device *dev = dbidev->drm.dev;
643 struct mipi_dbi *dbi = &dbidev->dbi;
644 int ret;
645
646 if (dbidev->regulator) {
647 ret = regulator_enable(dbidev->regulator);
648 if (ret) {
649 DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret);
650 return ret;
651 }
652 }
653
654 if (cond && mipi_dbi_display_is_on(dbi))
655 return 1;
656
657 mipi_dbi_hw_reset(dbi);
658 ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET);
659 if (ret) {
660 DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret);
661 if (dbidev->regulator)
662 regulator_disable(dbidev->regulator);
663 return ret;
664 }
665
666
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669
670
671 if (dbi->reset)
672 usleep_range(5000, 20000);
673 else
674 msleep(120);
675
676 return 0;
677}
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689int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev)
690{
691 return mipi_dbi_poweron_reset_conditional(dbidev, false);
692}
693EXPORT_SYMBOL(mipi_dbi_poweron_reset);
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707int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev)
708{
709 return mipi_dbi_poweron_reset_conditional(dbidev, true);
710}
711EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset);
712
713#if IS_ENABLED(CONFIG_SPI)
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723
724u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
725{
726 if (len > 64)
727 return 0;
728
729 return min_t(u32, 10000000, spi->max_speed_hz);
730}
731EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
732
733static bool mipi_dbi_machine_little_endian(void)
734{
735#if defined(__LITTLE_ENDIAN)
736 return true;
737#else
738 return false;
739#endif
740}
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760static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,
761 const void *buf, size_t len,
762 unsigned int bpw)
763{
764 bool swap_bytes = (bpw == 16 && mipi_dbi_machine_little_endian());
765 size_t chunk, max_chunk = dbi->tx_buf9_len;
766 struct spi_device *spi = dbi->spi;
767 struct spi_transfer tr = {
768 .tx_buf = dbi->tx_buf9,
769 .bits_per_word = 8,
770 };
771 struct spi_message m;
772 const u8 *src = buf;
773 int i, ret;
774 u8 *dst;
775
776 if (drm_debug_enabled(DRM_UT_DRIVER))
777 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
778 __func__, dc, max_chunk);
779
780 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
781 spi_message_init_with_transfers(&m, &tr, 1);
782
783 if (!dc) {
784 if (WARN_ON_ONCE(len != 1))
785 return -EINVAL;
786
787
788 dst = dbi->tx_buf9;
789 memset(dst, 0, 9);
790 dst[8] = *src;
791 tr.len = 9;
792
793 return spi_sync(spi, &m);
794 }
795
796
797 max_chunk = max_chunk / 9 * 8;
798
799 max_chunk = min(max_chunk, len);
800
801 max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
802
803 while (len) {
804 size_t added = 0;
805
806 chunk = min(len, max_chunk);
807 len -= chunk;
808 dst = dbi->tx_buf9;
809
810 if (chunk < 8) {
811 u8 val, carry = 0;
812
813
814 memset(dst, 0, 9);
815
816 if (swap_bytes) {
817 for (i = 1; i < (chunk + 1); i++) {
818 val = src[1];
819 *dst++ = carry | BIT(8 - i) | (val >> i);
820 carry = val << (8 - i);
821 i++;
822 val = src[0];
823 *dst++ = carry | BIT(8 - i) | (val >> i);
824 carry = val << (8 - i);
825 src += 2;
826 }
827 *dst++ = carry;
828 } else {
829 for (i = 1; i < (chunk + 1); i++) {
830 val = *src++;
831 *dst++ = carry | BIT(8 - i) | (val >> i);
832 carry = val << (8 - i);
833 }
834 *dst++ = carry;
835 }
836
837 chunk = 8;
838 added = 1;
839 } else {
840 for (i = 0; i < chunk; i += 8) {
841 if (swap_bytes) {
842 *dst++ = BIT(7) | (src[1] >> 1);
843 *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
844 *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
845 *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
846 *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
847 *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
848 *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
849 *dst++ = (src[7] << 1) | BIT(0);
850 *dst++ = src[6];
851 } else {
852 *dst++ = BIT(7) | (src[0] >> 1);
853 *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
854 *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
855 *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
856 *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
857 *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
858 *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
859 *dst++ = (src[6] << 1) | BIT(0);
860 *dst++ = src[7];
861 }
862
863 src += 8;
864 added++;
865 }
866 }
867
868 tr.len = chunk + added;
869
870 ret = spi_sync(spi, &m);
871 if (ret)
872 return ret;
873 }
874
875 return 0;
876}
877
878static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,
879 const void *buf, size_t len,
880 unsigned int bpw)
881{
882 struct spi_device *spi = dbi->spi;
883 struct spi_transfer tr = {
884 .bits_per_word = 9,
885 };
886 const u16 *src16 = buf;
887 const u8 *src8 = buf;
888 struct spi_message m;
889 size_t max_chunk;
890 u16 *dst16;
891 int ret;
892
893 if (!spi_is_bpw_supported(spi, 9))
894 return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);
895
896 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
897 max_chunk = dbi->tx_buf9_len;
898 dst16 = dbi->tx_buf9;
899
900 if (drm_debug_enabled(DRM_UT_DRIVER))
901 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
902 __func__, dc, max_chunk);
903
904 max_chunk = min(max_chunk / 2, len);
905
906 spi_message_init_with_transfers(&m, &tr, 1);
907 tr.tx_buf = dst16;
908
909 while (len) {
910 size_t chunk = min(len, max_chunk);
911 unsigned int i;
912
913 if (bpw == 16 && mipi_dbi_machine_little_endian()) {
914 for (i = 0; i < (chunk * 2); i += 2) {
915 dst16[i] = *src16 >> 8;
916 dst16[i + 1] = *src16++ & 0xFF;
917 if (dc) {
918 dst16[i] |= 0x0100;
919 dst16[i + 1] |= 0x0100;
920 }
921 }
922 } else {
923 for (i = 0; i < chunk; i++) {
924 dst16[i] = *src8++;
925 if (dc)
926 dst16[i] |= 0x0100;
927 }
928 }
929
930 tr.len = chunk * 2;
931 len -= chunk;
932
933 ret = spi_sync(spi, &m);
934 if (ret)
935 return ret;
936 }
937
938 return 0;
939}
940
941static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd,
942 u8 *data, size_t len)
943{
944 struct spi_device *spi = dbi->spi;
945 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
946 spi->max_speed_hz / 2);
947 struct spi_transfer tr[2] = {
948 {
949 .speed_hz = speed_hz,
950 .bits_per_word = 9,
951 .tx_buf = dbi->tx_buf9,
952 .len = 2,
953 }, {
954 .speed_hz = speed_hz,
955 .bits_per_word = 8,
956 .len = len,
957 .rx_buf = data,
958 },
959 };
960 struct spi_message m;
961 u16 *dst16;
962 int ret;
963
964 if (!len)
965 return -EINVAL;
966
967 if (!spi_is_bpw_supported(spi, 9)) {
968
969
970
971
972 dev_err(&spi->dev,
973 "reading on host not supporting 9 bpw not yet implemented\n");
974 return -EOPNOTSUPP;
975 }
976
977
978
979
980
981
982 dst16 = dbi->tx_buf9;
983 dst16[0] = *cmd;
984
985 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
986 ret = spi_sync(spi, &m);
987
988 if (!ret)
989 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
990
991 return ret;
992}
993
994static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,
995 u8 *parameters, size_t num)
996{
997 unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8;
998 int ret;
999
1000 if (mipi_dbi_command_is_read(dbi, *cmd))
1001 return mipi_dbi_typec1_command_read(dbi, cmd, parameters, num);
1002
1003 MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num);
1004
1005 ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8);
1006 if (ret || !num)
1007 return ret;
1008
1009 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);
1010}
1011
1012
1013
1014static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd,
1015 u8 *data, size_t len)
1016{
1017 struct spi_device *spi = dbi->spi;
1018 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
1019 spi->max_speed_hz / 2);
1020 struct spi_transfer tr[2] = {
1021 {
1022 .speed_hz = speed_hz,
1023 .tx_buf = cmd,
1024 .len = 1,
1025 }, {
1026 .speed_hz = speed_hz,
1027 .len = len,
1028 },
1029 };
1030 struct spi_message m;
1031 u8 *buf;
1032 int ret;
1033
1034 if (!len)
1035 return -EINVAL;
1036
1037
1038
1039
1040
1041 if (*cmd == MIPI_DCS_GET_DISPLAY_ID ||
1042 *cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
1043 if (!(len == 3 || len == 4))
1044 return -EINVAL;
1045
1046 tr[1].len = len + 1;
1047 }
1048
1049 buf = kmalloc(tr[1].len, GFP_KERNEL);
1050 if (!buf)
1051 return -ENOMEM;
1052
1053 tr[1].rx_buf = buf;
1054 gpiod_set_value_cansleep(dbi->dc, 0);
1055
1056 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
1057 ret = spi_sync(spi, &m);
1058 if (ret)
1059 goto err_free;
1060
1061 if (tr[1].len == len) {
1062 memcpy(data, buf, len);
1063 } else {
1064 unsigned int i;
1065
1066 for (i = 0; i < len; i++)
1067 data[i] = (buf[i] << 1) | (buf[i + 1] >> 7);
1068 }
1069
1070 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
1071
1072err_free:
1073 kfree(buf);
1074
1075 return ret;
1076}
1077
1078static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd,
1079 u8 *par, size_t num)
1080{
1081 struct spi_device *spi = dbi->spi;
1082 unsigned int bpw = 8;
1083 u32 speed_hz;
1084 int ret;
1085
1086 if (mipi_dbi_command_is_read(dbi, *cmd))
1087 return mipi_dbi_typec3_command_read(dbi, cmd, par, num);
1088
1089 MIPI_DBI_DEBUG_COMMAND(*cmd, par, num);
1090
1091 gpiod_set_value_cansleep(dbi->dc, 0);
1092 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
1093 ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1);
1094 if (ret || !num)
1095 return ret;
1096
1097 if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes)
1098 bpw = 16;
1099
1100 gpiod_set_value_cansleep(dbi->dc, 1);
1101 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
1102
1103 return mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num);
1104}
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
1129 struct gpio_desc *dc)
1130{
1131 struct device *dev = &spi->dev;
1132 int ret;
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144 if (!dev->coherent_dma_mask) {
1145 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
1146 if (ret) {
1147 dev_warn(dev, "Failed to set dma mask %d\n", ret);
1148 return ret;
1149 }
1150 }
1151
1152 dbi->spi = spi;
1153 dbi->read_commands = mipi_dbi_dcs_read_commands;
1154
1155 if (dc) {
1156 dbi->command = mipi_dbi_typec3_command;
1157 dbi->dc = dc;
1158 if (mipi_dbi_machine_little_endian() && !spi_is_bpw_supported(spi, 16))
1159 dbi->swap_bytes = true;
1160 } else {
1161 dbi->command = mipi_dbi_typec1_command;
1162 dbi->tx_buf9_len = SZ_16K;
1163 dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL);
1164 if (!dbi->tx_buf9)
1165 return -ENOMEM;
1166 }
1167
1168 mutex_init(&dbi->cmdlock);
1169
1170 DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
1171
1172 return 0;
1173}
1174EXPORT_SYMBOL(mipi_dbi_spi_init);
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
1191 u8 bpw, const void *buf, size_t len)
1192{
1193 size_t max_chunk = spi_max_transfer_size(spi);
1194 struct spi_transfer tr = {
1195 .bits_per_word = bpw,
1196 .speed_hz = speed_hz,
1197 };
1198 struct spi_message m;
1199 size_t chunk;
1200 int ret;
1201
1202 spi_message_init_with_transfers(&m, &tr, 1);
1203
1204 while (len) {
1205 chunk = min(len, max_chunk);
1206
1207 tr.tx_buf = buf;
1208 tr.len = chunk;
1209 buf += chunk;
1210 len -= chunk;
1211
1212 ret = spi_sync(spi, &m);
1213 if (ret)
1214 return ret;
1215 }
1216
1217 return 0;
1218}
1219EXPORT_SYMBOL(mipi_dbi_spi_transfer);
1220
1221#endif
1222
1223#ifdef CONFIG_DEBUG_FS
1224
1225static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
1226 const char __user *ubuf,
1227 size_t count, loff_t *ppos)
1228{
1229 struct seq_file *m = file->private_data;
1230 struct mipi_dbi_dev *dbidev = m->private;
1231 u8 val, cmd = 0, parameters[64];
1232 char *buf, *pos, *token;
1233 int i, ret, idx;
1234
1235 if (!drm_dev_enter(&dbidev->drm, &idx))
1236 return -ENODEV;
1237
1238 buf = memdup_user_nul(ubuf, count);
1239 if (IS_ERR(buf)) {
1240 ret = PTR_ERR(buf);
1241 goto err_exit;
1242 }
1243
1244
1245 for (i = count - 1; i > 0; i--)
1246 if (isspace(buf[i]))
1247 buf[i] = '\0';
1248 else
1249 break;
1250 i = 0;
1251 pos = buf;
1252 while (pos) {
1253 token = strsep(&pos, " ");
1254 if (!token) {
1255 ret = -EINVAL;
1256 goto err_free;
1257 }
1258
1259 ret = kstrtou8(token, 16, &val);
1260 if (ret < 0)
1261 goto err_free;
1262
1263 if (token == buf)
1264 cmd = val;
1265 else
1266 parameters[i++] = val;
1267
1268 if (i == 64) {
1269 ret = -E2BIG;
1270 goto err_free;
1271 }
1272 }
1273
1274 ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i);
1275
1276err_free:
1277 kfree(buf);
1278err_exit:
1279 drm_dev_exit(idx);
1280
1281 return ret < 0 ? ret : count;
1282}
1283
1284static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
1285{
1286 struct mipi_dbi_dev *dbidev = m->private;
1287 struct mipi_dbi *dbi = &dbidev->dbi;
1288 u8 cmd, val[4];
1289 int ret, idx;
1290 size_t len;
1291
1292 if (!drm_dev_enter(&dbidev->drm, &idx))
1293 return -ENODEV;
1294
1295 for (cmd = 0; cmd < 255; cmd++) {
1296 if (!mipi_dbi_command_is_read(dbi, cmd))
1297 continue;
1298
1299 switch (cmd) {
1300 case MIPI_DCS_READ_MEMORY_START:
1301 case MIPI_DCS_READ_MEMORY_CONTINUE:
1302 len = 2;
1303 break;
1304 case MIPI_DCS_GET_DISPLAY_ID:
1305 len = 3;
1306 break;
1307 case MIPI_DCS_GET_DISPLAY_STATUS:
1308 len = 4;
1309 break;
1310 default:
1311 len = 1;
1312 break;
1313 }
1314
1315 seq_printf(m, "%02x: ", cmd);
1316 ret = mipi_dbi_command_buf(dbi, cmd, val, len);
1317 if (ret) {
1318 seq_puts(m, "XX\n");
1319 continue;
1320 }
1321 seq_printf(m, "%*phN\n", (int)len, val);
1322 }
1323
1324 drm_dev_exit(idx);
1325
1326 return 0;
1327}
1328
1329static int mipi_dbi_debugfs_command_open(struct inode *inode,
1330 struct file *file)
1331{
1332 return single_open(file, mipi_dbi_debugfs_command_show,
1333 inode->i_private);
1334}
1335
1336static const struct file_operations mipi_dbi_debugfs_command_fops = {
1337 .owner = THIS_MODULE,
1338 .open = mipi_dbi_debugfs_command_open,
1339 .read = seq_read,
1340 .llseek = seq_lseek,
1341 .release = single_release,
1342 .write = mipi_dbi_debugfs_command_write,
1343};
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354void mipi_dbi_debugfs_init(struct drm_minor *minor)
1355{
1356 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev);
1357 umode_t mode = S_IFREG | S_IWUSR;
1358
1359 if (dbidev->dbi.read_commands)
1360 mode |= S_IRUGO;
1361 debugfs_create_file("command", mode, minor->debugfs_root, dbidev,
1362 &mipi_dbi_debugfs_command_fops);
1363}
1364EXPORT_SYMBOL(mipi_dbi_debugfs_init);
1365
1366#endif
1367
1368MODULE_LICENSE("GPL");
1369