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11#include <drm/drm_drv.h>
12#include <drm/drm_vblank.h>
13
14#include "power.h"
15#include "psb_drv.h"
16#include "psb_intel_reg.h"
17#include "psb_irq.h"
18#include "psb_reg.h"
19
20
21
22
23
24static inline u32
25psb_pipestat(int pipe)
26{
27 if (pipe == 0)
28 return PIPEASTAT;
29 if (pipe == 1)
30 return PIPEBSTAT;
31 if (pipe == 2)
32 return PIPECSTAT;
33 BUG();
34}
35
36static inline u32
37mid_pipe_event(int pipe)
38{
39 if (pipe == 0)
40 return _PSB_PIPEA_EVENT_FLAG;
41 if (pipe == 1)
42 return _MDFLD_PIPEB_EVENT_FLAG;
43 if (pipe == 2)
44 return _MDFLD_PIPEC_EVENT_FLAG;
45 BUG();
46}
47
48static inline u32
49mid_pipe_vsync(int pipe)
50{
51 if (pipe == 0)
52 return _PSB_VSYNC_PIPEA_FLAG;
53 if (pipe == 1)
54 return _PSB_VSYNC_PIPEB_FLAG;
55 if (pipe == 2)
56 return _MDFLD_PIPEC_VBLANK_FLAG;
57 BUG();
58}
59
60static inline u32
61mid_pipeconf(int pipe)
62{
63 if (pipe == 0)
64 return PIPEACONF;
65 if (pipe == 1)
66 return PIPEBCONF;
67 if (pipe == 2)
68 return PIPECCONF;
69 BUG();
70}
71
72void
73psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
74{
75 if ((dev_priv->pipestat[pipe] & mask) != mask) {
76 u32 reg = psb_pipestat(pipe);
77 dev_priv->pipestat[pipe] |= mask;
78
79 if (gma_power_begin(&dev_priv->dev, false)) {
80 u32 writeVal = PSB_RVDC32(reg);
81 writeVal |= (mask | (mask >> 16));
82 PSB_WVDC32(writeVal, reg);
83 (void) PSB_RVDC32(reg);
84 gma_power_end(&dev_priv->dev);
85 }
86 }
87}
88
89void
90psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
91{
92 if ((dev_priv->pipestat[pipe] & mask) != 0) {
93 u32 reg = psb_pipestat(pipe);
94 dev_priv->pipestat[pipe] &= ~mask;
95 if (gma_power_begin(&dev_priv->dev, false)) {
96 u32 writeVal = PSB_RVDC32(reg);
97 writeVal &= ~mask;
98 PSB_WVDC32(writeVal, reg);
99 (void) PSB_RVDC32(reg);
100 gma_power_end(&dev_priv->dev);
101 }
102 }
103}
104
105
106
107
108static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
109{
110 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
111
112 uint32_t pipe_stat_val = 0;
113 uint32_t pipe_stat_reg = psb_pipestat(pipe);
114 uint32_t pipe_enable = dev_priv->pipestat[pipe];
115 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
116 uint32_t pipe_clear;
117 uint32_t i = 0;
118
119 spin_lock(&dev_priv->irqmask_lock);
120
121 pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
122 pipe_stat_val &= pipe_enable | pipe_status;
123 pipe_stat_val &= pipe_stat_val >> 16;
124
125 spin_unlock(&dev_priv->irqmask_lock);
126
127
128
129 for (i = 0; i < 0xffff; i++) {
130 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
131 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
132
133 if (pipe_clear == 0)
134 break;
135 }
136
137 if (pipe_clear)
138 dev_err(dev->dev,
139 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
140 __func__, pipe, PSB_RVDC32(pipe_stat_reg));
141
142 if (pipe_stat_val & PIPE_VBLANK_STATUS) {
143 struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);
144 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
145 unsigned long flags;
146
147 drm_handle_vblank(dev, pipe);
148
149 spin_lock_irqsave(&dev->event_lock, flags);
150 if (gma_crtc->page_flip_event) {
151 drm_crtc_send_vblank_event(crtc,
152 gma_crtc->page_flip_event);
153 gma_crtc->page_flip_event = NULL;
154 drm_crtc_vblank_put(crtc);
155 }
156 spin_unlock_irqrestore(&dev->event_lock, flags);
157 }
158}
159
160
161
162
163static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
164{
165 if (vdc_stat & _PSB_IRQ_ASLE)
166 psb_intel_opregion_asle_intr(dev);
167
168 if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
169 mid_pipe_event_handler(dev, 0);
170
171 if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
172 mid_pipe_event_handler(dev, 1);
173}
174
175
176
177
178static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2)
179{
180 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
181 u32 val, addr;
182
183 if (stat_1 & _PSB_CE_TWOD_COMPLETE)
184 val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
185
186 if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) {
187 val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
188 addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
189 if (val) {
190 if (val & _PSB_CBI_STAT_PF_N_RW)
191 DRM_ERROR("SGX MMU page fault:");
192 else
193 DRM_ERROR("SGX MMU read / write protection fault:");
194
195 if (val & _PSB_CBI_STAT_FAULT_CACHE)
196 DRM_ERROR("\tCache requestor");
197 if (val & _PSB_CBI_STAT_FAULT_TA)
198 DRM_ERROR("\tTA requestor");
199 if (val & _PSB_CBI_STAT_FAULT_VDM)
200 DRM_ERROR("\tVDM requestor");
201 if (val & _PSB_CBI_STAT_FAULT_2D)
202 DRM_ERROR("\t2D requestor");
203 if (val & _PSB_CBI_STAT_FAULT_PBE)
204 DRM_ERROR("\tPBE requestor");
205 if (val & _PSB_CBI_STAT_FAULT_TSP)
206 DRM_ERROR("\tTSP requestor");
207 if (val & _PSB_CBI_STAT_FAULT_ISP)
208 DRM_ERROR("\tISP requestor");
209 if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
210 DRM_ERROR("\tUSSEPDS requestor");
211 if (val & _PSB_CBI_STAT_FAULT_HOST)
212 DRM_ERROR("\tHost requestor");
213
214 DRM_ERROR("\tMMU failing address is 0x%08x.\n",
215 (unsigned int)addr);
216 }
217 }
218
219
220 PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR);
221 PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2);
222 PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
223}
224
225static irqreturn_t psb_irq_handler(int irq, void *arg)
226{
227 struct drm_device *dev = arg;
228 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
229 uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
230 u32 sgx_stat_1, sgx_stat_2;
231 int handled = 0;
232
233 spin_lock(&dev_priv->irqmask_lock);
234
235 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
236
237 if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE))
238 dsp_int = 1;
239
240 if (vdc_stat & _PSB_IRQ_SGX_FLAG)
241 sgx_int = 1;
242 if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC)
243 hotplug_int = 1;
244
245 vdc_stat &= dev_priv->vdc_irq_mask;
246 spin_unlock(&dev_priv->irqmask_lock);
247
248 if (dsp_int && gma_power_is_on(dev)) {
249 psb_vdc_interrupt(dev, vdc_stat);
250 handled = 1;
251 }
252
253 if (sgx_int) {
254 sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
255 sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
256 psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2);
257 handled = 1;
258 }
259
260
261
262 if (hotplug_int && dev_priv->ops->hotplug) {
263 handled = dev_priv->ops->hotplug(dev);
264 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
265 }
266
267 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
268 (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
269 rmb();
270
271 if (!handled)
272 return IRQ_NONE;
273
274 return IRQ_HANDLED;
275}
276
277void psb_irq_preinstall(struct drm_device *dev)
278{
279 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
280 unsigned long irqflags;
281
282 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
283
284 if (gma_power_is_on(dev)) {
285 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
286 PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
287 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
288 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
289 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
290 }
291 if (dev->vblank[0].enabled)
292 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
293 if (dev->vblank[1].enabled)
294 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
295
296
297 if (dev_priv->ops->hotplug)
298 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
299 dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;
300
301
302 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
303 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
304}
305
306void psb_irq_postinstall(struct drm_device *dev)
307{
308 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
309 unsigned long irqflags;
310 unsigned int i;
311
312 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
313
314
315 PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2);
316 PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE);
317 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
318
319
320 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
321 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
322
323 for (i = 0; i < dev->num_crtcs; ++i) {
324 if (dev->vblank[i].enabled)
325 psb_enable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
326 else
327 psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
328 }
329
330 if (dev_priv->ops->hotplug_enable)
331 dev_priv->ops->hotplug_enable(dev, true);
332
333 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
334}
335
336int psb_irq_install(struct drm_device *dev, unsigned int irq)
337{
338 int ret;
339
340 if (irq == IRQ_NOTCONNECTED)
341 return -ENOTCONN;
342
343 psb_irq_preinstall(dev);
344
345
346 ret = request_irq(irq, psb_irq_handler, IRQF_SHARED, dev->driver->name, dev);
347 if (ret)
348 return ret;
349
350 psb_irq_postinstall(dev);
351
352 return 0;
353}
354
355void psb_irq_uninstall(struct drm_device *dev)
356{
357 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
358 struct pci_dev *pdev = to_pci_dev(dev->dev);
359 unsigned long irqflags;
360 unsigned int i;
361
362 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
363
364 if (dev_priv->ops->hotplug_enable)
365 dev_priv->ops->hotplug_enable(dev, false);
366
367 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
368
369 for (i = 0; i < dev->num_crtcs; ++i) {
370 if (dev->vblank[i].enabled)
371 psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
372 }
373
374 dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
375 _PSB_IRQ_MSVDX_FLAG |
376 _LNC_IRQ_TOPAZ_FLAG;
377
378
379 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
380 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
381
382 wmb();
383
384
385 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
386 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
387
388 free_irq(pdev->irq, dev);
389}
390
391
392
393
394int psb_enable_vblank(struct drm_crtc *crtc)
395{
396 struct drm_device *dev = crtc->dev;
397 unsigned int pipe = crtc->index;
398 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
399 unsigned long irqflags;
400 uint32_t reg_val = 0;
401 uint32_t pipeconf_reg = mid_pipeconf(pipe);
402
403 if (gma_power_begin(dev, false)) {
404 reg_val = REG_READ(pipeconf_reg);
405 gma_power_end(dev);
406 }
407
408 if (!(reg_val & PIPEACONF_ENABLE))
409 return -EINVAL;
410
411 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
412
413 if (pipe == 0)
414 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
415 else if (pipe == 1)
416 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
417
418 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
419 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
420 psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
421
422 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
423
424 return 0;
425}
426
427
428
429
430void psb_disable_vblank(struct drm_crtc *crtc)
431{
432 struct drm_device *dev = crtc->dev;
433 unsigned int pipe = crtc->index;
434 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
435 unsigned long irqflags;
436
437 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
438
439 if (pipe == 0)
440 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
441 else if (pipe == 1)
442 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
443
444 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
445 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
446 psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
447
448 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
449}
450
451
452
453
454u32 psb_get_vblank_counter(struct drm_crtc *crtc)
455{
456 struct drm_device *dev = crtc->dev;
457 unsigned int pipe = crtc->index;
458 uint32_t high_frame = PIPEAFRAMEHIGH;
459 uint32_t low_frame = PIPEAFRAMEPIXEL;
460 uint32_t pipeconf_reg = PIPEACONF;
461 uint32_t reg_val = 0;
462 uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
463
464 switch (pipe) {
465 case 0:
466 break;
467 case 1:
468 high_frame = PIPEBFRAMEHIGH;
469 low_frame = PIPEBFRAMEPIXEL;
470 pipeconf_reg = PIPEBCONF;
471 break;
472 case 2:
473 high_frame = PIPECFRAMEHIGH;
474 low_frame = PIPECFRAMEPIXEL;
475 pipeconf_reg = PIPECCONF;
476 break;
477 default:
478 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
479 return 0;
480 }
481
482 if (!gma_power_begin(dev, false))
483 return 0;
484
485 reg_val = REG_READ(pipeconf_reg);
486
487 if (!(reg_val & PIPEACONF_ENABLE)) {
488 dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n",
489 pipe);
490 goto psb_get_vblank_counter_exit;
491 }
492
493
494
495
496
497
498 do {
499 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
500 PIPE_FRAME_HIGH_SHIFT);
501 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
502 PIPE_FRAME_LOW_SHIFT);
503 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
504 PIPE_FRAME_HIGH_SHIFT);
505 } while (high1 != high2);
506
507 count = (high1 << 8) | low;
508
509psb_get_vblank_counter_exit:
510
511 gma_power_end(dev);
512
513 return count;
514}
515
516
