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9#include <drm/dp/drm_dp_helper.h>
10#include <drm/dp/drm_dp_mst_helper.h>
11#include <drm/drm_hdcp.h>
12#include <drm/drm_print.h>
13
14#include "intel_ddi.h"
15#include "intel_de.h"
16#include "intel_display_types.h"
17#include "intel_dp.h"
18#include "intel_dp_hdcp.h"
19#include "intel_hdcp.h"
20
21static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
22{
23 u32 stream_enc_mask;
24
25 switch (cpu_transcoder) {
26 case TRANSCODER_A:
27 stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
28 break;
29 case TRANSCODER_B:
30 stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
31 break;
32 case TRANSCODER_C:
33 stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
34 break;
35 case TRANSCODER_D:
36 stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
37 break;
38 default:
39 stream_enc_mask = 0;
40 }
41
42 return stream_enc_mask;
43}
44
45static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
46{
47 long ret;
48
49#define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
50 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
51 msecs_to_jiffies(timeout));
52
53 if (!ret)
54 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
55}
56
57static
58int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
59 u8 *an)
60{
61 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
62 u8 aksv[DRM_HDCP_KSV_LEN] = {};
63 ssize_t dpcd_ret;
64
65
66 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,
67 an, DRM_HDCP_AN_LEN);
68 if (dpcd_ret != DRM_HDCP_AN_LEN) {
69 drm_dbg_kms(&i915->drm,
70 "Failed to write An over DP/AUX (%zd)\n",
71 dpcd_ret);
72 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
73 }
74
75
76
77
78
79
80
81
82 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,
83 aksv, DRM_HDCP_KSV_LEN);
84 if (dpcd_ret != DRM_HDCP_KSV_LEN) {
85 drm_dbg_kms(&i915->drm,
86 "Failed to write Aksv over DP/AUX (%zd)\n",
87 dpcd_ret);
88 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
89 }
90 return 0;
91}
92
93static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
94 u8 *bksv)
95{
96 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
97 ssize_t ret;
98
99 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
100 DRM_HDCP_KSV_LEN);
101 if (ret != DRM_HDCP_KSV_LEN) {
102 drm_dbg_kms(&i915->drm,
103 "Read Bksv from DP/AUX failed (%zd)\n", ret);
104 return ret >= 0 ? -EIO : ret;
105 }
106 return 0;
107}
108
109static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
110 u8 *bstatus)
111{
112 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
113 ssize_t ret;
114
115
116
117
118
119
120 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO,
121 bstatus, DRM_HDCP_BSTATUS_LEN);
122 if (ret != DRM_HDCP_BSTATUS_LEN) {
123 drm_dbg_kms(&i915->drm,
124 "Read bstatus from DP/AUX failed (%zd)\n", ret);
125 return ret >= 0 ? -EIO : ret;
126 }
127 return 0;
128}
129
130static
131int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port,
132 u8 *bcaps)
133{
134 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
135 ssize_t ret;
136
137 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
138 bcaps, 1);
139 if (ret != 1) {
140 drm_dbg_kms(&i915->drm,
141 "Read bcaps from DP/AUX failed (%zd)\n", ret);
142 return ret >= 0 ? -EIO : ret;
143 }
144
145 return 0;
146}
147
148static
149int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
150 bool *repeater_present)
151{
152 ssize_t ret;
153 u8 bcaps;
154
155 ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
156 if (ret)
157 return ret;
158
159 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
160 return 0;
161}
162
163static
164int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
165 u8 *ri_prime)
166{
167 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
168 ssize_t ret;
169
170 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
171 ri_prime, DRM_HDCP_RI_LEN);
172 if (ret != DRM_HDCP_RI_LEN) {
173 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
174 ret);
175 return ret >= 0 ? -EIO : ret;
176 }
177 return 0;
178}
179
180static
181int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
182 bool *ksv_ready)
183{
184 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
185 ssize_t ret;
186 u8 bstatus;
187
188 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
189 &bstatus, 1);
190 if (ret != 1) {
191 drm_dbg_kms(&i915->drm,
192 "Read bstatus from DP/AUX failed (%zd)\n", ret);
193 return ret >= 0 ? -EIO : ret;
194 }
195 *ksv_ready = bstatus & DP_BSTATUS_READY;
196 return 0;
197}
198
199static
200int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
201 int num_downstream, u8 *ksv_fifo)
202{
203 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
204 ssize_t ret;
205 int i;
206
207
208 for (i = 0; i < num_downstream; i += 3) {
209 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
210 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
211 DP_AUX_HDCP_KSV_FIFO,
212 ksv_fifo + i * DRM_HDCP_KSV_LEN,
213 len);
214 if (ret != len) {
215 drm_dbg_kms(&i915->drm,
216 "Read ksv[%d] from DP/AUX failed (%zd)\n",
217 i, ret);
218 return ret >= 0 ? -EIO : ret;
219 }
220 }
221 return 0;
222}
223
224static
225int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
226 int i, u32 *part)
227{
228 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
229 ssize_t ret;
230
231 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
232 return -EINVAL;
233
234 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
235 DP_AUX_HDCP_V_PRIME(i), part,
236 DRM_HDCP_V_PRIME_PART_LEN);
237 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
238 drm_dbg_kms(&i915->drm,
239 "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
240 return ret >= 0 ? -EIO : ret;
241 }
242 return 0;
243}
244
245static
246int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
247 enum transcoder cpu_transcoder,
248 bool enable)
249{
250
251 return 0;
252}
253
254static
255bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
256 struct intel_connector *connector)
257{
258 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
259 ssize_t ret;
260 u8 bstatus;
261
262 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
263 &bstatus, 1);
264 if (ret != 1) {
265 drm_dbg_kms(&i915->drm,
266 "Read bstatus from DP/AUX failed (%zd)\n", ret);
267 return false;
268 }
269
270 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
271}
272
273static
274int intel_dp_hdcp_capable(struct intel_digital_port *dig_port,
275 bool *hdcp_capable)
276{
277 ssize_t ret;
278 u8 bcaps;
279
280 ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
281 if (ret)
282 return ret;
283
284 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
285 return 0;
286}
287
288struct hdcp2_dp_errata_stream_type {
289 u8 msg_id;
290 u8 stream_type;
291} __packed;
292
293struct hdcp2_dp_msg_data {
294 u8 msg_id;
295 u32 offset;
296 bool msg_detectable;
297 u32 timeout;
298 u32 timeout2;
299
300 u32 msg_read_timeout;
301};
302
303static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
304 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0, 0},
305 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
306 false, HDCP_2_2_CERT_TIMEOUT_MS, 0, HDCP_2_2_DP_CERT_READ_TIMEOUT_MS},
307 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
308 false, 0, 0, 0 },
309 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
310 false, 0, 0, 0 },
311 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
312 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
313 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS, HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS},
314 { HDCP_2_2_AKE_SEND_PAIRING_INFO,
315 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
316 HDCP_2_2_PAIRING_TIMEOUT_MS, 0, HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS },
317 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0, 0 },
318 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
319 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0, 0 },
320 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
321 0, 0, 0 },
322 { HDCP_2_2_REP_SEND_RECVID_LIST,
323 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
324 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0, 0 },
325 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
326 0, 0, 0 },
327 { HDCP_2_2_REP_STREAM_MANAGE,
328 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
329 0, 0, 0},
330 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
331 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0, 0 },
332
333#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
334 { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
335 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
336 0, 0 },
337};
338
339static int
340intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
341 u8 *rx_status)
342{
343 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
344 ssize_t ret;
345
346 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
347 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
348 HDCP_2_2_DP_RXSTATUS_LEN);
349 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
350 drm_dbg_kms(&i915->drm,
351 "Read bstatus from DP/AUX failed (%zd)\n", ret);
352 return ret >= 0 ? -EIO : ret;
353 }
354
355 return 0;
356}
357
358static
359int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
360 u8 msg_id, bool *msg_ready)
361{
362 u8 rx_status;
363 int ret;
364
365 *msg_ready = false;
366 ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
367 if (ret < 0)
368 return ret;
369
370 switch (msg_id) {
371 case HDCP_2_2_AKE_SEND_HPRIME:
372 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
373 *msg_ready = true;
374 break;
375 case HDCP_2_2_AKE_SEND_PAIRING_INFO:
376 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
377 *msg_ready = true;
378 break;
379 case HDCP_2_2_REP_SEND_RECVID_LIST:
380 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
381 *msg_ready = true;
382 break;
383 default:
384 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
385 return -EINVAL;
386 }
387
388 return 0;
389}
390
391static ssize_t
392intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
393 const struct hdcp2_dp_msg_data *hdcp2_msg_data)
394{
395 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
396 struct intel_dp *dp = &dig_port->dp;
397 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
398 u8 msg_id = hdcp2_msg_data->msg_id;
399 int ret, timeout;
400 bool msg_ready = false;
401
402 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
403 timeout = hdcp2_msg_data->timeout2;
404 else
405 timeout = hdcp2_msg_data->timeout;
406
407
408
409
410
411 if (!hdcp2_msg_data->msg_detectable) {
412 mdelay(timeout);
413 ret = 0;
414 } else {
415
416
417
418
419 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
420 ret = hdcp2_detect_msg_availability(dig_port,
421 msg_id, &msg_ready);
422 if (!msg_ready)
423 ret = -ETIMEDOUT;
424 }
425
426 if (ret)
427 drm_dbg_kms(&i915->drm,
428 "msg_id %d, ret %d, timeout(mSec): %d\n",
429 hdcp2_msg_data->msg_id, ret, timeout);
430
431 return ret;
432}
433
434static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
435{
436 int i;
437
438 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
439 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
440 return &hdcp2_dp_msg_data[i];
441
442 return NULL;
443}
444
445static
446int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port,
447 void *buf, size_t size)
448{
449 unsigned int offset;
450 u8 *byte = buf;
451 ssize_t ret, bytes_to_write, len;
452 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
453
454 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
455 if (!hdcp2_msg_data)
456 return -EINVAL;
457
458 offset = hdcp2_msg_data->offset;
459
460
461 bytes_to_write = size - 1;
462 byte++;
463
464 while (bytes_to_write) {
465 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
466 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
467
468 ret = drm_dp_dpcd_write(&dig_port->dp.aux,
469 offset, (void *)byte, len);
470 if (ret < 0)
471 return ret;
472
473 bytes_to_write -= ret;
474 byte += ret;
475 offset += ret;
476 }
477
478 return size;
479}
480
481static
482ssize_t get_receiver_id_list_rx_info(struct intel_digital_port *dig_port, u32 *dev_cnt, u8 *byte)
483{
484 ssize_t ret;
485 u8 *rx_info = byte;
486
487 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
488 DP_HDCP_2_2_REG_RXINFO_OFFSET,
489 (void *)rx_info, HDCP_2_2_RXINFO_LEN);
490 if (ret != HDCP_2_2_RXINFO_LEN)
491 return ret >= 0 ? -EIO : ret;
492
493 *dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
494 HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
495
496 if (*dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
497 *dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
498
499 return ret;
500}
501
502static
503int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port,
504 u8 msg_id, void *buf, size_t size)
505{
506 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
507 struct intel_dp *dp = &dig_port->dp;
508 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
509 unsigned int offset;
510 u8 *byte = buf;
511 ssize_t ret, bytes_to_recv, len;
512 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
513 ktime_t msg_end = ktime_set(0, 0);
514 bool msg_expired;
515 u32 dev_cnt;
516
517 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
518 if (!hdcp2_msg_data)
519 return -EINVAL;
520 offset = hdcp2_msg_data->offset;
521
522 ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data);
523 if (ret < 0)
524 return ret;
525
526 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
527
528
529 byte++;
530
531 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
532 ret = get_receiver_id_list_rx_info(dig_port, &dev_cnt, byte);
533 if (ret < 0)
534 return ret;
535
536 byte += ret;
537 size = sizeof(struct hdcp2_rep_send_receiverid_list) -
538 HDCP_2_2_RXINFO_LEN - HDCP_2_2_RECEIVER_IDS_MAX_LEN +
539 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
540 offset += HDCP_2_2_RXINFO_LEN;
541 }
542
543 bytes_to_recv = size - 1;
544
545 while (bytes_to_recv) {
546 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
547 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
548
549
550 if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout > 0)
551 msg_end = ktime_add_ms(ktime_get_raw(),
552 hdcp2_msg_data->msg_read_timeout);
553
554 ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset,
555 (void *)byte, len);
556 if (ret < 0) {
557 drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
558 msg_id, ret);
559 return ret;
560 }
561
562 bytes_to_recv -= ret;
563 byte += ret;
564 offset += ret;
565 }
566
567 if (hdcp2_msg_data->msg_read_timeout > 0) {
568 msg_expired = ktime_after(ktime_get_raw(), msg_end);
569 if (msg_expired) {
570 drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n",
571 msg_id, hdcp2_msg_data->msg_read_timeout);
572 return -ETIMEDOUT;
573 }
574 }
575
576 byte = buf;
577 *byte = msg_id;
578
579 return size;
580}
581
582static
583int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
584 bool is_repeater, u8 content_type)
585{
586 int ret;
587 struct hdcp2_dp_errata_stream_type stream_type_msg;
588
589 if (is_repeater)
590 return 0;
591
592
593
594
595
596
597
598
599 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
600 stream_type_msg.stream_type = content_type;
601
602 ret = intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg,
603 sizeof(stream_type_msg));
604
605 return ret < 0 ? ret : 0;
606
607}
608
609static
610int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
611 struct intel_connector *connector)
612{
613 u8 rx_status;
614 int ret;
615
616 ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
617 if (ret)
618 return ret;
619
620 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
621 ret = HDCP_REAUTH_REQUEST;
622 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
623 ret = HDCP_LINK_INTEGRITY_FAILURE;
624 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
625 ret = HDCP_TOPOLOGY_CHANGE;
626
627 return ret;
628}
629
630static
631int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port,
632 bool *capable)
633{
634 u8 rx_caps[3];
635 int ret;
636
637 *capable = false;
638 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
639 DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
640 rx_caps, HDCP_2_2_RXCAPS_LEN);
641 if (ret != HDCP_2_2_RXCAPS_LEN)
642 return ret >= 0 ? -EIO : ret;
643
644 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
645 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
646 *capable = true;
647
648 return 0;
649}
650
651static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
652 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
653 .read_bksv = intel_dp_hdcp_read_bksv,
654 .read_bstatus = intel_dp_hdcp_read_bstatus,
655 .repeater_present = intel_dp_hdcp_repeater_present,
656 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
657 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
658 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
659 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
660 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
661 .check_link = intel_dp_hdcp_check_link,
662 .hdcp_capable = intel_dp_hdcp_capable,
663 .write_2_2_msg = intel_dp_hdcp2_write_msg,
664 .read_2_2_msg = intel_dp_hdcp2_read_msg,
665 .config_stream_type = intel_dp_hdcp2_config_stream_type,
666 .check_2_2_link = intel_dp_hdcp2_check_link,
667 .hdcp_2_2_capable = intel_dp_hdcp2_capable,
668 .protocol = HDCP_PROTOCOL_DP,
669};
670
671static int
672intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
673 bool enable)
674{
675 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
676 struct drm_i915_private *i915 = to_i915(connector->base.dev);
677 struct intel_hdcp *hdcp = &connector->hdcp;
678 int ret;
679
680 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
681 hdcp->stream_transcoder, enable,
682 TRANS_DDI_HDCP_SELECT);
683 if (ret)
684 drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
685 enable ? "Enable" : "Disable", ret);
686 return ret;
687}
688
689static int
690intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
691 bool enable)
692{
693 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
694 struct drm_i915_private *i915 = to_i915(connector->base.dev);
695 struct intel_hdcp *hdcp = &connector->hdcp;
696 enum port port = dig_port->base.port;
697 enum transcoder cpu_transcoder = hdcp->stream_transcoder;
698 u32 stream_enc_status;
699 int ret;
700
701 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
702 if (ret)
703 return ret;
704
705 stream_enc_status = transcoder_to_stream_enc_status(cpu_transcoder);
706 if (!stream_enc_status)
707 return -EINVAL;
708
709
710 if (intel_de_wait_for_register(i915,
711 HDCP_STATUS(i915, cpu_transcoder, port),
712 stream_enc_status,
713 enable ? stream_enc_status : 0,
714 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
715 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
716 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
717 return -ETIMEDOUT;
718 }
719
720 return 0;
721}
722
723static int
724intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
725 bool enable)
726{
727 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
728 struct drm_i915_private *i915 = to_i915(connector->base.dev);
729 struct hdcp_port_data *data = &dig_port->hdcp_port_data;
730 struct intel_hdcp *hdcp = &connector->hdcp;
731 enum transcoder cpu_transcoder = hdcp->stream_transcoder;
732 enum pipe pipe = (enum pipe)cpu_transcoder;
733 enum port port = dig_port->base.port;
734 int ret;
735
736 drm_WARN_ON(&i915->drm, enable &&
737 !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
738 & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
739
740 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
741 if (ret)
742 return ret;
743
744
745 if (intel_de_wait_for_register(i915,
746 HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe),
747 STREAM_ENCRYPTION_STATUS,
748 enable ? STREAM_ENCRYPTION_STATUS : 0,
749 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
750 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
751 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
752 return -ETIMEDOUT;
753 }
754
755 return 0;
756}
757
758static
759int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
760 struct intel_connector *connector)
761{
762 struct intel_hdcp *hdcp = &connector->hdcp;
763 int ret;
764
765
766
767
768
769
770
771 if (hdcp->is_repeater) {
772 ret = intel_dp_hdcp2_check_link(dig_port, connector);
773 if (ret)
774 return ret;
775 }
776
777 return 0;
778}
779
780static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
781 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
782 .read_bksv = intel_dp_hdcp_read_bksv,
783 .read_bstatus = intel_dp_hdcp_read_bstatus,
784 .repeater_present = intel_dp_hdcp_repeater_present,
785 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
786 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
787 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
788 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
789 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
790 .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
791 .check_link = intel_dp_hdcp_check_link,
792 .hdcp_capable = intel_dp_hdcp_capable,
793 .write_2_2_msg = intel_dp_hdcp2_write_msg,
794 .read_2_2_msg = intel_dp_hdcp2_read_msg,
795 .config_stream_type = intel_dp_hdcp2_config_stream_type,
796 .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
797 .check_2_2_link = intel_dp_mst_hdcp2_check_link,
798 .hdcp_2_2_capable = intel_dp_hdcp2_capable,
799 .protocol = HDCP_PROTOCOL_DP,
800};
801
802int intel_dp_hdcp_init(struct intel_digital_port *dig_port,
803 struct intel_connector *intel_connector)
804{
805 struct drm_device *dev = intel_connector->base.dev;
806 struct drm_i915_private *dev_priv = to_i915(dev);
807 struct intel_encoder *intel_encoder = &dig_port->base;
808 enum port port = intel_encoder->port;
809 struct intel_dp *intel_dp = &dig_port->dp;
810
811 if (!is_hdcp_supported(dev_priv, port))
812 return 0;
813
814 if (intel_connector->mst_port)
815 return intel_hdcp_init(intel_connector, dig_port,
816 &intel_dp_mst_hdcp_shim);
817 else if (!intel_dp_is_edp(intel_dp))
818 return intel_hdcp_init(intel_connector, dig_port,
819 &intel_dp_hdcp_shim);
820
821 return 0;
822}
823
