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25#ifndef _INTEL_DPLL_MGR_H_
26#define _INTEL_DPLL_MGR_H_
27
28#include <linux/types.h>
29
30#include "intel_wakeref.h"
31
32
33#define abs_diff(a, b) ({ \
34 typeof(a) __a = (a); \
35 typeof(b) __b = (b); \
36 (void) (&__a == &__b); \
37 __a > __b ? (__a - __b) : (__b - __a); })
38
39enum tc_port;
40struct drm_device;
41struct drm_i915_private;
42struct intel_atomic_state;
43struct intel_crtc;
44struct intel_crtc_state;
45struct intel_encoder;
46struct intel_shared_dpll;
47struct intel_shared_dpll_funcs;
48
49
50
51
52
53
54enum intel_dpll_id {
55
56
57
58 DPLL_ID_PRIVATE = -1,
59
60
61
62
63 DPLL_ID_PCH_PLL_A = 0,
64
65
66
67 DPLL_ID_PCH_PLL_B = 1,
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71
72
73 DPLL_ID_WRPLL1 = 0,
74
75
76
77 DPLL_ID_WRPLL2 = 1,
78
79
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81 DPLL_ID_SPLL = 2,
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83
84
85 DPLL_ID_LCPLL_810 = 3,
86
87
88
89 DPLL_ID_LCPLL_1350 = 4,
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93 DPLL_ID_LCPLL_2700 = 5,
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99 DPLL_ID_SKL_DPLL0 = 0,
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103 DPLL_ID_SKL_DPLL1 = 1,
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107 DPLL_ID_SKL_DPLL2 = 2,
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111 DPLL_ID_SKL_DPLL3 = 3,
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117 DPLL_ID_ICL_DPLL0 = 0,
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121 DPLL_ID_ICL_DPLL1 = 1,
122
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125 DPLL_ID_EHL_DPLL4 = 2,
126
127
128
129 DPLL_ID_ICL_TBTPLL = 2,
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133
134 DPLL_ID_ICL_MGPLL1 = 3,
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139 DPLL_ID_ICL_MGPLL2 = 4,
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144 DPLL_ID_ICL_MGPLL3 = 5,
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149 DPLL_ID_ICL_MGPLL4 = 6,
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153 DPLL_ID_TGL_MGPLL5 = 7,
154
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157 DPLL_ID_TGL_MGPLL6 = 8,
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162 DPLL_ID_DG1_DPLL0 = 0,
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166 DPLL_ID_DG1_DPLL1 = 1,
167
168
169
170 DPLL_ID_DG1_DPLL2 = 2,
171
172
173
174 DPLL_ID_DG1_DPLL3 = 3,
175};
176
177#define I915_NUM_PLLS 9
178
179enum icl_port_dpll_id {
180 ICL_PORT_DPLL_DEFAULT,
181 ICL_PORT_DPLL_MG_PHY,
182
183 ICL_PORT_DPLL_COUNT,
184};
185
186struct intel_dpll_hw_state {
187
188 u32 dpll;
189 u32 dpll_md;
190 u32 fp0;
191 u32 fp1;
192
193
194 u32 wrpll;
195 u32 spll;
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204 u32 ctrl1;
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206 u32 cfgcr1, cfgcr2;
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209 u32 cfgcr0;
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211
212 u32 div0;
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214
215 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
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220
221 u32 mg_refclkin_ctl;
222 u32 mg_clktop2_coreclkctl1;
223 u32 mg_clktop2_hsclkctl;
224 u32 mg_pll_div0;
225 u32 mg_pll_div1;
226 u32 mg_pll_lf;
227 u32 mg_pll_frac_lock;
228 u32 mg_pll_ssc;
229 u32 mg_pll_bias;
230 u32 mg_pll_tdc_coldst_bias;
231 u32 mg_pll_bias_mask;
232 u32 mg_pll_tdc_coldst_bias_mask;
233};
234
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244
245struct intel_shared_dpll_state {
246
247
248
249 u8 pipe_mask;
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254
255 struct intel_dpll_hw_state hw_state;
256};
257
258
259
260
261struct dpll_info {
262
263
264
265 const char *name;
266
267
268
269
270 const struct intel_shared_dpll_funcs *funcs;
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274
275
276 enum intel_dpll_id id;
277
278#define INTEL_DPLL_ALWAYS_ON (1 << 0)
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285
286 u32 flags;
287};
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289
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291
292struct intel_shared_dpll {
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297
298
299 struct intel_shared_dpll_state state;
300
301
302
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304 u8 active_mask;
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309 bool on;
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311
312
313
314 const struct dpll_info *info;
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319
320 intel_wakeref_t wakeref;
321};
322
323#define SKL_DPLL0 0
324#define SKL_DPLL1 1
325#define SKL_DPLL2 2
326#define SKL_DPLL3 3
327
328
329struct intel_shared_dpll *
330intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
331 enum intel_dpll_id id);
332enum intel_dpll_id
333intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
334 struct intel_shared_dpll *pll);
335void assert_shared_dpll(struct drm_i915_private *dev_priv,
336 struct intel_shared_dpll *pll,
337 bool state);
338#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
339#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
340bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
341 struct intel_crtc *crtc,
342 struct intel_encoder *encoder);
343void intel_release_shared_dplls(struct intel_atomic_state *state,
344 struct intel_crtc *crtc);
345void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
346 enum icl_port_dpll_id port_dpll_id);
347void intel_update_active_dpll(struct intel_atomic_state *state,
348 struct intel_crtc *crtc,
349 struct intel_encoder *encoder);
350int intel_dpll_get_freq(struct drm_i915_private *i915,
351 const struct intel_shared_dpll *pll,
352 const struct intel_dpll_hw_state *pll_state);
353bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
354 struct intel_shared_dpll *pll,
355 struct intel_dpll_hw_state *hw_state);
356void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
357void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
358void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
359void intel_shared_dpll_init(struct drm_device *dev);
360void intel_dpll_update_ref_clks(struct drm_i915_private *dev_priv);
361void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
362void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
363
364void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
365 const struct intel_dpll_hw_state *hw_state);
366enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
367bool intel_dpll_is_combophy(enum intel_dpll_id id);
368
369#endif
370