1
2
3
4
5
6#include <drm/drm_managed.h>
7#include <drm/intel-gtt.h>
8
9#include "gem/i915_gem_internal.h"
10#include "gem/i915_gem_lmem.h"
11#include "pxp/intel_pxp.h"
12
13#include "i915_drv.h"
14#include "intel_context.h"
15#include "intel_engine_regs.h"
16#include "intel_gt.h"
17#include "intel_gt_buffer_pool.h"
18#include "intel_gt_clock_utils.h"
19#include "intel_gt_debugfs.h"
20#include "intel_gt_pm.h"
21#include "intel_gt_regs.h"
22#include "intel_gt_requests.h"
23#include "intel_migrate.h"
24#include "intel_mocs.h"
25#include "intel_pm.h"
26#include "intel_rc6.h"
27#include "intel_renderstate.h"
28#include "intel_rps.h"
29#include "intel_uncore.h"
30#include "shmem_utils.h"
31
32void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
33{
34 spin_lock_init(>->irq_lock);
35
36 mutex_init(>->tlb_invalidate_lock);
37
38 INIT_LIST_HEAD(>->closed_vma);
39 spin_lock_init(>->closed_lock);
40
41 init_llist_head(>->watchdog.list);
42 INIT_WORK(>->watchdog.work, intel_gt_watchdog_work);
43
44 intel_gt_init_buffer_pool(gt);
45 intel_gt_init_reset(gt);
46 intel_gt_init_requests(gt);
47 intel_gt_init_timelines(gt);
48 intel_gt_pm_init_early(gt);
49
50 intel_uc_init_early(>->uc);
51 intel_rps_init_early(>->rps);
52}
53
54void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
55{
56 gt->i915 = i915;
57 gt->uncore = &i915->uncore;
58}
59
60int intel_gt_probe_lmem(struct intel_gt *gt)
61{
62 struct drm_i915_private *i915 = gt->i915;
63 struct intel_memory_region *mem;
64 int id;
65 int err;
66
67 mem = intel_gt_setup_lmem(gt);
68 if (IS_ERR(mem)) {
69 err = PTR_ERR(mem);
70 if (err == -ENODEV)
71 return 0;
72
73 drm_err(&i915->drm,
74 "Failed to setup region(%d) type=%d\n",
75 err, INTEL_MEMORY_LOCAL);
76 return err;
77 }
78
79 id = INTEL_REGION_LMEM;
80
81 mem->id = id;
82
83 intel_memory_region_set_name(mem, "local%u", mem->instance);
84
85 GEM_BUG_ON(!HAS_REGION(i915, id));
86 GEM_BUG_ON(i915->mm.regions[id]);
87 i915->mm.regions[id] = mem;
88
89 return 0;
90}
91
92int intel_gt_assign_ggtt(struct intel_gt *gt)
93{
94 gt->ggtt = drmm_kzalloc(>->i915->drm, sizeof(*gt->ggtt), GFP_KERNEL);
95
96 return gt->ggtt ? 0 : -ENOMEM;
97}
98
99static const struct intel_mmio_range icl_l3bank_steering_table[] = {
100 { 0x00B100, 0x00B3FF },
101 {},
102};
103
104static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
105 { 0x004000, 0x004AFF },
106 { 0x00C800, 0x00CFFF },
107 { 0x00DD00, 0x00DDFF },
108 { 0x00E900, 0x00FFFF },
109 {},
110};
111
112static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
113 { 0x00B000, 0x00B0FF },
114 { 0x00D800, 0x00D8FF },
115 {},
116};
117
118static const struct intel_mmio_range dg2_lncf_steering_table[] = {
119 { 0x00B000, 0x00B0FF },
120 { 0x00D880, 0x00D8FF },
121 {},
122};
123
124static u16 slicemask(struct intel_gt *gt, int count)
125{
126 u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
127
128 return intel_slicemask_from_dssmask(dss_mask, count);
129}
130
131int intel_gt_init_mmio(struct intel_gt *gt)
132{
133 struct drm_i915_private *i915 = gt->i915;
134
135 intel_gt_init_clock_frequency(gt);
136
137 intel_uc_init_mmio(>->uc);
138 intel_sseu_info_init(gt);
139
140
141
142
143
144 if (HAS_MSLICES(i915))
145 gt->info.mslice_mask =
146 slicemask(gt, GEN_DSS_PER_MSLICE) |
147 (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
148 GEN12_MEML3_EN_MASK);
149
150 if (IS_DG2(i915)) {
151 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
152 gt->steering_table[LNCF] = dg2_lncf_steering_table;
153 } else if (IS_XEHPSDV(i915)) {
154 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
155 gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
156 } else if (GRAPHICS_VER(i915) >= 11 &&
157 GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
158 gt->steering_table[L3BANK] = icl_l3bank_steering_table;
159 gt->info.l3bank_mask =
160 ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
161 GEN10_L3BANK_MASK;
162 } else if (HAS_MSLICES(i915)) {
163 MISSING_CASE(INTEL_INFO(i915)->platform);
164 }
165
166 return intel_engines_init_mmio(gt);
167}
168
169static void init_unused_ring(struct intel_gt *gt, u32 base)
170{
171 struct intel_uncore *uncore = gt->uncore;
172
173 intel_uncore_write(uncore, RING_CTL(base), 0);
174 intel_uncore_write(uncore, RING_HEAD(base), 0);
175 intel_uncore_write(uncore, RING_TAIL(base), 0);
176 intel_uncore_write(uncore, RING_START(base), 0);
177}
178
179static void init_unused_rings(struct intel_gt *gt)
180{
181 struct drm_i915_private *i915 = gt->i915;
182
183 if (IS_I830(i915)) {
184 init_unused_ring(gt, PRB1_BASE);
185 init_unused_ring(gt, SRB0_BASE);
186 init_unused_ring(gt, SRB1_BASE);
187 init_unused_ring(gt, SRB2_BASE);
188 init_unused_ring(gt, SRB3_BASE);
189 } else if (GRAPHICS_VER(i915) == 2) {
190 init_unused_ring(gt, SRB0_BASE);
191 init_unused_ring(gt, SRB1_BASE);
192 } else if (GRAPHICS_VER(i915) == 3) {
193 init_unused_ring(gt, PRB1_BASE);
194 init_unused_ring(gt, PRB2_BASE);
195 }
196}
197
198int intel_gt_init_hw(struct intel_gt *gt)
199{
200 struct drm_i915_private *i915 = gt->i915;
201 struct intel_uncore *uncore = gt->uncore;
202 int ret;
203
204 gt->last_init_time = ktime_get();
205
206
207 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
208
209 if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
210 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
211
212 if (IS_HASWELL(i915))
213 intel_uncore_write(uncore,
214 HSW_MI_PREDICATE_RESULT_2,
215 IS_HSW_GT3(i915) ?
216 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
217
218
219 intel_gt_apply_workarounds(gt);
220
221 intel_gt_verify_workarounds(gt, "init");
222
223 intel_gt_init_swizzling(gt);
224
225
226
227
228
229
230
231 init_unused_rings(gt);
232
233 ret = i915_ppgtt_init_hw(gt);
234 if (ret) {
235 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
236 goto out;
237 }
238
239
240 ret = intel_uc_init_hw(>->uc);
241 if (ret) {
242 i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
243 goto out;
244 }
245
246 intel_mocs_init(gt);
247
248out:
249 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
250 return ret;
251}
252
253static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
254{
255 intel_uncore_rmw(uncore, reg, 0, set);
256}
257
258static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
259{
260 intel_uncore_rmw(uncore, reg, clr, 0);
261}
262
263static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
264{
265 intel_uncore_rmw(uncore, reg, 0, 0);
266}
267
268static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
269{
270 GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
271 GEN6_RING_FAULT_REG_POSTING_READ(engine);
272}
273
274void
275intel_gt_clear_error_registers(struct intel_gt *gt,
276 intel_engine_mask_t engine_mask)
277{
278 struct drm_i915_private *i915 = gt->i915;
279 struct intel_uncore *uncore = gt->uncore;
280 u32 eir;
281
282 if (GRAPHICS_VER(i915) != 2)
283 clear_register(uncore, PGTBL_ER);
284
285 if (GRAPHICS_VER(i915) < 4)
286 clear_register(uncore, IPEIR(RENDER_RING_BASE));
287 else
288 clear_register(uncore, IPEIR_I965);
289
290 clear_register(uncore, EIR);
291 eir = intel_uncore_read(uncore, EIR);
292 if (eir) {
293
294
295
296
297 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
298 rmw_set(uncore, EMR, eir);
299 intel_uncore_write(uncore, GEN2_IIR,
300 I915_MASTER_ERROR_INTERRUPT);
301 }
302
303 if (GRAPHICS_VER(i915) >= 12) {
304 rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
305 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
306 } else if (GRAPHICS_VER(i915) >= 8) {
307 rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
308 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
309 } else if (GRAPHICS_VER(i915) >= 6) {
310 struct intel_engine_cs *engine;
311 enum intel_engine_id id;
312
313 for_each_engine_masked(engine, gt, engine_mask, id)
314 gen6_clear_engine_error_register(engine);
315 }
316}
317
318static void gen6_check_faults(struct intel_gt *gt)
319{
320 struct intel_engine_cs *engine;
321 enum intel_engine_id id;
322 u32 fault;
323
324 for_each_engine(engine, gt, id) {
325 fault = GEN6_RING_FAULT_REG_READ(engine);
326 if (fault & RING_FAULT_VALID) {
327 drm_dbg(&engine->i915->drm, "Unexpected fault\n"
328 "\tAddr: 0x%08lx\n"
329 "\tAddress space: %s\n"
330 "\tSource ID: %d\n"
331 "\tType: %d\n",
332 fault & PAGE_MASK,
333 fault & RING_FAULT_GTTSEL_MASK ?
334 "GGTT" : "PPGTT",
335 RING_FAULT_SRCID(fault),
336 RING_FAULT_FAULT_TYPE(fault));
337 }
338 }
339}
340
341static void gen8_check_faults(struct intel_gt *gt)
342{
343 struct intel_uncore *uncore = gt->uncore;
344 i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
345 u32 fault;
346
347 if (GRAPHICS_VER(gt->i915) >= 12) {
348 fault_reg = GEN12_RING_FAULT_REG;
349 fault_data0_reg = GEN12_FAULT_TLB_DATA0;
350 fault_data1_reg = GEN12_FAULT_TLB_DATA1;
351 } else {
352 fault_reg = GEN8_RING_FAULT_REG;
353 fault_data0_reg = GEN8_FAULT_TLB_DATA0;
354 fault_data1_reg = GEN8_FAULT_TLB_DATA1;
355 }
356
357 fault = intel_uncore_read(uncore, fault_reg);
358 if (fault & RING_FAULT_VALID) {
359 u32 fault_data0, fault_data1;
360 u64 fault_addr;
361
362 fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
363 fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
364
365 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
366 ((u64)fault_data0 << 12);
367
368 drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
369 "\tAddr: 0x%08x_%08x\n"
370 "\tAddress space: %s\n"
371 "\tEngine ID: %d\n"
372 "\tSource ID: %d\n"
373 "\tType: %d\n",
374 upper_32_bits(fault_addr), lower_32_bits(fault_addr),
375 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
376 GEN8_RING_FAULT_ENGINE_ID(fault),
377 RING_FAULT_SRCID(fault),
378 RING_FAULT_FAULT_TYPE(fault));
379 }
380}
381
382void intel_gt_check_and_clear_faults(struct intel_gt *gt)
383{
384 struct drm_i915_private *i915 = gt->i915;
385
386
387 if (GRAPHICS_VER(i915) >= 8)
388 gen8_check_faults(gt);
389 else if (GRAPHICS_VER(i915) >= 6)
390 gen6_check_faults(gt);
391 else
392 return;
393
394 intel_gt_clear_error_registers(gt, ALL_ENGINES);
395}
396
397void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
398{
399 struct intel_uncore *uncore = gt->uncore;
400 intel_wakeref_t wakeref;
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421 wmb();
422
423 if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
424 return;
425
426 intel_gt_chipset_flush(gt);
427
428 with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
429 unsigned long flags;
430
431 spin_lock_irqsave(&uncore->lock, flags);
432 intel_uncore_posting_read_fw(uncore,
433 RING_HEAD(RENDER_RING_BASE));
434 spin_unlock_irqrestore(&uncore->lock, flags);
435 }
436}
437
438void intel_gt_chipset_flush(struct intel_gt *gt)
439{
440 wmb();
441 if (GRAPHICS_VER(gt->i915) < 6)
442 intel_gtt_chipset_flush();
443}
444
445void intel_gt_driver_register(struct intel_gt *gt)
446{
447 intel_rps_driver_register(>->rps);
448
449 intel_gt_debugfs_register(gt);
450}
451
452static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
453{
454 struct drm_i915_private *i915 = gt->i915;
455 struct drm_i915_gem_object *obj;
456 struct i915_vma *vma;
457 int ret;
458
459 obj = i915_gem_object_create_lmem(i915, size,
460 I915_BO_ALLOC_VOLATILE |
461 I915_BO_ALLOC_GPU_ONLY);
462 if (IS_ERR(obj))
463 obj = i915_gem_object_create_stolen(i915, size);
464 if (IS_ERR(obj))
465 obj = i915_gem_object_create_internal(i915, size);
466 if (IS_ERR(obj)) {
467 drm_err(&i915->drm, "Failed to allocate scratch page\n");
468 return PTR_ERR(obj);
469 }
470
471 vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
472 if (IS_ERR(vma)) {
473 ret = PTR_ERR(vma);
474 goto err_unref;
475 }
476
477 ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH);
478 if (ret)
479 goto err_unref;
480
481 gt->scratch = i915_vma_make_unshrinkable(vma);
482
483 return 0;
484
485err_unref:
486 i915_gem_object_put(obj);
487 return ret;
488}
489
490static void intel_gt_fini_scratch(struct intel_gt *gt)
491{
492 i915_vma_unpin_and_release(>->scratch, 0);
493}
494
495static struct i915_address_space *kernel_vm(struct intel_gt *gt)
496{
497 if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
498 return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
499 else
500 return i915_vm_get(>->ggtt->vm);
501}
502
503static int __engines_record_defaults(struct intel_gt *gt)
504{
505 struct i915_request *requests[I915_NUM_ENGINES] = {};
506 struct intel_engine_cs *engine;
507 enum intel_engine_id id;
508 int err = 0;
509
510
511
512
513
514
515
516
517
518
519 for_each_engine(engine, gt, id) {
520 struct intel_renderstate so;
521 struct intel_context *ce;
522 struct i915_request *rq;
523
524
525 GEM_BUG_ON(!engine->kernel_context);
526
527 ce = intel_context_create(engine);
528 if (IS_ERR(ce)) {
529 err = PTR_ERR(ce);
530 goto out;
531 }
532
533 err = intel_renderstate_init(&so, ce);
534 if (err)
535 goto err;
536
537 rq = i915_request_create(ce);
538 if (IS_ERR(rq)) {
539 err = PTR_ERR(rq);
540 goto err_fini;
541 }
542
543 err = intel_engine_emit_ctx_wa(rq);
544 if (err)
545 goto err_rq;
546
547 err = intel_renderstate_emit(&so, rq);
548 if (err)
549 goto err_rq;
550
551err_rq:
552 requests[id] = i915_request_get(rq);
553 i915_request_add(rq);
554err_fini:
555 intel_renderstate_fini(&so, ce);
556err:
557 if (err) {
558 intel_context_put(ce);
559 goto out;
560 }
561 }
562
563
564 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
565 err = -EIO;
566 goto out;
567 }
568
569 for (id = 0; id < ARRAY_SIZE(requests); id++) {
570 struct i915_request *rq;
571 struct file *state;
572
573 rq = requests[id];
574 if (!rq)
575 continue;
576
577 if (rq->fence.error) {
578 err = -EIO;
579 goto out;
580 }
581
582 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
583 if (!rq->context->state)
584 continue;
585
586
587 state = shmem_create_from_object(rq->context->state->obj);
588 if (IS_ERR(state)) {
589 err = PTR_ERR(state);
590 goto out;
591 }
592 rq->engine->default_state = state;
593 }
594
595out:
596
597
598
599
600
601 if (err)
602 intel_gt_set_wedged(gt);
603
604 for (id = 0; id < ARRAY_SIZE(requests); id++) {
605 struct intel_context *ce;
606 struct i915_request *rq;
607
608 rq = requests[id];
609 if (!rq)
610 continue;
611
612 ce = rq->context;
613 i915_request_put(rq);
614 intel_context_put(ce);
615 }
616 return err;
617}
618
619static int __engines_verify_workarounds(struct intel_gt *gt)
620{
621 struct intel_engine_cs *engine;
622 enum intel_engine_id id;
623 int err = 0;
624
625 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
626 return 0;
627
628 for_each_engine(engine, gt, id) {
629 if (intel_engine_verify_workarounds(engine, "load"))
630 err = -EIO;
631 }
632
633
634 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME)
635 err = -EIO;
636
637 return err;
638}
639
640static void __intel_gt_disable(struct intel_gt *gt)
641{
642 intel_gt_set_wedged_on_fini(gt);
643
644 intel_gt_suspend_prepare(gt);
645 intel_gt_suspend_late(gt);
646
647 GEM_BUG_ON(intel_gt_pm_is_awake(gt));
648}
649
650int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
651{
652 long remaining_timeout;
653
654
655 if (!intel_gt_pm_is_awake(gt))
656 return 0;
657
658 while ((timeout = intel_gt_retire_requests_timeout(gt, timeout,
659 &remaining_timeout)) > 0) {
660 cond_resched();
661 if (signal_pending(current))
662 return -EINTR;
663 }
664
665 return timeout ? timeout : intel_uc_wait_for_idle(>->uc,
666 remaining_timeout);
667}
668
669int intel_gt_init(struct intel_gt *gt)
670{
671 int err;
672
673 err = i915_inject_probe_error(gt->i915, -ENODEV);
674 if (err)
675 return err;
676
677 intel_gt_init_workarounds(gt);
678
679
680
681
682
683
684
685
686 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
687
688 err = intel_gt_init_scratch(gt,
689 GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
690 if (err)
691 goto out_fw;
692
693 intel_gt_pm_init(gt);
694
695 gt->vm = kernel_vm(gt);
696 if (!gt->vm) {
697 err = -ENOMEM;
698 goto err_pm;
699 }
700
701 intel_set_mocs_index(gt);
702
703 err = intel_engines_init(gt);
704 if (err)
705 goto err_engines;
706
707 err = intel_uc_init(>->uc);
708 if (err)
709 goto err_engines;
710
711 err = intel_gt_resume(gt);
712 if (err)
713 goto err_uc_init;
714
715 err = __engines_record_defaults(gt);
716 if (err)
717 goto err_gt;
718
719 err = __engines_verify_workarounds(gt);
720 if (err)
721 goto err_gt;
722
723 intel_uc_init_late(>->uc);
724
725 err = i915_inject_probe_error(gt->i915, -EIO);
726 if (err)
727 goto err_gt;
728
729 intel_migrate_init(>->migrate, gt);
730
731 intel_pxp_init(>->pxp);
732
733 goto out_fw;
734err_gt:
735 __intel_gt_disable(gt);
736 intel_uc_fini_hw(>->uc);
737err_uc_init:
738 intel_uc_fini(>->uc);
739err_engines:
740 intel_engines_release(gt);
741 i915_vm_put(fetch_and_zero(>->vm));
742err_pm:
743 intel_gt_pm_fini(gt);
744 intel_gt_fini_scratch(gt);
745out_fw:
746 if (err)
747 intel_gt_set_wedged_on_init(gt);
748 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
749 return err;
750}
751
752void intel_gt_driver_remove(struct intel_gt *gt)
753{
754 __intel_gt_disable(gt);
755
756 intel_migrate_fini(>->migrate);
757 intel_uc_driver_remove(>->uc);
758
759 intel_engines_release(gt);
760
761 intel_gt_flush_buffer_pool(gt);
762}
763
764void intel_gt_driver_unregister(struct intel_gt *gt)
765{
766 intel_wakeref_t wakeref;
767
768 intel_rps_driver_unregister(>->rps);
769
770 intel_pxp_fini(>->pxp);
771
772
773
774
775
776
777 intel_gt_set_wedged_on_fini(gt);
778
779
780 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
781 __intel_gt_reset(gt, ALL_ENGINES);
782}
783
784void intel_gt_driver_release(struct intel_gt *gt)
785{
786 struct i915_address_space *vm;
787
788 vm = fetch_and_zero(>->vm);
789 if (vm)
790 i915_vm_put(vm);
791
792 intel_wa_list_free(>->wa_list);
793 intel_gt_pm_fini(gt);
794 intel_gt_fini_scratch(gt);
795 intel_gt_fini_buffer_pool(gt);
796}
797
798void intel_gt_driver_late_release(struct intel_gt *gt)
799{
800
801 rcu_barrier();
802
803 intel_uc_driver_late_release(>->uc);
804 intel_gt_fini_requests(gt);
805 intel_gt_fini_reset(gt);
806 intel_gt_fini_timelines(gt);
807 intel_engines_free(gt);
808}
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
825 i915_reg_t reg,
826 enum intel_steering_type type)
827{
828 const u32 offset = i915_mmio_reg_offset(reg);
829 const struct intel_mmio_range *entry;
830
831 if (likely(!intel_gt_needs_read_steering(gt, type)))
832 return false;
833
834 for (entry = gt->steering_table[type]; entry->end; entry++) {
835 if (offset >= entry->start && offset <= entry->end)
836 return true;
837 }
838
839 return false;
840}
841
842
843
844
845
846
847
848
849
850
851
852static void intel_gt_get_valid_steering(struct intel_gt *gt,
853 enum intel_steering_type type,
854 u8 *sliceid, u8 *subsliceid)
855{
856 switch (type) {
857 case L3BANK:
858 GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask);
859
860 *sliceid = 0;
861 *subsliceid = __ffs(gt->info.l3bank_mask);
862 break;
863 case MSLICE:
864 GEM_DEBUG_WARN_ON(!gt->info.mslice_mask);
865
866 *sliceid = __ffs(gt->info.mslice_mask);
867 *subsliceid = 0;
868 break;
869 case LNCF:
870 GEM_DEBUG_WARN_ON(!gt->info.mslice_mask);
871
872
873
874
875
876 *sliceid = __ffs(gt->info.mslice_mask) << 1;
877 *subsliceid = 0;
878 break;
879 default:
880 MISSING_CASE(type);
881 *sliceid = 0;
882 *subsliceid = 0;
883 }
884}
885
886
887
888
889
890
891
892
893
894
895
896
897u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg)
898{
899 int type;
900 u8 sliceid, subsliceid;
901
902 for (type = 0; type < NUM_STEERING_TYPES; type++) {
903 if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
904 intel_gt_get_valid_steering(gt, type, &sliceid,
905 &subsliceid);
906 return intel_uncore_read_with_mcr_steering_fw(gt->uncore,
907 reg,
908 sliceid,
909 subsliceid);
910 }
911 }
912
913 return intel_uncore_read_fw(gt->uncore, reg);
914}
915
916u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg)
917{
918 int type;
919 u8 sliceid, subsliceid;
920
921 for (type = 0; type < NUM_STEERING_TYPES; type++) {
922 if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
923 intel_gt_get_valid_steering(gt, type, &sliceid,
924 &subsliceid);
925 return intel_uncore_read_with_mcr_steering(gt->uncore,
926 reg,
927 sliceid,
928 subsliceid);
929 }
930 }
931
932 return intel_uncore_read(gt->uncore, reg);
933}
934
935void intel_gt_info_print(const struct intel_gt_info *info,
936 struct drm_printer *p)
937{
938 drm_printf(p, "available engines: %x\n", info->engine_mask);
939
940 intel_sseu_dump(&info->sseu, p);
941}
942
943struct reg_and_bit {
944 i915_reg_t reg;
945 u32 bit;
946};
947
948static struct reg_and_bit
949get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8,
950 const i915_reg_t *regs, const unsigned int num)
951{
952 const unsigned int class = engine->class;
953 struct reg_and_bit rb = { };
954
955 if (drm_WARN_ON_ONCE(&engine->i915->drm,
956 class >= num || !regs[class].reg))
957 return rb;
958
959 rb.reg = regs[class];
960 if (gen8 && class == VIDEO_DECODE_CLASS)
961 rb.reg.reg += 4 * engine->instance;
962 else
963 rb.bit = engine->instance;
964
965 rb.bit = BIT(rb.bit);
966
967 return rb;
968}
969
970void intel_gt_invalidate_tlbs(struct intel_gt *gt)
971{
972 static const i915_reg_t gen8_regs[] = {
973 [RENDER_CLASS] = GEN8_RTCR,
974 [VIDEO_DECODE_CLASS] = GEN8_M1TCR,
975 [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR,
976 [COPY_ENGINE_CLASS] = GEN8_BTCR,
977 };
978 static const i915_reg_t gen12_regs[] = {
979 [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR,
980 [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR,
981 [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR,
982 [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
983 };
984 struct drm_i915_private *i915 = gt->i915;
985 struct intel_uncore *uncore = gt->uncore;
986 struct intel_engine_cs *engine;
987 enum intel_engine_id id;
988 const i915_reg_t *regs;
989 unsigned int num = 0;
990
991 if (I915_SELFTEST_ONLY(gt->awake == -ENODEV))
992 return;
993
994 if (GRAPHICS_VER(i915) == 12) {
995 regs = gen12_regs;
996 num = ARRAY_SIZE(gen12_regs);
997 } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) {
998 regs = gen8_regs;
999 num = ARRAY_SIZE(gen8_regs);
1000 } else if (GRAPHICS_VER(i915) < 8) {
1001 return;
1002 }
1003
1004 if (drm_WARN_ONCE(&i915->drm, !num,
1005 "Platform does not implement TLB invalidation!"))
1006 return;
1007
1008 GEM_TRACE("\n");
1009
1010 assert_rpm_wakelock_held(&i915->runtime_pm);
1011
1012 mutex_lock(>->tlb_invalidate_lock);
1013 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
1014
1015 for_each_engine(engine, gt, id) {
1016
1017
1018
1019
1020
1021 const unsigned int timeout_us = 100;
1022 const unsigned int timeout_ms = 4;
1023 struct reg_and_bit rb;
1024
1025 rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
1026 if (!i915_mmio_reg_offset(rb.reg))
1027 continue;
1028
1029 intel_uncore_write_fw(uncore, rb.reg, rb.bit);
1030 if (__intel_wait_for_register_fw(uncore,
1031 rb.reg, rb.bit, 0,
1032 timeout_us, timeout_ms,
1033 NULL))
1034 drm_err_ratelimited(>->i915->drm,
1035 "%s TLB invalidation did not complete in %ums!\n",
1036 engine->name, timeout_ms);
1037 }
1038
1039
1040
1041
1042
1043
1044
1045 intel_uncore_forcewake_put_delayed(uncore, FORCEWAKE_ALL);
1046 mutex_unlock(>->tlb_invalidate_lock);
1047}
1048