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29#include <linux/sched/mm.h>
30#include <linux/sort.h>
31
32#include <drm/drm_debugfs.h>
33
34#include "gem/i915_gem_context.h"
35#include "gt/intel_gt.h"
36#include "gt/intel_gt_buffer_pool.h"
37#include "gt/intel_gt_clock_utils.h"
38#include "gt/intel_gt_debugfs.h"
39#include "gt/intel_gt_pm.h"
40#include "gt/intel_gt_pm_debugfs.h"
41#include "gt/intel_gt_regs.h"
42#include "gt/intel_gt_requests.h"
43#include "gt/intel_rc6.h"
44#include "gt/intel_reset.h"
45#include "gt/intel_rps.h"
46#include "gt/intel_sseu_debugfs.h"
47
48#include "i915_debugfs.h"
49#include "i915_debugfs_params.h"
50#include "i915_irq.h"
51#include "i915_scheduler.h"
52#include "intel_mchbar_regs.h"
53#include "intel_pm.h"
54
55static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
56{
57 return to_i915(node->minor->dev);
58}
59
60static int i915_capabilities(struct seq_file *m, void *data)
61{
62 struct drm_i915_private *i915 = node_to_i915(m->private);
63 struct drm_printer p = drm_seq_file_printer(m);
64
65 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
66
67 intel_device_info_print_static(INTEL_INFO(i915), &p);
68 intel_device_info_print_runtime(RUNTIME_INFO(i915), &p);
69 i915_print_iommu_status(i915, &p);
70 intel_gt_info_print(&to_gt(i915)->info, &p);
71 intel_driver_caps_print(&i915->caps, &p);
72
73 kernel_param_lock(THIS_MODULE);
74 i915_params_dump(&i915->params, &p);
75 kernel_param_unlock(THIS_MODULE);
76
77 return 0;
78}
79
80static char get_tiling_flag(struct drm_i915_gem_object *obj)
81{
82 switch (i915_gem_object_get_tiling(obj)) {
83 default:
84 case I915_TILING_NONE: return ' ';
85 case I915_TILING_X: return 'X';
86 case I915_TILING_Y: return 'Y';
87 }
88}
89
90static char get_global_flag(struct drm_i915_gem_object *obj)
91{
92 return READ_ONCE(obj->userfault_count) ? 'g' : ' ';
93}
94
95static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
96{
97 return obj->mm.mapping ? 'M' : ' ';
98}
99
100static const char *
101stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
102{
103 size_t x = 0;
104
105 switch (page_sizes) {
106 case 0:
107 return "";
108 case I915_GTT_PAGE_SIZE_4K:
109 return "4K";
110 case I915_GTT_PAGE_SIZE_64K:
111 return "64K";
112 case I915_GTT_PAGE_SIZE_2M:
113 return "2M";
114 default:
115 if (!buf)
116 return "M";
117
118 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
119 x += snprintf(buf + x, len - x, "2M, ");
120 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
121 x += snprintf(buf + x, len - x, "64K, ");
122 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
123 x += snprintf(buf + x, len - x, "4K, ");
124 buf[x-2] = '\0';
125
126 return buf;
127 }
128}
129
130static const char *stringify_vma_type(const struct i915_vma *vma)
131{
132 if (i915_vma_is_ggtt(vma))
133 return "ggtt";
134
135 if (i915_vma_is_dpt(vma))
136 return "dpt";
137
138 return "ppgtt";
139}
140
141static const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
142{
143 switch (type) {
144 case I915_CACHE_NONE: return " uncached";
145 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
146 case I915_CACHE_L3_LLC: return " L3+LLC";
147 case I915_CACHE_WT: return " WT";
148 default: return "";
149 }
150}
151
152void
153i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
154{
155 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
156 struct i915_vma *vma;
157 int pin_count = 0;
158
159 seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s",
160 &obj->base,
161 get_tiling_flag(obj),
162 get_global_flag(obj),
163 get_pin_mapped_flag(obj),
164 obj->base.size / 1024,
165 obj->read_domains,
166 obj->write_domain,
167 i915_cache_level_str(dev_priv, obj->cache_level),
168 obj->mm.dirty ? " dirty" : "",
169 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
170 if (obj->base.name)
171 seq_printf(m, " (name: %d)", obj->base.name);
172
173 spin_lock(&obj->vma.lock);
174 list_for_each_entry(vma, &obj->vma.list, obj_link) {
175 if (!drm_mm_node_allocated(&vma->node))
176 continue;
177
178 spin_unlock(&obj->vma.lock);
179
180 if (i915_vma_is_pinned(vma))
181 pin_count++;
182
183 seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
184 stringify_vma_type(vma),
185 vma->node.start, vma->node.size,
186 stringify_page_sizes(vma->resource->page_sizes_gtt,
187 NULL, 0));
188 if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
189 switch (vma->ggtt_view.type) {
190 case I915_GGTT_VIEW_NORMAL:
191 seq_puts(m, ", normal");
192 break;
193
194 case I915_GGTT_VIEW_PARTIAL:
195 seq_printf(m, ", partial [%08llx+%x]",
196 vma->ggtt_view.partial.offset << PAGE_SHIFT,
197 vma->ggtt_view.partial.size << PAGE_SHIFT);
198 break;
199
200 case I915_GGTT_VIEW_ROTATED:
201 seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]",
202 vma->ggtt_view.rotated.plane[0].width,
203 vma->ggtt_view.rotated.plane[0].height,
204 vma->ggtt_view.rotated.plane[0].src_stride,
205 vma->ggtt_view.rotated.plane[0].dst_stride,
206 vma->ggtt_view.rotated.plane[0].offset,
207 vma->ggtt_view.rotated.plane[1].width,
208 vma->ggtt_view.rotated.plane[1].height,
209 vma->ggtt_view.rotated.plane[1].src_stride,
210 vma->ggtt_view.rotated.plane[1].dst_stride,
211 vma->ggtt_view.rotated.plane[1].offset);
212 break;
213
214 case I915_GGTT_VIEW_REMAPPED:
215 seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]",
216 vma->ggtt_view.remapped.plane[0].width,
217 vma->ggtt_view.remapped.plane[0].height,
218 vma->ggtt_view.remapped.plane[0].src_stride,
219 vma->ggtt_view.remapped.plane[0].dst_stride,
220 vma->ggtt_view.remapped.plane[0].offset,
221 vma->ggtt_view.remapped.plane[1].width,
222 vma->ggtt_view.remapped.plane[1].height,
223 vma->ggtt_view.remapped.plane[1].src_stride,
224 vma->ggtt_view.remapped.plane[1].dst_stride,
225 vma->ggtt_view.remapped.plane[1].offset);
226 break;
227
228 default:
229 MISSING_CASE(vma->ggtt_view.type);
230 break;
231 }
232 }
233 if (vma->fence)
234 seq_printf(m, " , fence: %d", vma->fence->id);
235 seq_puts(m, ")");
236
237 spin_lock(&obj->vma.lock);
238 }
239 spin_unlock(&obj->vma.lock);
240
241 seq_printf(m, " (pinned x %d)", pin_count);
242 if (i915_gem_object_is_stolen(obj))
243 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
244 if (i915_gem_object_is_framebuffer(obj))
245 seq_printf(m, " (fb)");
246}
247
248static int i915_gem_object_info(struct seq_file *m, void *data)
249{
250 struct drm_i915_private *i915 = node_to_i915(m->private);
251 struct drm_printer p = drm_seq_file_printer(m);
252 struct intel_memory_region *mr;
253 enum intel_region_id id;
254
255 seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n",
256 i915->mm.shrink_count,
257 atomic_read(&i915->mm.free_count),
258 i915->mm.shrink_memory);
259 for_each_memory_region(mr, i915, id)
260 intel_memory_region_debug(mr, &p);
261
262 return 0;
263}
264
265#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
266static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
267 size_t count, loff_t *pos)
268{
269 struct i915_gpu_coredump *error;
270 ssize_t ret;
271 void *buf;
272
273 error = file->private_data;
274 if (!error)
275 return 0;
276
277
278 buf = kmalloc(count, GFP_KERNEL);
279 if (!buf)
280 return -ENOMEM;
281
282 ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count);
283 if (ret <= 0)
284 goto out;
285
286 if (!copy_to_user(ubuf, buf, ret))
287 *pos += ret;
288 else
289 ret = -EFAULT;
290
291out:
292 kfree(buf);
293 return ret;
294}
295
296static int gpu_state_release(struct inode *inode, struct file *file)
297{
298 i915_gpu_coredump_put(file->private_data);
299 return 0;
300}
301
302static int i915_gpu_info_open(struct inode *inode, struct file *file)
303{
304 struct drm_i915_private *i915 = inode->i_private;
305 struct i915_gpu_coredump *gpu;
306 intel_wakeref_t wakeref;
307
308 gpu = NULL;
309 with_intel_runtime_pm(&i915->runtime_pm, wakeref)
310 gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES);
311 if (IS_ERR(gpu))
312 return PTR_ERR(gpu);
313
314 file->private_data = gpu;
315 return 0;
316}
317
318static const struct file_operations i915_gpu_info_fops = {
319 .owner = THIS_MODULE,
320 .open = i915_gpu_info_open,
321 .read = gpu_state_read,
322 .llseek = default_llseek,
323 .release = gpu_state_release,
324};
325
326static ssize_t
327i915_error_state_write(struct file *filp,
328 const char __user *ubuf,
329 size_t cnt,
330 loff_t *ppos)
331{
332 struct i915_gpu_coredump *error = filp->private_data;
333
334 if (!error)
335 return 0;
336
337 drm_dbg(&error->i915->drm, "Resetting error state\n");
338 i915_reset_error_state(error->i915);
339
340 return cnt;
341}
342
343static int i915_error_state_open(struct inode *inode, struct file *file)
344{
345 struct i915_gpu_coredump *error;
346
347 error = i915_first_error_state(inode->i_private);
348 if (IS_ERR(error))
349 return PTR_ERR(error);
350
351 file->private_data = error;
352 return 0;
353}
354
355static const struct file_operations i915_error_state_fops = {
356 .owner = THIS_MODULE,
357 .open = i915_error_state_open,
358 .read = gpu_state_read,
359 .write = i915_error_state_write,
360 .llseek = default_llseek,
361 .release = gpu_state_release,
362};
363#endif
364
365static int i915_frequency_info(struct seq_file *m, void *unused)
366{
367 struct drm_i915_private *i915 = node_to_i915(m->private);
368 struct intel_gt *gt = to_gt(i915);
369 struct drm_printer p = drm_seq_file_printer(m);
370
371 intel_gt_pm_frequency_dump(gt, &p);
372
373 return 0;
374}
375
376static const char *swizzle_string(unsigned swizzle)
377{
378 switch (swizzle) {
379 case I915_BIT_6_SWIZZLE_NONE:
380 return "none";
381 case I915_BIT_6_SWIZZLE_9:
382 return "bit9";
383 case I915_BIT_6_SWIZZLE_9_10:
384 return "bit9/bit10";
385 case I915_BIT_6_SWIZZLE_9_11:
386 return "bit9/bit11";
387 case I915_BIT_6_SWIZZLE_9_10_11:
388 return "bit9/bit10/bit11";
389 case I915_BIT_6_SWIZZLE_9_17:
390 return "bit9/bit17";
391 case I915_BIT_6_SWIZZLE_9_10_17:
392 return "bit9/bit10/bit17";
393 case I915_BIT_6_SWIZZLE_UNKNOWN:
394 return "unknown";
395 }
396
397 return "bug";
398}
399
400static int i915_swizzle_info(struct seq_file *m, void *data)
401{
402 struct drm_i915_private *dev_priv = node_to_i915(m->private);
403 struct intel_uncore *uncore = &dev_priv->uncore;
404 intel_wakeref_t wakeref;
405
406 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
407 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
408 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
409 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
410
411 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
412 seq_puts(m, "L-shaped memory detected\n");
413
414
415 if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))
416 return 0;
417
418 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
419
420 if (IS_GRAPHICS_VER(dev_priv, 3, 4)) {
421 seq_printf(m, "DDC = 0x%08x\n",
422 intel_uncore_read(uncore, DCC));
423 seq_printf(m, "DDC2 = 0x%08x\n",
424 intel_uncore_read(uncore, DCC2));
425 seq_printf(m, "C0DRB3 = 0x%04x\n",
426 intel_uncore_read16(uncore, C0DRB3_BW));
427 seq_printf(m, "C1DRB3 = 0x%04x\n",
428 intel_uncore_read16(uncore, C1DRB3_BW));
429 } else if (GRAPHICS_VER(dev_priv) >= 6) {
430 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
431 intel_uncore_read(uncore, MAD_DIMM_C0));
432 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
433 intel_uncore_read(uncore, MAD_DIMM_C1));
434 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
435 intel_uncore_read(uncore, MAD_DIMM_C2));
436 seq_printf(m, "TILECTL = 0x%08x\n",
437 intel_uncore_read(uncore, TILECTL));
438 if (GRAPHICS_VER(dev_priv) >= 8)
439 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
440 intel_uncore_read(uncore, GAMTARBMODE));
441 else
442 seq_printf(m, "ARB_MODE = 0x%08x\n",
443 intel_uncore_read(uncore, ARB_MODE));
444 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
445 intel_uncore_read(uncore, DISP_ARB_CTL));
446 }
447
448 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
449
450 return 0;
451}
452
453static int i915_rps_boost_info(struct seq_file *m, void *data)
454{
455 struct drm_i915_private *dev_priv = node_to_i915(m->private);
456 struct intel_rps *rps = &to_gt(dev_priv)->rps;
457
458 seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));
459 seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));
460 seq_printf(m, "GPU busy? %s\n", yesno(to_gt(dev_priv)->awake));
461 seq_printf(m, "Boosts outstanding? %d\n",
462 atomic_read(&rps->num_waiters));
463 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
464 seq_printf(m, "Frequency requested %d, actual %d\n",
465 intel_gpu_freq(rps, rps->cur_freq),
466 intel_rps_read_actual_frequency(rps));
467 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
468 intel_gpu_freq(rps, rps->min_freq),
469 intel_gpu_freq(rps, rps->min_freq_softlimit),
470 intel_gpu_freq(rps, rps->max_freq_softlimit),
471 intel_gpu_freq(rps, rps->max_freq));
472 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
473 intel_gpu_freq(rps, rps->idle_freq),
474 intel_gpu_freq(rps, rps->efficient_freq),
475 intel_gpu_freq(rps, rps->boost_freq));
476
477 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
478
479 return 0;
480}
481
482static int i915_runtime_pm_status(struct seq_file *m, void *unused)
483{
484 struct drm_i915_private *dev_priv = node_to_i915(m->private);
485 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
486
487 if (!HAS_RUNTIME_PM(dev_priv))
488 seq_puts(m, "Runtime power management not supported\n");
489
490 seq_printf(m, "Runtime power status: %s\n",
491 enableddisabled(!dev_priv->power_domains.init_wakeref));
492
493 seq_printf(m, "GPU idle: %s\n", yesno(!to_gt(dev_priv)->awake));
494 seq_printf(m, "IRQs disabled: %s\n",
495 yesno(!intel_irqs_enabled(dev_priv)));
496#ifdef CONFIG_PM
497 seq_printf(m, "Usage count: %d\n",
498 atomic_read(&dev_priv->drm.dev->power.usage_count));
499#else
500 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
501#endif
502 seq_printf(m, "PCI device power state: %s [%d]\n",
503 pci_power_name(pdev->current_state),
504 pdev->current_state);
505
506 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) {
507 struct drm_printer p = drm_seq_file_printer(m);
508
509 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p);
510 }
511
512 return 0;
513}
514
515static int i915_engine_info(struct seq_file *m, void *unused)
516{
517 struct drm_i915_private *i915 = node_to_i915(m->private);
518 struct intel_engine_cs *engine;
519 intel_wakeref_t wakeref;
520 struct drm_printer p;
521
522 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
523
524 seq_printf(m, "GT awake? %s [%d], %llums\n",
525 yesno(to_gt(i915)->awake),
526 atomic_read(&to_gt(i915)->wakeref.count),
527 ktime_to_ms(intel_gt_get_awake_time(to_gt(i915))));
528 seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
529 to_gt(i915)->clock_frequency,
530 to_gt(i915)->clock_period_ns);
531
532 p = drm_seq_file_printer(m);
533 for_each_uabi_engine(engine, i915)
534 intel_engine_dump(engine, &p, "%s\n", engine->name);
535
536 intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule);
537
538 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
539
540 return 0;
541}
542
543static int i915_wa_registers(struct seq_file *m, void *unused)
544{
545 struct drm_i915_private *i915 = node_to_i915(m->private);
546 struct intel_engine_cs *engine;
547
548 for_each_uabi_engine(engine, i915) {
549 const struct i915_wa_list *wal = &engine->ctx_wa_list;
550 const struct i915_wa *wa;
551 unsigned int count;
552
553 count = wal->count;
554 if (!count)
555 continue;
556
557 seq_printf(m, "%s: Workarounds applied: %u\n",
558 engine->name, count);
559
560 for (wa = wal->list; count--; wa++)
561 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
562 i915_mmio_reg_offset(wa->reg),
563 wa->set, wa->clr);
564
565 seq_printf(m, "\n");
566 }
567
568 return 0;
569}
570
571static int i915_wedged_get(void *data, u64 *val)
572{
573 struct drm_i915_private *i915 = data;
574
575 return intel_gt_debugfs_reset_show(to_gt(i915), val);
576}
577
578static int i915_wedged_set(void *data, u64 val)
579{
580 struct drm_i915_private *i915 = data;
581
582 return intel_gt_debugfs_reset_store(to_gt(i915), val);
583}
584
585DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
586 i915_wedged_get, i915_wedged_set,
587 "%llu\n");
588
589static int
590i915_perf_noa_delay_set(void *data, u64 val)
591{
592 struct drm_i915_private *i915 = data;
593
594
595
596
597
598 if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX)
599 return -EINVAL;
600
601 atomic64_set(&i915->perf.noa_programming_delay, val);
602 return 0;
603}
604
605static int
606i915_perf_noa_delay_get(void *data, u64 *val)
607{
608 struct drm_i915_private *i915 = data;
609
610 *val = atomic64_read(&i915->perf.noa_programming_delay);
611 return 0;
612}
613
614DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
615 i915_perf_noa_delay_get,
616 i915_perf_noa_delay_set,
617 "%llu\n");
618
619#define DROP_UNBOUND BIT(0)
620#define DROP_BOUND BIT(1)
621#define DROP_RETIRE BIT(2)
622#define DROP_ACTIVE BIT(3)
623#define DROP_FREED BIT(4)
624#define DROP_SHRINK_ALL BIT(5)
625#define DROP_IDLE BIT(6)
626#define DROP_RESET_ACTIVE BIT(7)
627#define DROP_RESET_SEQNO BIT(8)
628#define DROP_RCU BIT(9)
629#define DROP_ALL (DROP_UNBOUND | \
630 DROP_BOUND | \
631 DROP_RETIRE | \
632 DROP_ACTIVE | \
633 DROP_FREED | \
634 DROP_SHRINK_ALL |\
635 DROP_IDLE | \
636 DROP_RESET_ACTIVE | \
637 DROP_RESET_SEQNO | \
638 DROP_RCU)
639static int
640i915_drop_caches_get(void *data, u64 *val)
641{
642 *val = DROP_ALL;
643
644 return 0;
645}
646static int
647gt_drop_caches(struct intel_gt *gt, u64 val)
648{
649 int ret;
650
651 if (val & DROP_RESET_ACTIVE &&
652 wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT))
653 intel_gt_set_wedged(gt);
654
655 if (val & DROP_RETIRE)
656 intel_gt_retire_requests(gt);
657
658 if (val & (DROP_IDLE | DROP_ACTIVE)) {
659 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
660 if (ret)
661 return ret;
662 }
663
664 if (val & DROP_IDLE) {
665 ret = intel_gt_pm_wait_for_idle(gt);
666 if (ret)
667 return ret;
668 }
669
670 if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt))
671 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL);
672
673 if (val & DROP_FREED)
674 intel_gt_flush_buffer_pool(gt);
675
676 return 0;
677}
678
679static int
680i915_drop_caches_set(void *data, u64 val)
681{
682 struct drm_i915_private *i915 = data;
683 unsigned int flags;
684 int ret;
685
686 DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
687 val, val & DROP_ALL);
688
689 ret = gt_drop_caches(to_gt(i915), val);
690 if (ret)
691 return ret;
692
693 fs_reclaim_acquire(GFP_KERNEL);
694 flags = memalloc_noreclaim_save();
695 if (val & DROP_BOUND)
696 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND);
697
698 if (val & DROP_UNBOUND)
699 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
700
701 if (val & DROP_SHRINK_ALL)
702 i915_gem_shrink_all(i915);
703 memalloc_noreclaim_restore(flags);
704 fs_reclaim_release(GFP_KERNEL);
705
706 if (val & DROP_RCU)
707 rcu_barrier();
708
709 if (val & DROP_FREED)
710 i915_gem_drain_freed_objects(i915);
711
712 return 0;
713}
714
715DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
716 i915_drop_caches_get, i915_drop_caches_set,
717 "0x%08llx\n");
718
719static int i915_sseu_status(struct seq_file *m, void *unused)
720{
721 struct drm_i915_private *i915 = node_to_i915(m->private);
722 struct intel_gt *gt = to_gt(i915);
723
724 return intel_sseu_status(m, gt);
725}
726
727static int i915_forcewake_open(struct inode *inode, struct file *file)
728{
729 struct drm_i915_private *i915 = inode->i_private;
730
731 return intel_gt_pm_debugfs_forcewake_user_open(to_gt(i915));
732}
733
734static int i915_forcewake_release(struct inode *inode, struct file *file)
735{
736 struct drm_i915_private *i915 = inode->i_private;
737
738 return intel_gt_pm_debugfs_forcewake_user_release(to_gt(i915));
739}
740
741static const struct file_operations i915_forcewake_fops = {
742 .owner = THIS_MODULE,
743 .open = i915_forcewake_open,
744 .release = i915_forcewake_release,
745};
746
747static const struct drm_info_list i915_debugfs_list[] = {
748 {"i915_capabilities", i915_capabilities, 0},
749 {"i915_gem_objects", i915_gem_object_info, 0},
750 {"i915_frequency_info", i915_frequency_info, 0},
751 {"i915_swizzle_info", i915_swizzle_info, 0},
752 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
753 {"i915_engine_info", i915_engine_info, 0},
754 {"i915_wa_registers", i915_wa_registers, 0},
755 {"i915_sseu_status", i915_sseu_status, 0},
756 {"i915_rps_boost_info", i915_rps_boost_info, 0},
757};
758#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
759
760static const struct i915_debugfs_files {
761 const char *name;
762 const struct file_operations *fops;
763} i915_debugfs_files[] = {
764 {"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
765 {"i915_wedged", &i915_wedged_fops},
766 {"i915_gem_drop_caches", &i915_drop_caches_fops},
767#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
768 {"i915_error_state", &i915_error_state_fops},
769 {"i915_gpu_info", &i915_gpu_info_fops},
770#endif
771};
772
773void i915_debugfs_register(struct drm_i915_private *dev_priv)
774{
775 struct drm_minor *minor = dev_priv->drm.primary;
776 int i;
777
778 i915_debugfs_params(dev_priv);
779
780 debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root,
781 to_i915(minor->dev), &i915_forcewake_fops);
782 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
783 debugfs_create_file(i915_debugfs_files[i].name,
784 S_IRUGO | S_IWUSR,
785 minor->debugfs_root,
786 to_i915(minor->dev),
787 i915_debugfs_files[i].fops);
788 }
789
790 drm_debugfs_create_files(i915_debugfs_list,
791 I915_DEBUGFS_ENTRIES,
792 minor->debugfs_root, minor);
793}
794
