LXR linux/drivers/gpu/drm/i915/intel_device

   1/*
   2 * Copyright © 2016 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 *
  23 */
  24
  25#include <drm/drm_print.h>
  26#include <drm/i915_pciids.h>
  27
  28#include "display/intel_cdclk.h"
  29#include "display/intel_de.h"
  30#include "intel_device_info.h"
  31#include "i915_drv.h"
  32
  33#define PLATFORM_NAME(x) [INTEL_##x] = #x
  34static const char * const platform_names[] = {
  35        PLATFORM_NAME(I830),
  36        PLATFORM_NAME(I845G),
  37        PLATFORM_NAME(I85X),
  38        PLATFORM_NAME(I865G),
  39        PLATFORM_NAME(I915G),
  40        PLATFORM_NAME(I915GM),
  41        PLATFORM_NAME(I945G),
  42        PLATFORM_NAME(I945GM),
  43        PLATFORM_NAME(G33),
  44        PLATFORM_NAME(PINEVIEW),
  45        PLATFORM_NAME(I965G),
  46        PLATFORM_NAME(I965GM),
  47        PLATFORM_NAME(G45),
  48        PLATFORM_NAME(GM45),
  49        PLATFORM_NAME(IRONLAKE),
  50        PLATFORM_NAME(SANDYBRIDGE),
  51        PLATFORM_NAME(IVYBRIDGE),
  52        PLATFORM_NAME(VALLEYVIEW),
  53        PLATFORM_NAME(HASWELL),
  54        PLATFORM_NAME(BROADWELL),
  55        PLATFORM_NAME(CHERRYVIEW),
  56        PLATFORM_NAME(SKYLAKE),
  57        PLATFORM_NAME(BROXTON),
  58        PLATFORM_NAME(KABYLAKE),
  59        PLATFORM_NAME(GEMINILAKE),
  60        PLATFORM_NAME(COFFEELAKE),
  61        PLATFORM_NAME(COMETLAKE),
  62        PLATFORM_NAME(ICELAKE),
  63        PLATFORM_NAME(ELKHARTLAKE),
  64        PLATFORM_NAME(JASPERLAKE),
  65        PLATFORM_NAME(TIGERLAKE),
  66        PLATFORM_NAME(ROCKETLAKE),
  67        PLATFORM_NAME(DG1),
  68        PLATFORM_NAME(ALDERLAKE_S),
  69        PLATFORM_NAME(ALDERLAKE_P),
  70        PLATFORM_NAME(XEHPSDV),
  71        PLATFORM_NAME(DG2),
  72};
  73#undef PLATFORM_NAME
  74
  75const char *intel_platform_name(enum intel_platform platform)
  76{
  77        BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
  78
  79        if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
  80                         platform_names[platform] == NULL))
  81                return "<unknown>";
  82
  83        return platform_names[platform];
  84}
  85
  86void intel_device_info_print_static(const struct intel_device_info *info,
  87                                    struct drm_printer *p)
  88{
  89        if (info->graphics.rel)
  90                drm_printf(p, "graphics version: %u.%02u\n", info->graphics.ver,
  91                           info->graphics.rel);
  92        else
  93                drm_printf(p, "graphics version: %u\n", info->graphics.ver);
  94
  95        if (info->media.rel)
  96                drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel);
  97        else
  98                drm_printf(p, "media version: %u\n", info->media.ver);
  99
 100        if (info->display.rel)
 101                drm_printf(p, "display version: %u.%02u\n", info->display.ver, info->display.rel);
 102        else
 103                drm_printf(p, "display version: %u\n", info->display.ver);
 104
 105        drm_printf(p, "gt: %d\n", info->gt);
 106        drm_printf(p, "memory-regions: %x\n", info->memory_regions);
 107        drm_printf(p, "page-sizes: %x\n", info->page_sizes);
 108        drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
 109        drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);
 110        drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);
 111        drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
 112
 113#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name))
 114        DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
 115#undef PRINT_FLAG
 116
 117#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name))
 118        DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
 119#undef PRINT_FLAG
 120}
 121
 122void intel_device_info_print_runtime(const struct intel_runtime_info *info,
 123                                     struct drm_printer *p)
 124{
 125        drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
 126}
 127
 128#undef INTEL_VGA_DEVICE
 129#define INTEL_VGA_DEVICE(id, info) (id)
 130
 131static const u16 subplatform_ult_ids[] = {
 132        INTEL_HSW_ULT_GT1_IDS(0),
 133        INTEL_HSW_ULT_GT2_IDS(0),
 134        INTEL_HSW_ULT_GT3_IDS(0),
 135        INTEL_BDW_ULT_GT1_IDS(0),
 136        INTEL_BDW_ULT_GT2_IDS(0),
 137        INTEL_BDW_ULT_GT3_IDS(0),
 138        INTEL_BDW_ULT_RSVD_IDS(0),
 139        INTEL_SKL_ULT_GT1_IDS(0),
 140        INTEL_SKL_ULT_GT2_IDS(0),
 141        INTEL_SKL_ULT_GT3_IDS(0),
 142        INTEL_KBL_ULT_GT1_IDS(0),
 143        INTEL_KBL_ULT_GT2_IDS(0),
 144        INTEL_KBL_ULT_GT3_IDS(0),
 145        INTEL_CFL_U_GT2_IDS(0),
 146        INTEL_CFL_U_GT3_IDS(0),
 147        INTEL_WHL_U_GT1_IDS(0),
 148        INTEL_WHL_U_GT2_IDS(0),
 149        INTEL_WHL_U_GT3_IDS(0),
 150        INTEL_CML_U_GT1_IDS(0),
 151        INTEL_CML_U_GT2_IDS(0),
 152};
 153
 154static const u16 subplatform_ulx_ids[] = {
 155        INTEL_HSW_ULX_GT1_IDS(0),
 156        INTEL_HSW_ULX_GT2_IDS(0),
 157        INTEL_BDW_ULX_GT1_IDS(0),
 158        INTEL_BDW_ULX_GT2_IDS(0),
 159        INTEL_BDW_ULX_GT3_IDS(0),
 160        INTEL_BDW_ULX_RSVD_IDS(0),
 161        INTEL_SKL_ULX_GT1_IDS(0),
 162        INTEL_SKL_ULX_GT2_IDS(0),
 163        INTEL_KBL_ULX_GT1_IDS(0),
 164        INTEL_KBL_ULX_GT2_IDS(0),
 165        INTEL_AML_KBL_GT2_IDS(0),
 166        INTEL_AML_CFL_GT2_IDS(0),
 167};
 168
 169static const u16 subplatform_portf_ids[] = {
 170        INTEL_ICL_PORT_F_IDS(0),
 171};
 172
 173static const u16 subplatform_uy_ids[] = {
 174        INTEL_TGL_12_GT2_IDS(0),
 175};
 176
 177static const u16 subplatform_n_ids[] = {
 178        INTEL_ADLN_IDS(0),
 179};
 180
 181static const u16 subplatform_rpls_ids[] = {
 182        INTEL_RPLS_IDS(0),
 183};
 184
 185static bool find_devid(u16 id, const u16 *p, unsigned int num)
 186{
 187        for (; num; num--, p++) {
 188                if (*p == id)
 189                        return true;
 190        }
 191
 192        return false;
 193}
 194
 195void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 196{
 197        const struct intel_device_info *info = INTEL_INFO(i915);
 198        const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
 199        const unsigned int pi = __platform_mask_index(rinfo, info->platform);
 200        const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
 201        u16 devid = INTEL_DEVID(i915);
 202        u32 mask = 0;
 203
 204        /* Make sure IS_<platform> checks are working. */
 205        RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
 206
 207        /* Find and mark subplatform bits based on the PCI device id. */
 208        if (find_devid(devid, subplatform_ult_ids,
 209                       ARRAY_SIZE(subplatform_ult_ids))) {
 210                mask = BIT(INTEL_SUBPLATFORM_ULT);
 211        } else if (find_devid(devid, subplatform_ulx_ids,
 212                              ARRAY_SIZE(subplatform_ulx_ids))) {
 213                mask = BIT(INTEL_SUBPLATFORM_ULX);
 214                if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
 215                        /* ULX machines are also considered ULT. */
 216                        mask |= BIT(INTEL_SUBPLATFORM_ULT);
 217                }
 218        } else if (find_devid(devid, subplatform_portf_ids,
 219                              ARRAY_SIZE(subplatform_portf_ids))) {
 220                mask = BIT(INTEL_SUBPLATFORM_PORTF);
 221        } else if (find_devid(devid, subplatform_uy_ids,
 222                           ARRAY_SIZE(subplatform_uy_ids))) {
 223                mask = BIT(INTEL_SUBPLATFORM_UY);
 224        } else if (find_devid(devid, subplatform_n_ids,
 225                                ARRAY_SIZE(subplatform_n_ids))) {
 226                mask = BIT(INTEL_SUBPLATFORM_N);
 227        } else if (find_devid(devid, subplatform_rpls_ids,
 228                              ARRAY_SIZE(subplatform_rpls_ids))) {
 229                mask = BIT(INTEL_SUBPLATFORM_RPL_S);
 230        }
 231
 232        GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
 233
 234        RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
 235}
 236
 237/**
 238 * intel_device_info_runtime_init - initialize runtime info
 239 * @dev_priv: the i915 device
 240 *
 241 * Determine various intel_device_info fields at runtime.
 242 *
 243 * Use it when either:
 244 *   - it's judged too laborious to fill n static structures with the limit
 245 *     when a simple if statement does the job,
 246 *   - run-time checks (eg read fuse/strap registers) are needed.
 247 *
 248 * This function needs to be called:
 249 *   - after the MMIO has been setup as we are reading registers,
 250 *   - after the PCH has been detected,
 251 *   - before the first usage of the fields it can tweak.
 252 */
 253void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 254{
 255        struct intel_device_info *info = mkwrite_device_info(dev_priv);
 256        struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
 257        enum pipe pipe;
 258
 259        /* Wa_14011765242: adl-s A0,A1 */
 260        if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
 261                for_each_pipe(dev_priv, pipe)
 262                        runtime->num_scalers[pipe] = 0;
 263        else if (DISPLAY_VER(dev_priv) >= 11) {
 264                for_each_pipe(dev_priv, pipe)
 265                        runtime->num_scalers[pipe] = 2;
 266        } else if (DISPLAY_VER(dev_priv) >= 9) {
 267                runtime->num_scalers[PIPE_A] = 2;
 268                runtime->num_scalers[PIPE_B] = 2;
 269                runtime->num_scalers[PIPE_C] = 1;
 270        }
 271
 272        BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 273
 274        if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
 275                for_each_pipe(dev_priv, pipe)
 276                        runtime->num_sprites[pipe] = 4;
 277        else if (DISPLAY_VER(dev_priv) >= 11)
 278                for_each_pipe(dev_priv, pipe)
 279                        runtime->num_sprites[pipe] = 6;
 280        else if (DISPLAY_VER(dev_priv) == 10)
 281                for_each_pipe(dev_priv, pipe)
 282                        runtime->num_sprites[pipe] = 3;
 283        else if (IS_BROXTON(dev_priv)) {
 284                /*
 285                 * Skylake and Broxton currently don't expose the topmost plane as its
 286                 * use is exclusive with the legacy cursor and we only want to expose
 287                 * one of those, not both. Until we can safely expose the topmost plane
 288                 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 289                 * we don't expose the topmost plane at all to prevent ABI breakage
 290                 * down the line.
 291                 */
 292
 293                runtime->num_sprites[PIPE_A] = 2;
 294                runtime->num_sprites[PIPE_B] = 2;
 295                runtime->num_sprites[PIPE_C] = 1;
 296        } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 297                for_each_pipe(dev_priv, pipe)
 298                        runtime->num_sprites[pipe] = 2;
 299        } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
 300                for_each_pipe(dev_priv, pipe)
 301                        runtime->num_sprites[pipe] = 1;
 302        }
 303
 304        if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
 305            HAS_PCH_SPLIT(dev_priv)) {
 306                u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
 307                u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
 308
 309                /*
 310                 * SFUSE_STRAP is supposed to have a bit signalling the display
 311                 * is fused off. Unfortunately it seems that, at least in
 312                 * certain cases, fused off display means that PCH display
 313                 * reads don't land anywhere. In that case, we read 0s.
 314                 *
 315                 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 316                 * should be set when taking over after the firmware.
 317                 */
 318                if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 319                    sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 320                    (HAS_PCH_CPT(dev_priv) &&
 321                     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 322                        drm_info(&dev_priv->drm,
 323                                 "Display fused off, disabling\n");
 324                        info->display.pipe_mask = 0;
 325                        info->display.cpu_transcoder_mask = 0;
 326                        info->display.fbc_mask = 0;
 327                } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
 328                        drm_info(&dev_priv->drm, "PipeC fused off\n");
 329                        info->display.pipe_mask &= ~BIT(PIPE_C);
 330                        info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
 331                }
 332        } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
 333                u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
 334
 335                if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
 336                        info->display.pipe_mask &= ~BIT(PIPE_A);
 337                        info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
 338                        info->display.fbc_mask &= ~BIT(INTEL_FBC_A);
 339                }
 340                if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
 341                        info->display.pipe_mask &= ~BIT(PIPE_B);
 342                        info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
 343                }
 344                if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
 345                        info->display.pipe_mask &= ~BIT(PIPE_C);
 346                        info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
 347                }
 348
 349                if (DISPLAY_VER(dev_priv) >= 12 &&
 350                    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
 351                        info->display.pipe_mask &= ~BIT(PIPE_D);
 352                        info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
 353                }
 354
 355                if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
 356                        info->display.has_hdcp = 0;
 357
 358                if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
 359                        info->display.fbc_mask = 0;
 360
 361                if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
 362                        info->display.has_dmc = 0;
 363
 364                if (DISPLAY_VER(dev_priv) >= 10 &&
 365                    (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
 366                        info->display.has_dsc = 0;
 367        }
 368
 369        if (GRAPHICS_VER(dev_priv) == 6 && intel_vtd_active(dev_priv)) {
 370                drm_info(&dev_priv->drm,
 371                         "Disabling ppGTT for VT-d support\n");
 372                info->ppgtt_type = INTEL_PPGTT_NONE;
 373        }
 374
 375        runtime->rawclk_freq = intel_read_rawclk(dev_priv);
 376        drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
 377
 378        if (!HAS_DISPLAY(dev_priv)) {
 379                dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
 380                                                   DRIVER_ATOMIC);
 381                memset(&info->display, 0, sizeof(info->display));
 382                memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
 383                memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
 384        }
 385}
 386
 387void intel_driver_caps_print(const struct intel_driver_caps *caps,
 388                             struct drm_printer *p)
 389{
 390        drm_printf(p, "Has logical contexts? %s\n",
 391                   yesno(caps->has_logical_contexts));
 392        drm_printf(p, "scheduler: %x\n", caps->scheduler);
 393}
 394