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6
7#include "msm_gpu.h"
8#include "msm_gem.h"
9#include "msm_mmu.h"
10#include "msm_fence.h"
11#include "msm_gpu_trace.h"
12#include "adreno/adreno_gpu.h"
13
14#include <generated/utsrelease.h>
15#include <linux/string_helpers.h>
16#include <linux/devcoredump.h>
17#include <linux/sched/task.h>
18
19
20
21
22
23static int enable_pwrrail(struct msm_gpu *gpu)
24{
25 struct drm_device *dev = gpu->dev;
26 int ret = 0;
27
28 if (gpu->gpu_reg) {
29 ret = regulator_enable(gpu->gpu_reg);
30 if (ret) {
31 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
32 return ret;
33 }
34 }
35
36 if (gpu->gpu_cx) {
37 ret = regulator_enable(gpu->gpu_cx);
38 if (ret) {
39 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
40 return ret;
41 }
42 }
43
44 return 0;
45}
46
47static int disable_pwrrail(struct msm_gpu *gpu)
48{
49 if (gpu->gpu_cx)
50 regulator_disable(gpu->gpu_cx);
51 if (gpu->gpu_reg)
52 regulator_disable(gpu->gpu_reg);
53 return 0;
54}
55
56static int enable_clk(struct msm_gpu *gpu)
57{
58 if (gpu->core_clk && gpu->fast_rate)
59 clk_set_rate(gpu->core_clk, gpu->fast_rate);
60
61
62 if (gpu->rbbmtimer_clk)
63 clk_set_rate(gpu->rbbmtimer_clk, 19200000);
64
65 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
66}
67
68static int disable_clk(struct msm_gpu *gpu)
69{
70 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
71
72
73
74
75
76
77 if (gpu->core_clk)
78 clk_set_rate(gpu->core_clk, 27000000);
79
80 if (gpu->rbbmtimer_clk)
81 clk_set_rate(gpu->rbbmtimer_clk, 0);
82
83 return 0;
84}
85
86static int enable_axi(struct msm_gpu *gpu)
87{
88 return clk_prepare_enable(gpu->ebi1_clk);
89}
90
91static int disable_axi(struct msm_gpu *gpu)
92{
93 clk_disable_unprepare(gpu->ebi1_clk);
94 return 0;
95}
96
97int msm_gpu_pm_resume(struct msm_gpu *gpu)
98{
99 int ret;
100
101 DBG("%s", gpu->name);
102 trace_msm_gpu_resume(0);
103
104 ret = enable_pwrrail(gpu);
105 if (ret)
106 return ret;
107
108 ret = enable_clk(gpu);
109 if (ret)
110 return ret;
111
112 ret = enable_axi(gpu);
113 if (ret)
114 return ret;
115
116 msm_devfreq_resume(gpu);
117
118 gpu->needs_hw_init = true;
119
120 return 0;
121}
122
123int msm_gpu_pm_suspend(struct msm_gpu *gpu)
124{
125 int ret;
126
127 DBG("%s", gpu->name);
128 trace_msm_gpu_suspend(0);
129
130 msm_devfreq_suspend(gpu);
131
132 ret = disable_axi(gpu);
133 if (ret)
134 return ret;
135
136 ret = disable_clk(gpu);
137 if (ret)
138 return ret;
139
140 ret = disable_pwrrail(gpu);
141 if (ret)
142 return ret;
143
144 gpu->suspend_count++;
145
146 return 0;
147}
148
149int msm_gpu_hw_init(struct msm_gpu *gpu)
150{
151 int ret;
152
153 WARN_ON(!mutex_is_locked(&gpu->lock));
154
155 if (!gpu->needs_hw_init)
156 return 0;
157
158 disable_irq(gpu->irq);
159 ret = gpu->funcs->hw_init(gpu);
160 if (!ret)
161 gpu->needs_hw_init = false;
162 enable_irq(gpu->irq);
163
164 return ret;
165}
166
167static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
168 uint32_t fence)
169{
170 struct msm_gem_submit *submit;
171 unsigned long flags;
172
173 spin_lock_irqsave(&ring->submit_lock, flags);
174 list_for_each_entry(submit, &ring->submits, node) {
175 if (fence_after(submit->seqno, fence))
176 break;
177
178 msm_update_fence(submit->ring->fctx,
179 submit->hw_fence->seqno);
180 dma_fence_signal(submit->hw_fence);
181 }
182 spin_unlock_irqrestore(&ring->submit_lock, flags);
183}
184
185#ifdef CONFIG_DEV_COREDUMP
186static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
187 size_t count, void *data, size_t datalen)
188{
189 struct msm_gpu *gpu = data;
190 struct drm_print_iterator iter;
191 struct drm_printer p;
192 struct msm_gpu_state *state;
193
194 state = msm_gpu_crashstate_get(gpu);
195 if (!state)
196 return 0;
197
198 iter.data = buffer;
199 iter.offset = 0;
200 iter.start = offset;
201 iter.remain = count;
202
203 p = drm_coredump_printer(&iter);
204
205 drm_printf(&p, "---\n");
206 drm_printf(&p, "kernel: " UTS_RELEASE "\n");
207 drm_printf(&p, "module: " KBUILD_MODNAME "\n");
208 drm_printf(&p, "time: %lld.%09ld\n",
209 state->time.tv_sec, state->time.tv_nsec);
210 if (state->comm)
211 drm_printf(&p, "comm: %s\n", state->comm);
212 if (state->cmd)
213 drm_printf(&p, "cmdline: %s\n", state->cmd);
214
215 gpu->funcs->show(gpu, state, &p);
216
217 msm_gpu_crashstate_put(gpu);
218
219 return count - iter.remain;
220}
221
222static void msm_gpu_devcoredump_free(void *data)
223{
224 struct msm_gpu *gpu = data;
225
226 msm_gpu_crashstate_put(gpu);
227}
228
229static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
230 struct msm_gem_object *obj, u64 iova, u32 flags)
231{
232 struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
233
234
235 state_bo->size = obj->base.size;
236 state_bo->iova = iova;
237
238
239 if ((flags & MSM_SUBMIT_BO_READ) && !obj->base.import_attach) {
240 void *ptr;
241
242 state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL);
243 if (!state_bo->data)
244 goto out;
245
246 msm_gem_lock(&obj->base);
247 ptr = msm_gem_get_vaddr_active(&obj->base);
248 msm_gem_unlock(&obj->base);
249 if (IS_ERR(ptr)) {
250 kvfree(state_bo->data);
251 state_bo->data = NULL;
252 goto out;
253 }
254
255 memcpy(state_bo->data, ptr, obj->base.size);
256 msm_gem_put_vaddr(&obj->base);
257 }
258out:
259 state->nr_bos++;
260}
261
262static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
263 struct msm_gem_submit *submit, char *comm, char *cmd)
264{
265 struct msm_gpu_state *state;
266
267
268 if (!gpu->funcs->gpu_state_get)
269 return;
270
271
272 if (gpu->crashstate)
273 return;
274
275 state = gpu->funcs->gpu_state_get(gpu);
276 if (IS_ERR_OR_NULL(state))
277 return;
278
279
280 state->comm = kstrdup(comm, GFP_KERNEL);
281 state->cmd = kstrdup(cmd, GFP_KERNEL);
282 state->fault_info = gpu->fault_info;
283
284 if (submit) {
285 int i, nr = 0;
286
287
288 for (i = 0; i < submit->nr_bos; i++)
289 if (should_dump(submit, i))
290 nr++;
291
292 for (i = 0; i < submit->nr_cmds; i++)
293 if (!should_dump(submit, submit->cmd[i].idx))
294 nr++;
295
296 state->bos = kcalloc(nr,
297 sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
298
299 for (i = 0; state->bos && i < submit->nr_bos; i++) {
300 if (should_dump(submit, i)) {
301 msm_gpu_crashstate_get_bo(state, submit->bos[i].obj,
302 submit->bos[i].iova, submit->bos[i].flags);
303 }
304 }
305
306 for (i = 0; state->bos && i < submit->nr_cmds; i++) {
307 int idx = submit->cmd[i].idx;
308
309 if (!should_dump(submit, submit->cmd[i].idx)) {
310 msm_gpu_crashstate_get_bo(state, submit->bos[idx].obj,
311 submit->bos[idx].iova, submit->bos[idx].flags);
312 }
313 }
314 }
315
316
317 gpu->crashstate = state;
318
319
320 dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
321 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
322}
323#else
324static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
325 struct msm_gem_submit *submit, char *comm, char *cmd)
326{
327}
328#endif
329
330
331
332
333
334static struct msm_gem_submit *
335find_submit(struct msm_ringbuffer *ring, uint32_t fence)
336{
337 struct msm_gem_submit *submit;
338 unsigned long flags;
339
340 spin_lock_irqsave(&ring->submit_lock, flags);
341 list_for_each_entry(submit, &ring->submits, node) {
342 if (submit->seqno == fence) {
343 spin_unlock_irqrestore(&ring->submit_lock, flags);
344 return submit;
345 }
346 }
347 spin_unlock_irqrestore(&ring->submit_lock, flags);
348
349 return NULL;
350}
351
352static void retire_submits(struct msm_gpu *gpu);
353
354static void recover_worker(struct kthread_work *work)
355{
356 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
357 struct drm_device *dev = gpu->dev;
358 struct msm_drm_private *priv = dev->dev_private;
359 struct msm_gem_submit *submit;
360 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
361 char *comm = NULL, *cmd = NULL;
362 int i;
363
364 mutex_lock(&gpu->lock);
365
366 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
367
368 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
369 if (submit) {
370 struct task_struct *task;
371
372
373 submit->queue->faults++;
374 submit->aspace->faults++;
375
376 task = get_pid_task(submit->pid, PIDTYPE_PID);
377 if (task) {
378 comm = kstrdup(task->comm, GFP_KERNEL);
379 cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
380 put_task_struct(task);
381 }
382
383 if (comm && cmd) {
384 DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
385 gpu->name, comm, cmd);
386
387 msm_rd_dump_submit(priv->hangrd, submit,
388 "offending task: %s (%s)", comm, cmd);
389 } else {
390 msm_rd_dump_submit(priv->hangrd, submit, NULL);
391 }
392 } else {
393
394
395
396
397 gpu->global_faults++;
398 }
399
400
401 pm_runtime_get_sync(&gpu->pdev->dev);
402 msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
403 pm_runtime_put_sync(&gpu->pdev->dev);
404
405 kfree(cmd);
406 kfree(comm);
407
408
409
410
411
412
413 for (i = 0; i < gpu->nr_rings; i++) {
414 struct msm_ringbuffer *ring = gpu->rb[i];
415
416 uint32_t fence = ring->memptrs->fence;
417
418
419
420
421
422 if (ring == cur_ring)
423 fence++;
424
425 update_fences(gpu, ring, fence);
426 }
427
428 if (msm_gpu_active(gpu)) {
429
430 retire_submits(gpu);
431
432 pm_runtime_get_sync(&gpu->pdev->dev);
433 gpu->funcs->recover(gpu);
434 pm_runtime_put_sync(&gpu->pdev->dev);
435
436
437
438
439
440 for (i = 0; i < gpu->nr_rings; i++) {
441 struct msm_ringbuffer *ring = gpu->rb[i];
442 unsigned long flags;
443
444 spin_lock_irqsave(&ring->submit_lock, flags);
445 list_for_each_entry(submit, &ring->submits, node)
446 gpu->funcs->submit(gpu, submit);
447 spin_unlock_irqrestore(&ring->submit_lock, flags);
448 }
449 }
450
451 mutex_unlock(&gpu->lock);
452
453 msm_gpu_retire(gpu);
454}
455
456static void fault_worker(struct kthread_work *work)
457{
458 struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work);
459 struct msm_gem_submit *submit;
460 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
461 char *comm = NULL, *cmd = NULL;
462
463 mutex_lock(&gpu->lock);
464
465 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
466 if (submit && submit->fault_dumped)
467 goto resume_smmu;
468
469 if (submit) {
470 struct task_struct *task;
471
472 task = get_pid_task(submit->pid, PIDTYPE_PID);
473 if (task) {
474 comm = kstrdup(task->comm, GFP_KERNEL);
475 cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
476 put_task_struct(task);
477 }
478
479
480
481
482
483 submit->fault_dumped = true;
484 }
485
486
487 pm_runtime_get_sync(&gpu->pdev->dev);
488 msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
489 pm_runtime_put_sync(&gpu->pdev->dev);
490
491 kfree(cmd);
492 kfree(comm);
493
494resume_smmu:
495 memset(&gpu->fault_info, 0, sizeof(gpu->fault_info));
496 gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
497
498 mutex_unlock(&gpu->lock);
499}
500
501static void hangcheck_timer_reset(struct msm_gpu *gpu)
502{
503 struct msm_drm_private *priv = gpu->dev->dev_private;
504 mod_timer(&gpu->hangcheck_timer,
505 round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period)));
506}
507
508static void hangcheck_handler(struct timer_list *t)
509{
510 struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
511 struct drm_device *dev = gpu->dev;
512 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
513 uint32_t fence = ring->memptrs->fence;
514
515 if (fence != ring->hangcheck_fence) {
516
517 ring->hangcheck_fence = fence;
518 } else if (fence_before(fence, ring->seqno)) {
519
520 ring->hangcheck_fence = fence;
521 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
522 gpu->name, ring->id);
523 DRM_DEV_ERROR(dev->dev, "%s: completed fence: %u\n",
524 gpu->name, fence);
525 DRM_DEV_ERROR(dev->dev, "%s: submitted fence: %u\n",
526 gpu->name, ring->seqno);
527
528 kthread_queue_work(gpu->worker, &gpu->recover_work);
529 }
530
531
532 if (fence_after(ring->seqno, ring->hangcheck_fence))
533 hangcheck_timer_reset(gpu);
534
535
536 msm_gpu_retire(gpu);
537}
538
539
540
541
542
543
544static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
545{
546 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
547 int i, n = min(ncntrs, gpu->num_perfcntrs);
548
549
550 for (i = 0; i < gpu->num_perfcntrs; i++)
551 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
552
553
554 for (i = 0; i < n; i++)
555 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
556
557
558 for (i = 0; i < gpu->num_perfcntrs; i++)
559 gpu->last_cntrs[i] = current_cntrs[i];
560
561 return n;
562}
563
564static void update_sw_cntrs(struct msm_gpu *gpu)
565{
566 ktime_t time;
567 uint32_t elapsed;
568 unsigned long flags;
569
570 spin_lock_irqsave(&gpu->perf_lock, flags);
571 if (!gpu->perfcntr_active)
572 goto out;
573
574 time = ktime_get();
575 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
576
577 gpu->totaltime += elapsed;
578 if (gpu->last_sample.active)
579 gpu->activetime += elapsed;
580
581 gpu->last_sample.active = msm_gpu_active(gpu);
582 gpu->last_sample.time = time;
583
584out:
585 spin_unlock_irqrestore(&gpu->perf_lock, flags);
586}
587
588void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
589{
590 unsigned long flags;
591
592 pm_runtime_get_sync(&gpu->pdev->dev);
593
594 spin_lock_irqsave(&gpu->perf_lock, flags);
595
596 gpu->last_sample.active = msm_gpu_active(gpu);
597 gpu->last_sample.time = ktime_get();
598 gpu->activetime = gpu->totaltime = 0;
599 gpu->perfcntr_active = true;
600 update_hw_cntrs(gpu, 0, NULL);
601 spin_unlock_irqrestore(&gpu->perf_lock, flags);
602}
603
604void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
605{
606 gpu->perfcntr_active = false;
607 pm_runtime_put_sync(&gpu->pdev->dev);
608}
609
610
611int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
612 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
613{
614 unsigned long flags;
615 int ret;
616
617 spin_lock_irqsave(&gpu->perf_lock, flags);
618
619 if (!gpu->perfcntr_active) {
620 ret = -EINVAL;
621 goto out;
622 }
623
624 *activetime = gpu->activetime;
625 *totaltime = gpu->totaltime;
626
627 gpu->activetime = gpu->totaltime = 0;
628
629 ret = update_hw_cntrs(gpu, ncntrs, cntrs);
630
631out:
632 spin_unlock_irqrestore(&gpu->perf_lock, flags);
633
634 return ret;
635}
636
637
638
639
640
641static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
642 struct msm_gem_submit *submit)
643{
644 int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
645 volatile struct msm_gpu_submit_stats *stats;
646 u64 elapsed, clock = 0;
647 unsigned long flags;
648
649 stats = &ring->memptrs->stats[index];
650
651 elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
652 do_div(elapsed, 192);
653
654
655 if (elapsed) {
656 clock = (stats->cpcycles_end - stats->cpcycles_start) * 1000;
657 do_div(clock, elapsed);
658 }
659
660 trace_msm_gpu_submit_retired(submit, elapsed, clock,
661 stats->alwayson_start, stats->alwayson_end);
662
663 msm_submit_retire(submit);
664
665 pm_runtime_mark_last_busy(&gpu->pdev->dev);
666 pm_runtime_put_autosuspend(&gpu->pdev->dev);
667
668 spin_lock_irqsave(&ring->submit_lock, flags);
669 list_del(&submit->node);
670 spin_unlock_irqrestore(&ring->submit_lock, flags);
671
672
673 mutex_lock(&gpu->active_lock);
674 gpu->active_submits--;
675 WARN_ON(gpu->active_submits < 0);
676 if (!gpu->active_submits)
677 msm_devfreq_idle(gpu);
678 mutex_unlock(&gpu->active_lock);
679
680 msm_gem_submit_put(submit);
681}
682
683static void retire_submits(struct msm_gpu *gpu)
684{
685 int i;
686
687
688 for (i = 0; i < gpu->nr_rings; i++) {
689 struct msm_ringbuffer *ring = gpu->rb[i];
690
691 while (true) {
692 struct msm_gem_submit *submit = NULL;
693 unsigned long flags;
694
695 spin_lock_irqsave(&ring->submit_lock, flags);
696 submit = list_first_entry_or_null(&ring->submits,
697 struct msm_gem_submit, node);
698 spin_unlock_irqrestore(&ring->submit_lock, flags);
699
700
701
702
703
704
705 if (submit && dma_fence_is_signaled(submit->hw_fence)) {
706 retire_submit(gpu, ring, submit);
707 } else {
708 break;
709 }
710 }
711 }
712
713 wake_up_all(&gpu->retire_event);
714}
715
716static void retire_worker(struct kthread_work *work)
717{
718 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
719
720 retire_submits(gpu);
721}
722
723
724void msm_gpu_retire(struct msm_gpu *gpu)
725{
726 int i;
727
728 for (i = 0; i < gpu->nr_rings; i++)
729 update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence);
730
731 kthread_queue_work(gpu->worker, &gpu->retire_work);
732 update_sw_cntrs(gpu);
733}
734
735
736void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
737{
738 struct drm_device *dev = gpu->dev;
739 struct msm_drm_private *priv = dev->dev_private;
740 struct msm_ringbuffer *ring = submit->ring;
741 unsigned long flags;
742
743 WARN_ON(!mutex_is_locked(&gpu->lock));
744
745 pm_runtime_get_sync(&gpu->pdev->dev);
746
747 msm_gpu_hw_init(gpu);
748
749 submit->seqno = ++ring->seqno;
750
751 msm_rd_dump_submit(priv->rd, submit, NULL);
752
753 update_sw_cntrs(gpu);
754
755
756
757
758
759 msm_gem_submit_get(submit);
760
761 spin_lock_irqsave(&ring->submit_lock, flags);
762 list_add_tail(&submit->node, &ring->submits);
763 spin_unlock_irqrestore(&ring->submit_lock, flags);
764
765
766 mutex_lock(&gpu->active_lock);
767 if (!gpu->active_submits)
768 msm_devfreq_active(gpu);
769 gpu->active_submits++;
770 mutex_unlock(&gpu->active_lock);
771
772 gpu->funcs->submit(gpu, submit);
773 gpu->cur_ctx_seqno = submit->queue->ctx->seqno;
774
775 hangcheck_timer_reset(gpu);
776}
777
778
779
780
781
782static irqreturn_t irq_handler(int irq, void *data)
783{
784 struct msm_gpu *gpu = data;
785 return gpu->funcs->irq(gpu);
786}
787
788static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
789{
790 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
791
792 if (ret < 1) {
793 gpu->nr_clocks = 0;
794 return ret;
795 }
796
797 gpu->nr_clocks = ret;
798
799 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
800 gpu->nr_clocks, "core");
801
802 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
803 gpu->nr_clocks, "rbbmtimer");
804
805 return 0;
806}
807
808
809struct msm_gem_address_space *
810msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task)
811{
812 struct msm_gem_address_space *aspace = NULL;
813 if (!gpu)
814 return NULL;
815
816
817
818
819
820 if (gpu->funcs->create_private_address_space) {
821 aspace = gpu->funcs->create_private_address_space(gpu);
822 if (!IS_ERR(aspace))
823 aspace->pid = get_pid(task_pid(task));
824 }
825
826 if (IS_ERR_OR_NULL(aspace))
827 aspace = msm_gem_address_space_get(gpu->aspace);
828
829 return aspace;
830}
831
832int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
833 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
834 const char *name, struct msm_gpu_config *config)
835{
836 int i, ret, nr_rings = config->nr_rings;
837 void *memptrs;
838 uint64_t memptrs_iova;
839
840 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
841 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
842
843 gpu->dev = drm;
844 gpu->funcs = funcs;
845 gpu->name = name;
846
847 gpu->worker = kthread_create_worker(0, "gpu-worker");
848 if (IS_ERR(gpu->worker)) {
849 ret = PTR_ERR(gpu->worker);
850 gpu->worker = NULL;
851 goto fail;
852 }
853
854 sched_set_fifo_low(gpu->worker->task);
855
856 INIT_LIST_HEAD(&gpu->active_list);
857 mutex_init(&gpu->active_lock);
858 mutex_init(&gpu->lock);
859 init_waitqueue_head(&gpu->retire_event);
860 kthread_init_work(&gpu->retire_work, retire_worker);
861 kthread_init_work(&gpu->recover_work, recover_worker);
862 kthread_init_work(&gpu->fault_work, fault_worker);
863
864 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
865
866 spin_lock_init(&gpu->perf_lock);
867
868
869
870 gpu->mmio = msm_ioremap(pdev, config->ioname);
871 if (IS_ERR(gpu->mmio)) {
872 ret = PTR_ERR(gpu->mmio);
873 goto fail;
874 }
875
876
877 gpu->irq = platform_get_irq(pdev, 0);
878 if (gpu->irq < 0) {
879 ret = gpu->irq;
880 DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret);
881 goto fail;
882 }
883
884 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
885 IRQF_TRIGGER_HIGH, "gpu-irq", gpu);
886 if (ret) {
887 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
888 goto fail;
889 }
890
891 ret = get_clocks(pdev, gpu);
892 if (ret)
893 goto fail;
894
895 gpu->ebi1_clk = msm_clk_get(pdev, "bus");
896 DBG("ebi1_clk: %p", gpu->ebi1_clk);
897 if (IS_ERR(gpu->ebi1_clk))
898 gpu->ebi1_clk = NULL;
899
900
901 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
902 DBG("gpu_reg: %p", gpu->gpu_reg);
903 if (IS_ERR(gpu->gpu_reg))
904 gpu->gpu_reg = NULL;
905
906 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
907 DBG("gpu_cx: %p", gpu->gpu_cx);
908 if (IS_ERR(gpu->gpu_cx))
909 gpu->gpu_cx = NULL;
910
911 gpu->pdev = pdev;
912 platform_set_drvdata(pdev, &gpu->adreno_smmu);
913
914 msm_devfreq_init(gpu);
915
916
917 gpu->aspace = gpu->funcs->create_address_space(gpu, pdev);
918
919 if (gpu->aspace == NULL)
920 DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
921 else if (IS_ERR(gpu->aspace)) {
922 ret = PTR_ERR(gpu->aspace);
923 goto fail;
924 }
925
926 memptrs = msm_gem_kernel_new(drm,
927 sizeof(struct msm_rbmemptrs) * nr_rings,
928 check_apriv(gpu, MSM_BO_UNCACHED), gpu->aspace, &gpu->memptrs_bo,
929 &memptrs_iova);
930
931 if (IS_ERR(memptrs)) {
932 ret = PTR_ERR(memptrs);
933 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
934 goto fail;
935 }
936
937 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
938
939 if (nr_rings > ARRAY_SIZE(gpu->rb)) {
940 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
941 ARRAY_SIZE(gpu->rb));
942 nr_rings = ARRAY_SIZE(gpu->rb);
943 }
944
945
946 for (i = 0; i < nr_rings; i++) {
947 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
948
949 if (IS_ERR(gpu->rb[i])) {
950 ret = PTR_ERR(gpu->rb[i]);
951 DRM_DEV_ERROR(drm->dev,
952 "could not create ringbuffer %d: %d\n", i, ret);
953 goto fail;
954 }
955
956 memptrs += sizeof(struct msm_rbmemptrs);
957 memptrs_iova += sizeof(struct msm_rbmemptrs);
958 }
959
960 gpu->nr_rings = nr_rings;
961
962 refcount_set(&gpu->sysprof_active, 1);
963
964 return 0;
965
966fail:
967 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
968 msm_ringbuffer_destroy(gpu->rb[i]);
969 gpu->rb[i] = NULL;
970 }
971
972 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
973
974 platform_set_drvdata(pdev, NULL);
975 return ret;
976}
977
978void msm_gpu_cleanup(struct msm_gpu *gpu)
979{
980 int i;
981
982 DBG("%s", gpu->name);
983
984 WARN_ON(!list_empty(&gpu->active_list));
985
986 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
987 msm_ringbuffer_destroy(gpu->rb[i]);
988 gpu->rb[i] = NULL;
989 }
990
991 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
992
993 if (!IS_ERR_OR_NULL(gpu->aspace)) {
994 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu);
995 msm_gem_address_space_put(gpu->aspace);
996 }
997
998 if (gpu->worker) {
999 kthread_destroy_worker(gpu->worker);
1000 }
1001
1002 msm_devfreq_cleanup(gpu);
1003}
1004