LXR linux/drivers/gpu/drm/radeon/rv770

   1/*
   2 * Copyright 2011 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#ifndef __RV770_DPM_H__
  24#define __RV770_DPM_H__
  25
  26#include "radeon.h"
  27#include "rv770_smc.h"
  28
  29struct rv770_clock_registers {
  30        u32 cg_spll_func_cntl;
  31        u32 cg_spll_func_cntl_2;
  32        u32 cg_spll_func_cntl_3;
  33        u32 cg_spll_spread_spectrum;
  34        u32 cg_spll_spread_spectrum_2;
  35        u32 mpll_ad_func_cntl;
  36        u32 mpll_ad_func_cntl_2;
  37        u32 mpll_dq_func_cntl;
  38        u32 mpll_dq_func_cntl_2;
  39        u32 mclk_pwrmgt_cntl;
  40        u32 dll_cntl;
  41        u32 mpll_ss1;
  42        u32 mpll_ss2;
  43};
  44
  45struct rv730_clock_registers {
  46        u32 cg_spll_func_cntl;
  47        u32 cg_spll_func_cntl_2;
  48        u32 cg_spll_func_cntl_3;
  49        u32 cg_spll_spread_spectrum;
  50        u32 cg_spll_spread_spectrum_2;
  51        u32 mclk_pwrmgt_cntl;
  52        u32 dll_cntl;
  53        u32 mpll_func_cntl;
  54        u32 mpll_func_cntl2;
  55        u32 mpll_func_cntl3;
  56        u32 mpll_ss;
  57        u32 mpll_ss2;
  58};
  59
  60union r7xx_clock_registers {
  61        struct rv770_clock_registers rv770;
  62        struct rv730_clock_registers rv730;
  63};
  64
  65struct vddc_table_entry {
  66        u16 vddc;
  67        u8 vddc_index;
  68        u8 high_smio;
  69        u32 low_smio;
  70};
  71
  72#define MAX_NO_OF_MVDD_VALUES 2
  73#define MAX_NO_VREG_STEPS 32
  74
  75struct rv7xx_power_info {
  76        /* flags */
  77        bool mem_gddr5;
  78        bool pcie_gen2;
  79        bool dynamic_pcie_gen2;
  80        bool acpi_pcie_gen2;
  81        bool boot_in_gen2;
  82        bool voltage_control; /* vddc */
  83        bool mvdd_control;
  84        bool sclk_ss;
  85        bool mclk_ss;
  86        bool dynamic_ss;
  87        bool gfx_clock_gating;
  88        bool mg_clock_gating;
  89        bool mgcgtssm;
  90        bool power_gating;
  91        bool thermal_protection;
  92        bool display_gap;
  93        bool dcodt;
  94        bool ulps;
  95        /* registers */
  96        union r7xx_clock_registers clk_regs;
  97        u32 s0_vid_lower_smio_cntl;
  98        /* voltage */
  99        u32 vddc_mask_low;
 100        u32 mvdd_mask_low;
 101        u32 mvdd_split_frequency;
 102        u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];
 103        u16 max_vddc;
 104        u16 max_vddc_in_table;
 105        u16 min_vddc_in_table;
 106        struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS];
 107        u8 valid_vddc_entries;
 108        /* dc odt */
 109        u32 mclk_odt_threshold;
 110        u8 odt_value_0[2];
 111        u8 odt_value_1[2];
 112        /* stored values */
 113        u32 boot_sclk;
 114        u16 acpi_vddc;
 115        u32 ref_div;
 116        u32 active_auto_throttle_sources;
 117        u32 mclk_stutter_mode_threshold;
 118        u32 mclk_strobe_mode_threshold;
 119        u32 mclk_edc_enable_threshold;
 120        u32 bsp;
 121        u32 bsu;
 122        u32 pbsp;
 123        u32 pbsu;
 124        u32 dsp;
 125        u32 psp;
 126        u32 asi;
 127        u32 pasi;
 128        u32 vrc;
 129        u32 restricted_levels;
 130        u32 rlp;
 131        u32 rmp;
 132        u32 lhp;
 133        u32 lmp;
 134        /* smc offsets */
 135        u16 state_table_start;
 136        u16 soft_regs_start;
 137        u16 sram_end;
 138        /* scratch structs */
 139        RV770_SMC_STATETABLE smc_statetable;
 140};
 141
 142struct rv7xx_pl {
 143        u32 sclk;
 144        u32 mclk;
 145        u16 vddc;
 146        u16 vddci; /* eg+ only */
 147        u32 flags;
 148        enum radeon_pcie_gen pcie_gen; /* si+ only */
 149};
 150
 151struct rv7xx_ps {
 152        struct rv7xx_pl high;
 153        struct rv7xx_pl medium;
 154        struct rv7xx_pl low;
 155        bool dc_compatible;
 156};
 157
 158#define RV770_RLP_DFLT                                10
 159#define RV770_RMP_DFLT                                25
 160#define RV770_LHP_DFLT                                25
 161#define RV770_LMP_DFLT                                10
 162#define RV770_VRC_DFLT                                0x003f
 163#define RV770_ASI_DFLT                                1000
 164#define RV770_HASI_DFLT                               200000
 165#define RV770_MGCGTTLOCAL0_DFLT                       0x00100000
 166#define RV7XX_MGCGTTLOCAL0_DFLT                       0
 167#define RV770_MGCGTTLOCAL1_DFLT                       0xFFFF0000
 168#define RV770_MGCGCGTSSMCTRL_DFLT                     0x55940000
 169
 170#define MVDD_LOW_INDEX  0
 171#define MVDD_HIGH_INDEX 1
 172
 173#define MVDD_LOW_VALUE  0
 174#define MVDD_HIGH_VALUE 0xffff
 175
 176#define RV770_DEFAULT_VCLK_FREQ  53300 /* 10 khz */
 177#define RV770_DEFAULT_DCLK_FREQ  40000 /* 10 khz */
 178
 179/* rv730/rv710 */
 180int rv730_populate_sclk_value(struct radeon_device *rdev,
 181                              u32 engine_clock,
 182                              RV770_SMC_SCLK_VALUE *sclk);
 183int rv730_populate_mclk_value(struct radeon_device *rdev,
 184                              u32 engine_clock, u32 memory_clock,
 185                              LPRV7XX_SMC_MCLK_VALUE mclk);
 186void rv730_read_clock_registers(struct radeon_device *rdev);
 187int rv730_populate_smc_acpi_state(struct radeon_device *rdev,
 188                                  RV770_SMC_STATETABLE *table);
 189int rv730_populate_smc_initial_state(struct radeon_device *rdev,
 190                                     struct radeon_ps *radeon_initial_state,
 191                                     RV770_SMC_STATETABLE *table);
 192void rv730_program_memory_timing_parameters(struct radeon_device *rdev,
 193                                            struct radeon_ps *radeon_state);
 194void rv730_power_gating_enable(struct radeon_device *rdev,
 195                               bool enable);
 196void rv730_start_dpm(struct radeon_device *rdev);
 197void rv730_stop_dpm(struct radeon_device *rdev);
 198void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt);
 199void rv730_get_odt_values(struct radeon_device *rdev);
 200
 201/* rv740 */
 202int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
 203                              RV770_SMC_SCLK_VALUE *sclk);
 204int rv740_populate_mclk_value(struct radeon_device *rdev,
 205                              u32 engine_clock, u32 memory_clock,
 206                              RV7XX_SMC_MCLK_VALUE *mclk);
 207void rv740_read_clock_registers(struct radeon_device *rdev);
 208int rv740_populate_smc_acpi_state(struct radeon_device *rdev,
 209                                  RV770_SMC_STATETABLE *table);
 210void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev,
 211                                       bool enable);
 212u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
 213u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
 214u32 rv740_get_decoded_reference_divider(u32 encoded_ref);
 215
 216/* rv770 */
 217u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);
 218int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc,
 219                              RV770_SMC_VOLTAGE_VALUE *voltage);
 220int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
 221                              RV770_SMC_VOLTAGE_VALUE *voltage);
 222u8 rv770_get_seq_value(struct radeon_device *rdev,
 223                       struct rv7xx_pl *pl);
 224int rv770_populate_initial_mvdd_value(struct radeon_device *rdev,
 225                                      RV770_SMC_VOLTAGE_VALUE *voltage);
 226u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,
 227                                        u32 engine_clock);
 228void rv770_program_response_times(struct radeon_device *rdev);
 229int rv770_populate_smc_sp(struct radeon_device *rdev,
 230                          struct radeon_ps *radeon_state,
 231                          RV770_SMC_SWSTATE *smc_state);
 232int rv770_populate_smc_t(struct radeon_device *rdev,
 233                         struct radeon_ps *radeon_state,
 234                         RV770_SMC_SWSTATE *smc_state);
 235void rv770_read_voltage_smio_registers(struct radeon_device *rdev);
 236void rv770_get_memory_type(struct radeon_device *rdev);
 237void r7xx_start_smc(struct radeon_device *rdev);
 238u8 rv770_get_memory_module_index(struct radeon_device *rdev);
 239void rv770_get_max_vddc(struct radeon_device *rdev);
 240void rv770_get_pcie_gen2_status(struct radeon_device *rdev);
 241void rv770_enable_acpi_pm(struct radeon_device *rdev);
 242void rv770_restore_cgcg(struct radeon_device *rdev);
 243bool rv770_dpm_enabled(struct radeon_device *rdev);
 244void rv770_enable_voltage_control(struct radeon_device *rdev,
 245                                  bool enable);
 246void rv770_enable_backbias(struct radeon_device *rdev,
 247                           bool enable);
 248void rv770_enable_thermal_protection(struct radeon_device *rdev,
 249                                     bool enable);
 250void rv770_enable_auto_throttle_source(struct radeon_device *rdev,
 251                                       enum radeon_dpm_auto_throttle_src source,
 252                                       bool enable);
 253void rv770_setup_bsp(struct radeon_device *rdev);
 254void rv770_program_git(struct radeon_device *rdev);
 255void rv770_program_tp(struct radeon_device *rdev);
 256void rv770_program_tpp(struct radeon_device *rdev);
 257void rv770_program_sstp(struct radeon_device *rdev);
 258void rv770_program_engine_speed_parameters(struct radeon_device *rdev);
 259void rv770_program_vc(struct radeon_device *rdev);
 260void rv770_clear_vc(struct radeon_device *rdev);
 261int rv770_upload_firmware(struct radeon_device *rdev);
 262void rv770_stop_dpm(struct radeon_device *rdev);
 263void r7xx_stop_smc(struct radeon_device *rdev);
 264void rv770_reset_smio_status(struct radeon_device *rdev);
 265int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev);
 266int rv770_dpm_force_performance_level(struct radeon_device *rdev,
 267                                      enum radeon_dpm_forced_level level);
 268int rv770_halt_smc(struct radeon_device *rdev);
 269int rv770_resume_smc(struct radeon_device *rdev);
 270int rv770_set_sw_state(struct radeon_device *rdev);
 271int rv770_set_boot_state(struct radeon_device *rdev);
 272int rv7xx_parse_power_table(struct radeon_device *rdev);
 273void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
 274                                              struct radeon_ps *new_ps,
 275                                              struct radeon_ps *old_ps);
 276void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
 277                                             struct radeon_ps *new_ps,
 278                                             struct radeon_ps *old_ps);
 279void rv770_get_engine_memory_ss(struct radeon_device *rdev);
 280
 281/* smc */
 282int rv770_write_smc_soft_register(struct radeon_device *rdev,
 283                                  u16 reg_offset, u32 value);
 284
 285#endif
 286