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12#include <linux/bitops.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/slab.h>
16#include <linux/jiffies.h>
17#include <linux/i2c.h>
18#include <linux/hwmon.h>
19#include <linux/err.h>
20#include <linux/mutex.h>
21#include <linux/of.h>
22
23
24static const unsigned short normal_i2c[] = {
25 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
26
27
28#define JC42_REG_CAP 0x00
29#define JC42_REG_CONFIG 0x01
30#define JC42_REG_TEMP_UPPER 0x02
31#define JC42_REG_TEMP_LOWER 0x03
32#define JC42_REG_TEMP_CRITICAL 0x04
33#define JC42_REG_TEMP 0x05
34#define JC42_REG_MANID 0x06
35#define JC42_REG_DEVICEID 0x07
36#define JC42_REG_SMBUS 0x22
37
38
39#define JC42_ALARM_CRIT_BIT 15
40#define JC42_ALARM_MAX_BIT 14
41#define JC42_ALARM_MIN_BIT 13
42
43
44#define JC42_CFG_CRIT_ONLY (1 << 2)
45#define JC42_CFG_TCRIT_LOCK (1 << 6)
46#define JC42_CFG_EVENT_LOCK (1 << 7)
47#define JC42_CFG_SHUTDOWN (1 << 8)
48#define JC42_CFG_HYST_SHIFT 9
49#define JC42_CFG_HYST_MASK (0x03 << 9)
50
51
52#define JC42_CAP_RANGE (1 << 2)
53
54
55#define ADT_MANID 0x11d4
56#define ATMEL_MANID 0x001f
57#define ATMEL_MANID2 0x1114
58#define MAX_MANID 0x004d
59#define IDT_MANID 0x00b3
60#define MCP_MANID 0x0054
61#define NXP_MANID 0x1131
62#define ONS_MANID 0x1b09
63#define STM_MANID 0x104a
64#define GT_MANID 0x1c68
65#define GT_MANID2 0x132d
66
67
68#define SMBUS_STMOUT BIT(7)
69
70
71
72
73#define ADT7408_DEVID 0x0801
74#define ADT7408_DEVID_MASK 0xffff
75
76
77#define AT30TS00_DEVID 0x8201
78#define AT30TS00_DEVID_MASK 0xffff
79
80#define AT30TSE004_DEVID 0x2200
81#define AT30TSE004_DEVID_MASK 0xffff
82
83
84#define GT30TS00_DEVID 0x2200
85#define GT30TS00_DEVID_MASK 0xff00
86
87#define GT34TS02_DEVID 0x3300
88#define GT34TS02_DEVID_MASK 0xff00
89
90
91#define TSE2004_DEVID 0x2200
92#define TSE2004_DEVID_MASK 0xff00
93
94#define TS3000_DEVID 0x2900
95#define TS3000_DEVID_MASK 0xff00
96
97#define TS3001_DEVID 0x3000
98#define TS3001_DEVID_MASK 0xff00
99
100
101#define MAX6604_DEVID 0x3e00
102#define MAX6604_DEVID_MASK 0xffff
103
104
105#define MCP9804_DEVID 0x0200
106#define MCP9804_DEVID_MASK 0xfffc
107
108#define MCP9808_DEVID 0x0400
109#define MCP9808_DEVID_MASK 0xfffc
110
111#define MCP98242_DEVID 0x2000
112#define MCP98242_DEVID_MASK 0xfffc
113
114#define MCP98243_DEVID 0x2100
115#define MCP98243_DEVID_MASK 0xfffc
116
117#define MCP98244_DEVID 0x2200
118#define MCP98244_DEVID_MASK 0xfffc
119
120#define MCP9843_DEVID 0x0000
121#define MCP9843_DEVID_MASK 0xfffe
122
123
124#define SE97_DEVID 0xa200
125#define SE97_DEVID_MASK 0xfffc
126
127#define SE98_DEVID 0xa100
128#define SE98_DEVID_MASK 0xfffc
129
130
131#define CAT6095_DEVID 0x0800
132#define CAT6095_DEVID_MASK 0xffe0
133
134#define CAT34TS02C_DEVID 0x0a00
135#define CAT34TS02C_DEVID_MASK 0xfff0
136
137#define CAT34TS04_DEVID 0x2200
138#define CAT34TS04_DEVID_MASK 0xfff0
139
140#define N34TS04_DEVID 0x2230
141#define N34TS04_DEVID_MASK 0xfff0
142
143
144#define STTS424_DEVID 0x0101
145#define STTS424_DEVID_MASK 0xffff
146
147#define STTS424E_DEVID 0x0000
148#define STTS424E_DEVID_MASK 0xfffe
149
150#define STTS2002_DEVID 0x0300
151#define STTS2002_DEVID_MASK 0xffff
152
153#define STTS2004_DEVID 0x2201
154#define STTS2004_DEVID_MASK 0xffff
155
156#define STTS3000_DEVID 0x0200
157#define STTS3000_DEVID_MASK 0xffff
158
159static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
160
161struct jc42_chips {
162 u16 manid;
163 u16 devid;
164 u16 devid_mask;
165};
166
167static struct jc42_chips jc42_chips[] = {
168 { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
169 { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
170 { ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
171 { GT_MANID, GT30TS00_DEVID, GT30TS00_DEVID_MASK },
172 { GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK },
173 { IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
174 { IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
175 { IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
176 { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
177 { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
178 { MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK },
179 { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
180 { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
181 { MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
182 { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
183 { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
184 { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
185 { ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK },
186 { ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK },
187 { ONS_MANID, N34TS04_DEVID, N34TS04_DEVID_MASK },
188 { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
189 { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
190 { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
191 { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
192 { STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
193 { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
194};
195
196enum temp_index {
197 t_input = 0,
198 t_crit,
199 t_min,
200 t_max,
201 t_num_temp
202};
203
204static const u8 temp_regs[t_num_temp] = {
205 [t_input] = JC42_REG_TEMP,
206 [t_crit] = JC42_REG_TEMP_CRITICAL,
207 [t_min] = JC42_REG_TEMP_LOWER,
208 [t_max] = JC42_REG_TEMP_UPPER,
209};
210
211
212struct jc42_data {
213 struct i2c_client *client;
214 struct mutex update_lock;
215 bool extended;
216 bool valid;
217 unsigned long last_updated;
218 u16 orig_config;
219 u16 config;
220 u16 temp[t_num_temp];
221};
222
223#define JC42_TEMP_MIN_EXTENDED (-40000)
224#define JC42_TEMP_MIN 0
225#define JC42_TEMP_MAX 125000
226
227static u16 jc42_temp_to_reg(long temp, bool extended)
228{
229 int ntemp = clamp_val(temp,
230 extended ? JC42_TEMP_MIN_EXTENDED :
231 JC42_TEMP_MIN, JC42_TEMP_MAX);
232
233
234 return (ntemp * 2 / 125) & 0x1fff;
235}
236
237static int jc42_temp_from_reg(s16 reg)
238{
239 reg = sign_extend32(reg, 12);
240
241
242 return reg * 125 / 2;
243}
244
245static struct jc42_data *jc42_update_device(struct device *dev)
246{
247 struct jc42_data *data = dev_get_drvdata(dev);
248 struct i2c_client *client = data->client;
249 struct jc42_data *ret = data;
250 int i, val;
251
252 mutex_lock(&data->update_lock);
253
254 if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
255 for (i = 0; i < t_num_temp; i++) {
256 val = i2c_smbus_read_word_swapped(client, temp_regs[i]);
257 if (val < 0) {
258 ret = ERR_PTR(val);
259 goto abort;
260 }
261 data->temp[i] = val;
262 }
263 data->last_updated = jiffies;
264 data->valid = true;
265 }
266abort:
267 mutex_unlock(&data->update_lock);
268 return ret;
269}
270
271static int jc42_read(struct device *dev, enum hwmon_sensor_types type,
272 u32 attr, int channel, long *val)
273{
274 struct jc42_data *data = jc42_update_device(dev);
275 int temp, hyst;
276
277 if (IS_ERR(data))
278 return PTR_ERR(data);
279
280 switch (attr) {
281 case hwmon_temp_input:
282 *val = jc42_temp_from_reg(data->temp[t_input]);
283 return 0;
284 case hwmon_temp_min:
285 *val = jc42_temp_from_reg(data->temp[t_min]);
286 return 0;
287 case hwmon_temp_max:
288 *val = jc42_temp_from_reg(data->temp[t_max]);
289 return 0;
290 case hwmon_temp_crit:
291 *val = jc42_temp_from_reg(data->temp[t_crit]);
292 return 0;
293 case hwmon_temp_max_hyst:
294 temp = jc42_temp_from_reg(data->temp[t_max]);
295 hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
296 >> JC42_CFG_HYST_SHIFT];
297 *val = temp - hyst;
298 return 0;
299 case hwmon_temp_crit_hyst:
300 temp = jc42_temp_from_reg(data->temp[t_crit]);
301 hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
302 >> JC42_CFG_HYST_SHIFT];
303 *val = temp - hyst;
304 return 0;
305 case hwmon_temp_min_alarm:
306 *val = (data->temp[t_input] >> JC42_ALARM_MIN_BIT) & 1;
307 return 0;
308 case hwmon_temp_max_alarm:
309 *val = (data->temp[t_input] >> JC42_ALARM_MAX_BIT) & 1;
310 return 0;
311 case hwmon_temp_crit_alarm:
312 *val = (data->temp[t_input] >> JC42_ALARM_CRIT_BIT) & 1;
313 return 0;
314 default:
315 return -EOPNOTSUPP;
316 }
317}
318
319static int jc42_write(struct device *dev, enum hwmon_sensor_types type,
320 u32 attr, int channel, long val)
321{
322 struct jc42_data *data = dev_get_drvdata(dev);
323 struct i2c_client *client = data->client;
324 int diff, hyst;
325 int ret;
326
327 mutex_lock(&data->update_lock);
328
329 switch (attr) {
330 case hwmon_temp_min:
331 data->temp[t_min] = jc42_temp_to_reg(val, data->extended);
332 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_min],
333 data->temp[t_min]);
334 break;
335 case hwmon_temp_max:
336 data->temp[t_max] = jc42_temp_to_reg(val, data->extended);
337 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_max],
338 data->temp[t_max]);
339 break;
340 case hwmon_temp_crit:
341 data->temp[t_crit] = jc42_temp_to_reg(val, data->extended);
342 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_crit],
343 data->temp[t_crit]);
344 break;
345 case hwmon_temp_crit_hyst:
346
347
348
349
350 val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED
351 : JC42_TEMP_MIN) - 6000,
352 JC42_TEMP_MAX);
353 diff = jc42_temp_from_reg(data->temp[t_crit]) - val;
354 hyst = 0;
355 if (diff > 0) {
356 if (diff < 2250)
357 hyst = 1;
358 else if (diff < 4500)
359 hyst = 2;
360 else
361 hyst = 3;
362 }
363 data->config = (data->config & ~JC42_CFG_HYST_MASK) |
364 (hyst << JC42_CFG_HYST_SHIFT);
365 ret = i2c_smbus_write_word_swapped(data->client,
366 JC42_REG_CONFIG,
367 data->config);
368 break;
369 default:
370 ret = -EOPNOTSUPP;
371 break;
372 }
373
374 mutex_unlock(&data->update_lock);
375
376 return ret;
377}
378
379static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type,
380 u32 attr, int channel)
381{
382 const struct jc42_data *data = _data;
383 unsigned int config = data->config;
384 umode_t mode = 0444;
385
386 switch (attr) {
387 case hwmon_temp_min:
388 case hwmon_temp_max:
389 if (!(config & JC42_CFG_EVENT_LOCK))
390 mode |= 0200;
391 break;
392 case hwmon_temp_crit:
393 if (!(config & JC42_CFG_TCRIT_LOCK))
394 mode |= 0200;
395 break;
396 case hwmon_temp_crit_hyst:
397 if (!(config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK)))
398 mode |= 0200;
399 break;
400 case hwmon_temp_input:
401 case hwmon_temp_max_hyst:
402 case hwmon_temp_min_alarm:
403 case hwmon_temp_max_alarm:
404 case hwmon_temp_crit_alarm:
405 break;
406 default:
407 mode = 0;
408 break;
409 }
410 return mode;
411}
412
413
414static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info)
415{
416 struct i2c_adapter *adapter = client->adapter;
417 int i, config, cap, manid, devid;
418
419 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
420 I2C_FUNC_SMBUS_WORD_DATA))
421 return -ENODEV;
422
423 cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
424 config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
425 manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
426 devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);
427
428 if (cap < 0 || config < 0 || manid < 0 || devid < 0)
429 return -ENODEV;
430
431 if ((cap & 0xff00) || (config & 0xf800))
432 return -ENODEV;
433
434 for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
435 struct jc42_chips *chip = &jc42_chips[i];
436 if (manid == chip->manid &&
437 (devid & chip->devid_mask) == chip->devid) {
438 strlcpy(info->type, "jc42", I2C_NAME_SIZE);
439 return 0;
440 }
441 }
442 return -ENODEV;
443}
444
445static const struct hwmon_channel_info *jc42_info[] = {
446 HWMON_CHANNEL_INFO(temp,
447 HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
448 HWMON_T_CRIT | HWMON_T_MAX_HYST |
449 HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
450 HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM),
451 NULL
452};
453
454static const struct hwmon_ops jc42_hwmon_ops = {
455 .is_visible = jc42_is_visible,
456 .read = jc42_read,
457 .write = jc42_write,
458};
459
460static const struct hwmon_chip_info jc42_chip_info = {
461 .ops = &jc42_hwmon_ops,
462 .info = jc42_info,
463};
464
465static int jc42_probe(struct i2c_client *client)
466{
467 struct device *dev = &client->dev;
468 struct device *hwmon_dev;
469 struct jc42_data *data;
470 int config, cap;
471
472 data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
473 if (!data)
474 return -ENOMEM;
475
476 data->client = client;
477 i2c_set_clientdata(client, data);
478 mutex_init(&data->update_lock);
479
480 cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
481 if (cap < 0)
482 return cap;
483
484 data->extended = !!(cap & JC42_CAP_RANGE);
485
486 if (device_property_read_bool(dev, "smbus-timeout-disable")) {
487 int smbus;
488
489
490
491
492
493
494
495 smbus = i2c_smbus_read_word_swapped(client, JC42_REG_SMBUS);
496 if (smbus < 0)
497 return smbus;
498 i2c_smbus_write_word_swapped(client, JC42_REG_SMBUS,
499 smbus | SMBUS_STMOUT);
500 }
501
502 config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
503 if (config < 0)
504 return config;
505
506 data->orig_config = config;
507 if (config & JC42_CFG_SHUTDOWN) {
508 config &= ~JC42_CFG_SHUTDOWN;
509 i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
510 }
511 data->config = config;
512
513 hwmon_dev = devm_hwmon_device_register_with_info(dev, "jc42",
514 data, &jc42_chip_info,
515 NULL);
516 return PTR_ERR_OR_ZERO(hwmon_dev);
517}
518
519static int jc42_remove(struct i2c_client *client)
520{
521 struct jc42_data *data = i2c_get_clientdata(client);
522
523
524 if ((data->config & ~JC42_CFG_HYST_MASK) !=
525 (data->orig_config & ~JC42_CFG_HYST_MASK)) {
526 int config;
527
528 config = (data->orig_config & ~JC42_CFG_HYST_MASK)
529 | (data->config & JC42_CFG_HYST_MASK);
530 i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
531 }
532 return 0;
533}
534
535#ifdef CONFIG_PM
536
537static int jc42_suspend(struct device *dev)
538{
539 struct jc42_data *data = dev_get_drvdata(dev);
540
541 data->config |= JC42_CFG_SHUTDOWN;
542 i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
543 data->config);
544 return 0;
545}
546
547static int jc42_resume(struct device *dev)
548{
549 struct jc42_data *data = dev_get_drvdata(dev);
550
551 data->config &= ~JC42_CFG_SHUTDOWN;
552 i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
553 data->config);
554 return 0;
555}
556
557static const struct dev_pm_ops jc42_dev_pm_ops = {
558 .suspend = jc42_suspend,
559 .resume = jc42_resume,
560};
561
562#define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
563#else
564#define JC42_DEV_PM_OPS NULL
565#endif
566
567static const struct i2c_device_id jc42_id[] = {
568 { "jc42", 0 },
569 { }
570};
571MODULE_DEVICE_TABLE(i2c, jc42_id);
572
573#ifdef CONFIG_OF
574static const struct of_device_id jc42_of_ids[] = {
575 { .compatible = "jedec,jc-42.4-temp", },
576 { }
577};
578MODULE_DEVICE_TABLE(of, jc42_of_ids);
579#endif
580
581static struct i2c_driver jc42_driver = {
582 .class = I2C_CLASS_SPD | I2C_CLASS_HWMON,
583 .driver = {
584 .name = "jc42",
585 .pm = JC42_DEV_PM_OPS,
586 .of_match_table = of_match_ptr(jc42_of_ids),
587 },
588 .probe_new = jc42_probe,
589 .remove = jc42_remove,
590 .id_table = jc42_id,
591 .detect = jc42_detect,
592 .address_list = normal_i2c,
593};
594
595module_i2c_driver(jc42_driver);
596
597MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
598MODULE_DESCRIPTION("JC42 driver");
599MODULE_LICENSE("GPL");
600
