linux/drivers/hwmon/tmp401.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/* tmp401.c
   3 *
   4 * Copyright (C) 2007,2008 Hans de Goede <hdegoede@redhat.com>
   5 * Preliminary tmp411 support by:
   6 * Gabriel Konat, Sander Leget, Wouter Willems
   7 * Copyright (C) 2009 Andre Prendel <andre.prendel@gmx.de>
   8 *
   9 * Cleanup and support for TMP431 and TMP432 by Guenter Roeck
  10 * Copyright (c) 2013 Guenter Roeck <linux@roeck-us.net>
  11 */
  12
  13/*
  14 * Driver for the Texas Instruments TMP401 SMBUS temperature sensor IC.
  15 *
  16 * Note this IC is in some aspect similar to the LM90, but it has quite a
  17 * few differences too, for example the local temp has a higher resolution
  18 * and thus has 16 bits registers for its value and limit instead of 8 bits.
  19 */
  20
  21#include <linux/bitops.h>
  22#include <linux/err.h>
  23#include <linux/i2c.h>
  24#include <linux/hwmon.h>
  25#include <linux/init.h>
  26#include <linux/module.h>
  27#include <linux/mutex.h>
  28#include <linux/regmap.h>
  29#include <linux/slab.h>
  30
  31/* Addresses to scan */
  32static const unsigned short normal_i2c[] = { 0x48, 0x49, 0x4a, 0x4c, 0x4d,
  33        0x4e, 0x4f, I2C_CLIENT_END };
  34
  35enum chips { tmp401, tmp411, tmp431, tmp432, tmp435 };
  36
  37/*
  38 * The TMP401 registers, note some registers have different addresses for
  39 * reading and writing
  40 */
  41#define TMP401_STATUS                           0x02
  42#define TMP401_CONFIG                           0x03
  43#define TMP401_CONVERSION_RATE                  0x04
  44#define TMP401_TEMP_CRIT_HYST                   0x21
  45#define TMP401_MANUFACTURER_ID_REG              0xFE
  46#define TMP401_DEVICE_ID_REG                    0xFF
  47
  48static const u8 TMP401_TEMP_MSB[7][3] = {
  49        { 0x00, 0x01, 0x23 },   /* temp */
  50        { 0x06, 0x08, 0x16 },   /* low limit */
  51        { 0x05, 0x07, 0x15 },   /* high limit */
  52        { 0x20, 0x19, 0x1a },   /* therm (crit) limit */
  53        { 0x30, 0x34, 0x00 },   /* lowest */
  54        { 0x32, 0xf6, 0x00 },   /* highest */
  55};
  56
  57/* [0] = fault, [1] = low, [2] = high, [3] = therm/crit */
  58static const u8 TMP432_STATUS_REG[] = {
  59        0x1b, 0x36, 0x35, 0x37 };
  60
  61/* Flags */
  62#define TMP401_CONFIG_RANGE                     BIT(2)
  63#define TMP401_CONFIG_SHUTDOWN                  BIT(6)
  64#define TMP401_STATUS_LOCAL_CRIT                BIT(0)
  65#define TMP401_STATUS_REMOTE_CRIT               BIT(1)
  66#define TMP401_STATUS_REMOTE_OPEN               BIT(2)
  67#define TMP401_STATUS_REMOTE_LOW                BIT(3)
  68#define TMP401_STATUS_REMOTE_HIGH               BIT(4)
  69#define TMP401_STATUS_LOCAL_LOW                 BIT(5)
  70#define TMP401_STATUS_LOCAL_HIGH                BIT(6)
  71
  72/* On TMP432, each status has its own register */
  73#define TMP432_STATUS_LOCAL                     BIT(0)
  74#define TMP432_STATUS_REMOTE1                   BIT(1)
  75#define TMP432_STATUS_REMOTE2                   BIT(2)
  76
  77/* Manufacturer / Device ID's */
  78#define TMP401_MANUFACTURER_ID                  0x55
  79#define TMP401_DEVICE_ID                        0x11
  80#define TMP411A_DEVICE_ID                       0x12
  81#define TMP411B_DEVICE_ID                       0x13
  82#define TMP411C_DEVICE_ID                       0x10
  83#define TMP431_DEVICE_ID                        0x31
  84#define TMP432_DEVICE_ID                        0x32
  85#define TMP435_DEVICE_ID                        0x35
  86
  87/*
  88 * Driver data (common to all clients)
  89 */
  90
  91static const struct i2c_device_id tmp401_id[] = {
  92        { "tmp401", tmp401 },
  93        { "tmp411", tmp411 },
  94        { "tmp431", tmp431 },
  95        { "tmp432", tmp432 },
  96        { "tmp435", tmp435 },
  97        { }
  98};
  99MODULE_DEVICE_TABLE(i2c, tmp401_id);
 100
 101/*
 102 * Client data (each client gets its own)
 103 */
 104
 105struct tmp401_data {
 106        struct i2c_client *client;
 107        struct regmap *regmap;
 108        struct mutex update_lock;
 109        enum chips kind;
 110
 111        bool extended_range;
 112
 113        /* hwmon API configuration data */
 114        u32 chip_channel_config[4];
 115        struct hwmon_channel_info chip_info;
 116        u32 temp_channel_config[4];
 117        struct hwmon_channel_info temp_info;
 118        const struct hwmon_channel_info *info[3];
 119        struct hwmon_chip_info chip;
 120};
 121
 122/* regmap */
 123
 124static bool tmp401_regmap_is_volatile(struct device *dev, unsigned int reg)
 125{
 126        switch (reg) {
 127        case 0:                 /* local temp msb */
 128        case 1:                 /* remote temp msb */
 129        case 2:                 /* status */
 130        case 0x10:              /* remote temp lsb */
 131        case 0x15:              /* local temp lsb */
 132        case 0x1b:              /* status (tmp432) */
 133        case 0x23 ... 0x24:     /* remote temp 2 msb / lsb */
 134        case 0x30 ... 0x37:     /* lowest/highest temp; status (tmp432) */
 135                return true;
 136        default:
 137                return false;
 138        }
 139}
 140
 141static int tmp401_reg_read(void *context, unsigned int reg, unsigned int *val)
 142{
 143        struct tmp401_data *data = context;
 144        struct i2c_client *client = data->client;
 145        int regval;
 146
 147        switch (reg) {
 148        case 0:                 /* local temp msb */
 149        case 1:                 /* remote temp msb */
 150        case 5:                 /* local temp high limit msb */
 151        case 6:                 /* local temp low limit msb */
 152        case 7:                 /* remote temp ligh limit msb */
 153        case 8:                 /* remote temp low limit msb */
 154        case 0x15:              /* remote temp 2 high limit msb */
 155        case 0x16:              /* remote temp 2 low limit msb */
 156        case 0x23:              /* remote temp 2 msb */
 157        case 0x30:              /* local temp minimum, tmp411 */
 158        case 0x32:              /* local temp maximum, tmp411 */
 159        case 0x34:              /* remote temp minimum, tmp411 */
 160        case 0xf6:              /* remote temp maximum, tmp411 (really 0x36) */
 161                /* work around register overlap between TMP411 and TMP432 */
 162                if (reg == 0xf6)
 163                        reg = 0x36;
 164                regval = i2c_smbus_read_word_swapped(client, reg);
 165                if (regval < 0)
 166                        return regval;
 167                *val = regval;
 168                break;
 169        case 0x19:              /* critical limits, 8-bit registers */
 170        case 0x1a:
 171        case 0x20:
 172                regval = i2c_smbus_read_byte_data(client, reg);
 173                if (regval < 0)
 174                        return regval;
 175                *val = regval << 8;
 176                break;
 177        case 0x1b:
 178        case 0x35 ... 0x37:
 179                if (data->kind == tmp432) {
 180                        regval = i2c_smbus_read_byte_data(client, reg);
 181                        if (regval < 0)
 182                                return regval;
 183                        *val = regval;
 184                        break;
 185                }
 186                /* simulate TMP432 status registers */
 187                regval = i2c_smbus_read_byte_data(client, TMP401_STATUS);
 188                if (regval < 0)
 189                        return regval;
 190                *val = 0;
 191                switch (reg) {
 192                case 0x1b:      /* open / fault */
 193                        if (regval & TMP401_STATUS_REMOTE_OPEN)
 194                                *val |= BIT(1);
 195                        break;
 196                case 0x35:      /* high limit */
 197                        if (regval & TMP401_STATUS_LOCAL_HIGH)
 198                                *val |= BIT(0);
 199                        if (regval & TMP401_STATUS_REMOTE_HIGH)
 200                                *val |= BIT(1);
 201                        break;
 202                case 0x36:      /* low limit */
 203                        if (regval & TMP401_STATUS_LOCAL_LOW)
 204                                *val |= BIT(0);
 205                        if (regval & TMP401_STATUS_REMOTE_LOW)
 206                                *val |= BIT(1);
 207                        break;
 208                case 0x37:      /* therm / crit limit */
 209                        if (regval & TMP401_STATUS_LOCAL_CRIT)
 210                                *val |= BIT(0);
 211                        if (regval & TMP401_STATUS_REMOTE_CRIT)
 212                                *val |= BIT(1);
 213                        break;
 214                }
 215                break;
 216        default:
 217                regval = i2c_smbus_read_byte_data(client, reg);
 218                if (regval < 0)
 219                        return regval;
 220                *val = regval;
 221                break;
 222        }
 223        return 0;
 224}
 225
 226static int tmp401_reg_write(void *context, unsigned int reg, unsigned int val)
 227{
 228        struct tmp401_data *data = context;
 229        struct i2c_client *client = data->client;
 230
 231        switch (reg) {
 232        case 0x05:              /* local temp high limit msb */
 233        case 0x06:              /* local temp low limit msb */
 234        case 0x07:              /* remote temp ligh limit msb */
 235        case 0x08:              /* remote temp low limit msb */
 236                reg += 6;       /* adjust for register write address */
 237                fallthrough;
 238        case 0x15:              /* remote temp 2 high limit msb */
 239        case 0x16:              /* remote temp 2 low limit msb */
 240                return i2c_smbus_write_word_swapped(client, reg, val);
 241        case 0x19:              /* critical limits, 8-bit registers */
 242        case 0x1a:
 243        case 0x20:
 244                return i2c_smbus_write_byte_data(client, reg, val >> 8);
 245        case TMP401_CONVERSION_RATE:
 246        case TMP401_CONFIG:
 247                reg += 6;       /* adjust for register write address */
 248                fallthrough;
 249        default:
 250                return i2c_smbus_write_byte_data(client, reg, val);
 251        }
 252}
 253
 254static const struct regmap_config tmp401_regmap_config = {
 255        .reg_bits = 8,
 256        .val_bits = 16,
 257        .cache_type = REGCACHE_RBTREE,
 258        .volatile_reg = tmp401_regmap_is_volatile,
 259        .reg_read = tmp401_reg_read,
 260        .reg_write = tmp401_reg_write,
 261};
 262
 263/* temperature conversion */
 264
 265static int tmp401_register_to_temp(u16 reg, bool extended)
 266{
 267        int temp = reg;
 268
 269        if (extended)
 270                temp -= 64 * 256;
 271
 272        return DIV_ROUND_CLOSEST(temp * 125, 32);
 273}
 274
 275static u16 tmp401_temp_to_register(long temp, bool extended, int zbits)
 276{
 277        if (extended) {
 278                temp = clamp_val(temp, -64000, 191000);
 279                temp += 64000;
 280        } else {
 281                temp = clamp_val(temp, 0, 127000);
 282        }
 283
 284        return DIV_ROUND_CLOSEST(temp * (1 << (8 - zbits)), 1000) << zbits;
 285}
 286
 287/* hwmon API functions */
 288
 289static const u8 tmp401_temp_reg_index[] = {
 290        [hwmon_temp_input] = 0,
 291        [hwmon_temp_min] = 1,
 292        [hwmon_temp_max] = 2,
 293        [hwmon_temp_crit] = 3,
 294        [hwmon_temp_lowest] = 4,
 295        [hwmon_temp_highest] = 5,
 296};
 297
 298static const u8 tmp401_status_reg_index[] = {
 299        [hwmon_temp_fault] = 0,
 300        [hwmon_temp_min_alarm] = 1,
 301        [hwmon_temp_max_alarm] = 2,
 302        [hwmon_temp_crit_alarm] = 3,
 303};
 304
 305static int tmp401_temp_read(struct device *dev, u32 attr, int channel, long *val)
 306{
 307        struct tmp401_data *data = dev_get_drvdata(dev);
 308        struct regmap *regmap = data->regmap;
 309        unsigned int regval;
 310        int reg, ret;
 311
 312        switch (attr) {
 313        case hwmon_temp_input:
 314        case hwmon_temp_min:
 315        case hwmon_temp_max:
 316        case hwmon_temp_crit:
 317        case hwmon_temp_lowest:
 318        case hwmon_temp_highest:
 319                reg = TMP401_TEMP_MSB[tmp401_temp_reg_index[attr]][channel];
 320                ret = regmap_read(regmap, reg, &regval);
 321                if (ret < 0)
 322                        return ret;
 323                *val = tmp401_register_to_temp(regval, data->extended_range);
 324                break;
 325        case hwmon_temp_crit_hyst:
 326                mutex_lock(&data->update_lock);
 327                reg = TMP401_TEMP_MSB[3][channel];
 328                ret = regmap_read(regmap, reg, &regval);
 329                if (ret < 0)
 330                        goto unlock;
 331                *val = tmp401_register_to_temp(regval, data->extended_range);
 332                ret = regmap_read(regmap, TMP401_TEMP_CRIT_HYST, &regval);
 333                if (ret < 0)
 334                        goto unlock;
 335                *val -= regval * 1000;
 336unlock:
 337                mutex_unlock(&data->update_lock);
 338                if (ret < 0)
 339                        return ret;
 340                break;
 341        case hwmon_temp_fault:
 342        case hwmon_temp_min_alarm:
 343        case hwmon_temp_max_alarm:
 344        case hwmon_temp_crit_alarm:
 345                reg = TMP432_STATUS_REG[tmp401_status_reg_index[attr]];
 346                ret = regmap_read(regmap, reg, &regval);
 347                if (ret < 0)
 348                        return ret;
 349                *val = !!(regval & BIT(channel));
 350                break;
 351        default:
 352                return -EOPNOTSUPP;
 353        }
 354        return 0;
 355}
 356
 357static int tmp401_temp_write(struct device *dev, u32 attr, int channel,
 358                             long val)
 359{
 360        struct tmp401_data *data = dev_get_drvdata(dev);
 361        struct regmap *regmap = data->regmap;
 362        unsigned int regval;
 363        int reg, ret, temp;
 364
 365        mutex_lock(&data->update_lock);
 366        switch (attr) {
 367        case hwmon_temp_min:
 368        case hwmon_temp_max:
 369        case hwmon_temp_crit:
 370                reg = TMP401_TEMP_MSB[tmp401_temp_reg_index[attr]][channel];
 371                regval = tmp401_temp_to_register(val, data->extended_range,
 372                                                 attr == hwmon_temp_crit ? 8 : 4);
 373                ret = regmap_write(regmap, reg, regval);
 374                break;
 375        case hwmon_temp_crit_hyst:
 376                if (data->extended_range)
 377                        val = clamp_val(val, -64000, 191000);
 378                else
 379                        val = clamp_val(val, 0, 127000);
 380
 381                reg = TMP401_TEMP_MSB[3][channel];
 382                ret = regmap_read(regmap, reg, &regval);
 383                if (ret < 0)
 384                        break;
 385                temp = tmp401_register_to_temp(regval, data->extended_range);
 386                val = clamp_val(val, temp - 255000, temp);
 387                regval = ((temp - val) + 500) / 1000;
 388                ret = regmap_write(regmap, TMP401_TEMP_CRIT_HYST, regval);
 389                break;
 390        default:
 391                ret = -EOPNOTSUPP;
 392                break;
 393        }
 394        mutex_unlock(&data->update_lock);
 395        return ret;
 396}
 397
 398static int tmp401_chip_read(struct device *dev, u32 attr, int channel, long *val)
 399{
 400        struct tmp401_data *data = dev_get_drvdata(dev);
 401        u32 regval;
 402        int ret;
 403
 404        switch (attr) {
 405        case hwmon_chip_update_interval:
 406                ret = regmap_read(data->regmap, TMP401_CONVERSION_RATE, &regval);
 407                if (ret < 0)
 408                        return ret;
 409                *val = (1 << (7 - regval)) * 125;
 410                break;
 411        case hwmon_chip_temp_reset_history:
 412                *val = 0;
 413                break;
 414        default:
 415                return -EOPNOTSUPP;
 416        }
 417
 418        return 0;
 419}
 420
 421static int tmp401_set_convrate(struct regmap *regmap, long val)
 422{
 423        int rate;
 424
 425        /*
 426         * For valid rates, interval can be calculated as
 427         *      interval = (1 << (7 - rate)) * 125;
 428         * Rounded rate is therefore
 429         *      rate = 7 - __fls(interval * 4 / (125 * 3));
 430         * Use clamp_val() to avoid overflows, and to ensure valid input
 431         * for __fls.
 432         */
 433        val = clamp_val(val, 125, 16000);
 434        rate = 7 - __fls(val * 4 / (125 * 3));
 435        return regmap_write(regmap, TMP401_CONVERSION_RATE, rate);
 436}
 437
 438static int tmp401_chip_write(struct device *dev, u32 attr, int channel, long val)
 439{
 440        struct tmp401_data *data = dev_get_drvdata(dev);
 441        struct regmap *regmap = data->regmap;
 442        int err;
 443
 444        mutex_lock(&data->update_lock);
 445        switch (attr) {
 446        case hwmon_chip_update_interval:
 447                err = tmp401_set_convrate(regmap, val);
 448                break;
 449        case hwmon_chip_temp_reset_history:
 450                if (val != 1) {
 451                        err = -EINVAL;
 452                        break;
 453                }
 454                /*
 455                 * Reset history by writing any value to any of the
 456                 * minimum/maximum registers (0x30-0x37).
 457                 */
 458                err = regmap_write(regmap, 0x30, 0);
 459                break;
 460        default:
 461                err = -EOPNOTSUPP;
 462                break;
 463        }
 464        mutex_unlock(&data->update_lock);
 465
 466        return err;
 467}
 468
 469static int tmp401_read(struct device *dev, enum hwmon_sensor_types type,
 470                       u32 attr, int channel, long *val)
 471{
 472        switch (type) {
 473        case hwmon_chip:
 474                return tmp401_chip_read(dev, attr, channel, val);
 475        case hwmon_temp:
 476                return tmp401_temp_read(dev, attr, channel, val);
 477        default:
 478                return -EOPNOTSUPP;
 479        }
 480}
 481
 482static int tmp401_write(struct device *dev, enum hwmon_sensor_types type,
 483                        u32 attr, int channel, long val)
 484{
 485        switch (type) {
 486        case hwmon_chip:
 487                return tmp401_chip_write(dev, attr, channel, val);
 488        case hwmon_temp:
 489                return tmp401_temp_write(dev, attr, channel, val);
 490        default:
 491                return -EOPNOTSUPP;
 492        }
 493}
 494
 495static umode_t tmp401_is_visible(const void *data, enum hwmon_sensor_types type,
 496                                 u32 attr, int channel)
 497{
 498        switch (type) {
 499        case hwmon_chip:
 500                switch (attr) {
 501                case hwmon_chip_update_interval:
 502                case hwmon_chip_temp_reset_history:
 503                        return 0644;
 504                default:
 505                        break;
 506                }
 507                break;
 508        case hwmon_temp:
 509                switch (attr) {
 510                case hwmon_temp_input:
 511                case hwmon_temp_min_alarm:
 512                case hwmon_temp_max_alarm:
 513                case hwmon_temp_crit_alarm:
 514                case hwmon_temp_fault:
 515                case hwmon_temp_lowest:
 516                case hwmon_temp_highest:
 517                        return 0444;
 518                case hwmon_temp_min:
 519                case hwmon_temp_max:
 520                case hwmon_temp_crit:
 521                case hwmon_temp_crit_hyst:
 522                        return 0644;
 523                default:
 524                        break;
 525                }
 526                break;
 527        default:
 528                break;
 529        }
 530        return 0;
 531}
 532
 533static const struct hwmon_ops tmp401_ops = {
 534        .is_visible = tmp401_is_visible,
 535        .read = tmp401_read,
 536        .write = tmp401_write,
 537};
 538
 539/* chip initialization, detect, probe */
 540
 541static int tmp401_init_client(struct tmp401_data *data)
 542{
 543        struct regmap *regmap = data->regmap;
 544        u32 config, config_orig;
 545        int ret;
 546
 547        /* Set conversion rate to 2 Hz */
 548        ret = regmap_write(regmap, TMP401_CONVERSION_RATE, 5);
 549        if (ret < 0)
 550                return ret;
 551
 552        /* Start conversions (disable shutdown if necessary) */
 553        ret = regmap_read(regmap, TMP401_CONFIG, &config);
 554        if (ret < 0)
 555                return ret;
 556
 557        config_orig = config;
 558        config &= ~TMP401_CONFIG_SHUTDOWN;
 559
 560        data->extended_range = !!(config & TMP401_CONFIG_RANGE);
 561
 562        if (config != config_orig)
 563                ret = regmap_write(regmap, TMP401_CONFIG, config);
 564
 565        return ret;
 566}
 567
 568static int tmp401_detect(struct i2c_client *client,
 569                         struct i2c_board_info *info)
 570{
 571        enum chips kind;
 572        struct i2c_adapter *adapter = client->adapter;
 573        u8 reg;
 574
 575        if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
 576                return -ENODEV;
 577
 578        /* Detect and identify the chip */
 579        reg = i2c_smbus_read_byte_data(client, TMP401_MANUFACTURER_ID_REG);
 580        if (reg != TMP401_MANUFACTURER_ID)
 581                return -ENODEV;
 582
 583        reg = i2c_smbus_read_byte_data(client, TMP401_DEVICE_ID_REG);
 584
 585        switch (reg) {
 586        case TMP401_DEVICE_ID:
 587                if (client->addr != 0x4c)
 588                        return -ENODEV;
 589                kind = tmp401;
 590                break;
 591        case TMP411A_DEVICE_ID:
 592                if (client->addr != 0x4c)
 593                        return -ENODEV;
 594                kind = tmp411;
 595                break;
 596        case TMP411B_DEVICE_ID:
 597                if (client->addr != 0x4d)
 598                        return -ENODEV;
 599                kind = tmp411;
 600                break;
 601        case TMP411C_DEVICE_ID:
 602                if (client->addr != 0x4e)
 603                        return -ENODEV;
 604                kind = tmp411;
 605                break;
 606        case TMP431_DEVICE_ID:
 607                if (client->addr != 0x4c && client->addr != 0x4d)
 608                        return -ENODEV;
 609                kind = tmp431;
 610                break;
 611        case TMP432_DEVICE_ID:
 612                if (client->addr != 0x4c && client->addr != 0x4d)
 613                        return -ENODEV;
 614                kind = tmp432;
 615                break;
 616        case TMP435_DEVICE_ID:
 617                kind = tmp435;
 618                break;
 619        default:
 620                return -ENODEV;
 621        }
 622
 623        reg = i2c_smbus_read_byte_data(client, TMP401_CONFIG);
 624        if (reg & 0x1b)
 625                return -ENODEV;
 626
 627        reg = i2c_smbus_read_byte_data(client, TMP401_CONVERSION_RATE);
 628        /* Datasheet says: 0x1-0x6 */
 629        if (reg > 15)
 630                return -ENODEV;
 631
 632        strlcpy(info->type, tmp401_id[kind].name, I2C_NAME_SIZE);
 633
 634        return 0;
 635}
 636
 637static int tmp401_probe(struct i2c_client *client)
 638{
 639        static const char * const names[] = {
 640                "TMP401", "TMP411", "TMP431", "TMP432", "TMP435"
 641        };
 642        struct device *dev = &client->dev;
 643        struct hwmon_channel_info *info;
 644        struct device *hwmon_dev;
 645        struct tmp401_data *data;
 646        int status;
 647
 648        data = devm_kzalloc(dev, sizeof(struct tmp401_data), GFP_KERNEL);
 649        if (!data)
 650                return -ENOMEM;
 651
 652        data->client = client;
 653        mutex_init(&data->update_lock);
 654        data->kind = i2c_match_id(tmp401_id, client)->driver_data;
 655
 656        data->regmap = devm_regmap_init(dev, NULL, data, &tmp401_regmap_config);
 657        if (IS_ERR(data->regmap))
 658                return PTR_ERR(data->regmap);
 659
 660        /* initialize configuration data */
 661        data->chip.ops = &tmp401_ops;
 662        data->chip.info = data->info;
 663
 664        data->info[0] = &data->chip_info;
 665        data->info[1] = &data->temp_info;
 666
 667        info = &data->chip_info;
 668        info->type = hwmon_chip;
 669        info->config = data->chip_channel_config;
 670
 671        data->chip_channel_config[0] = HWMON_C_UPDATE_INTERVAL;
 672
 673        info = &data->temp_info;
 674        info->type = hwmon_temp;
 675        info->config = data->temp_channel_config;
 676
 677        data->temp_channel_config[0] = HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
 678                HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
 679                HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM;
 680        data->temp_channel_config[1] = HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
 681                HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
 682                HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_FAULT;
 683
 684        if (data->kind == tmp411) {
 685                data->temp_channel_config[0] |= HWMON_T_HIGHEST | HWMON_T_LOWEST;
 686                data->temp_channel_config[1] |= HWMON_T_HIGHEST | HWMON_T_LOWEST;
 687                data->chip_channel_config[0] |= HWMON_C_TEMP_RESET_HISTORY;
 688        }
 689
 690        if (data->kind == tmp432) {
 691                data->temp_channel_config[2] = HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
 692                        HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
 693                        HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_FAULT;
 694        }
 695
 696        /* Initialize the TMP401 chip */
 697        status = tmp401_init_client(data);
 698        if (status < 0)
 699                return status;
 700
 701        hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, data,
 702                                                         &data->chip, NULL);
 703        if (IS_ERR(hwmon_dev))
 704                return PTR_ERR(hwmon_dev);
 705
 706        dev_info(dev, "Detected TI %s chip\n", names[data->kind]);
 707
 708        return 0;
 709}
 710
 711static const struct of_device_id __maybe_unused tmp4xx_of_match[] = {
 712        { .compatible = "ti,tmp401", },
 713        { .compatible = "ti,tmp411", },
 714        { .compatible = "ti,tmp431", },
 715        { .compatible = "ti,tmp432", },
 716        { .compatible = "ti,tmp435", },
 717        { },
 718};
 719MODULE_DEVICE_TABLE(of, tmp4xx_of_match);
 720
 721static struct i2c_driver tmp401_driver = {
 722        .class          = I2C_CLASS_HWMON,
 723        .driver = {
 724                .name   = "tmp401",
 725                .of_match_table = of_match_ptr(tmp4xx_of_match),
 726        },
 727        .probe_new      = tmp401_probe,
 728        .id_table       = tmp401_id,
 729        .detect         = tmp401_detect,
 730        .address_list   = normal_i2c,
 731};
 732
 733module_i2c_driver(tmp401_driver);
 734
 735MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
 736MODULE_DESCRIPTION("Texas Instruments TMP401 temperature sensor driver");
 737MODULE_LICENSE("GPL");
 738