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8#include <linux/bitops.h>
9#include <linux/delay.h>
10#include <linux/hwspinlock.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/irqchip.h>
15#include <linux/irqchip/chained_irq.h>
16#include <linux/irqdomain.h>
17#include <linux/module.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21#include <linux/syscore_ops.h>
22
23#include <dt-bindings/interrupt-controller/arm-gic.h>
24
25#define IRQS_PER_BANK 32
26
27#define HWSPNLCK_TIMEOUT 1000
28
29struct stm32_exti_bank {
30 u32 imr_ofst;
31 u32 emr_ofst;
32 u32 rtsr_ofst;
33 u32 ftsr_ofst;
34 u32 swier_ofst;
35 u32 rpr_ofst;
36 u32 fpr_ofst;
37};
38
39#define UNDEF_REG ~0
40
41struct stm32_desc_irq {
42 u32 exti;
43 u32 irq_parent;
44 struct irq_chip *chip;
45};
46
47struct stm32_exti_drv_data {
48 const struct stm32_exti_bank **exti_banks;
49 const struct stm32_desc_irq *desc_irqs;
50 u32 bank_nr;
51 u32 irq_nr;
52};
53
54struct stm32_exti_chip_data {
55 struct stm32_exti_host_data *host_data;
56 const struct stm32_exti_bank *reg_bank;
57 struct raw_spinlock rlock;
58 u32 wake_active;
59 u32 mask_cache;
60 u32 rtsr_cache;
61 u32 ftsr_cache;
62};
63
64struct stm32_exti_host_data {
65 void __iomem *base;
66 struct stm32_exti_chip_data *chips_data;
67 const struct stm32_exti_drv_data *drv_data;
68 struct hwspinlock *hwlock;
69};
70
71static struct stm32_exti_host_data *stm32_host_data;
72
73static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
74 .imr_ofst = 0x00,
75 .emr_ofst = 0x04,
76 .rtsr_ofst = 0x08,
77 .ftsr_ofst = 0x0C,
78 .swier_ofst = 0x10,
79 .rpr_ofst = 0x14,
80 .fpr_ofst = UNDEF_REG,
81};
82
83static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
84 &stm32f4xx_exti_b1,
85};
86
87static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
88 .exti_banks = stm32f4xx_exti_banks,
89 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
90};
91
92static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
93 .imr_ofst = 0x80,
94 .emr_ofst = 0x84,
95 .rtsr_ofst = 0x00,
96 .ftsr_ofst = 0x04,
97 .swier_ofst = 0x08,
98 .rpr_ofst = 0x88,
99 .fpr_ofst = UNDEF_REG,
100};
101
102static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
103 .imr_ofst = 0x90,
104 .emr_ofst = 0x94,
105 .rtsr_ofst = 0x20,
106 .ftsr_ofst = 0x24,
107 .swier_ofst = 0x28,
108 .rpr_ofst = 0x98,
109 .fpr_ofst = UNDEF_REG,
110};
111
112static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
113 .imr_ofst = 0xA0,
114 .emr_ofst = 0xA4,
115 .rtsr_ofst = 0x40,
116 .ftsr_ofst = 0x44,
117 .swier_ofst = 0x48,
118 .rpr_ofst = 0xA8,
119 .fpr_ofst = UNDEF_REG,
120};
121
122static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
123 &stm32h7xx_exti_b1,
124 &stm32h7xx_exti_b2,
125 &stm32h7xx_exti_b3,
126};
127
128static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
129 .exti_banks = stm32h7xx_exti_banks,
130 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
131};
132
133static const struct stm32_exti_bank stm32mp1_exti_b1 = {
134 .imr_ofst = 0x80,
135 .emr_ofst = 0x84,
136 .rtsr_ofst = 0x00,
137 .ftsr_ofst = 0x04,
138 .swier_ofst = 0x08,
139 .rpr_ofst = 0x0C,
140 .fpr_ofst = 0x10,
141};
142
143static const struct stm32_exti_bank stm32mp1_exti_b2 = {
144 .imr_ofst = 0x90,
145 .emr_ofst = 0x94,
146 .rtsr_ofst = 0x20,
147 .ftsr_ofst = 0x24,
148 .swier_ofst = 0x28,
149 .rpr_ofst = 0x2C,
150 .fpr_ofst = 0x30,
151};
152
153static const struct stm32_exti_bank stm32mp1_exti_b3 = {
154 .imr_ofst = 0xA0,
155 .emr_ofst = 0xA4,
156 .rtsr_ofst = 0x40,
157 .ftsr_ofst = 0x44,
158 .swier_ofst = 0x48,
159 .rpr_ofst = 0x4C,
160 .fpr_ofst = 0x50,
161};
162
163static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
164 &stm32mp1_exti_b1,
165 &stm32mp1_exti_b2,
166 &stm32mp1_exti_b3,
167};
168
169static struct irq_chip stm32_exti_h_chip;
170static struct irq_chip stm32_exti_h_chip_direct;
171
172static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
173 { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
174 { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
175 { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
176 { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
177 { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
178 { .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip },
179 { .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip },
180 { .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip },
181 { .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip },
182 { .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip },
183 { .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip },
184 { .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip },
185 { .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip },
186 { .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip },
187 { .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip },
188 { .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip },
189 { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
190 { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
191 { .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct },
192 { .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct },
193 { .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
194 { .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct },
195 { .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct },
196 { .exti = 26, .irq_parent = 37, .chip = &stm32_exti_h_chip_direct },
197 { .exti = 27, .irq_parent = 38, .chip = &stm32_exti_h_chip_direct },
198 { .exti = 28, .irq_parent = 39, .chip = &stm32_exti_h_chip_direct },
199 { .exti = 29, .irq_parent = 71, .chip = &stm32_exti_h_chip_direct },
200 { .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct },
201 { .exti = 31, .irq_parent = 53, .chip = &stm32_exti_h_chip_direct },
202 { .exti = 32, .irq_parent = 82, .chip = &stm32_exti_h_chip_direct },
203 { .exti = 33, .irq_parent = 83, .chip = &stm32_exti_h_chip_direct },
204 { .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
205 { .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct },
206 { .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct },
207 { .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct },
208 { .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct },
209 { .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct },
210 { .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct },
211 { .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip },
212 { .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip },
213 { .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct },
214 { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip },
215};
216
217static const struct stm32_desc_irq stm32mp13_desc_irq[] = {
218 { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
219 { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
220 { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
221 { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
222 { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
223 { .exti = 5, .irq_parent = 24, .chip = &stm32_exti_h_chip },
224 { .exti = 6, .irq_parent = 65, .chip = &stm32_exti_h_chip },
225 { .exti = 7, .irq_parent = 66, .chip = &stm32_exti_h_chip },
226 { .exti = 8, .irq_parent = 67, .chip = &stm32_exti_h_chip },
227 { .exti = 9, .irq_parent = 68, .chip = &stm32_exti_h_chip },
228 { .exti = 10, .irq_parent = 41, .chip = &stm32_exti_h_chip },
229 { .exti = 11, .irq_parent = 43, .chip = &stm32_exti_h_chip },
230 { .exti = 12, .irq_parent = 77, .chip = &stm32_exti_h_chip },
231 { .exti = 13, .irq_parent = 78, .chip = &stm32_exti_h_chip },
232 { .exti = 14, .irq_parent = 106, .chip = &stm32_exti_h_chip },
233 { .exti = 15, .irq_parent = 109, .chip = &stm32_exti_h_chip },
234 { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
235 { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
236 { .exti = 21, .irq_parent = 32, .chip = &stm32_exti_h_chip_direct },
237 { .exti = 22, .irq_parent = 34, .chip = &stm32_exti_h_chip_direct },
238 { .exti = 23, .irq_parent = 73, .chip = &stm32_exti_h_chip_direct },
239 { .exti = 24, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
240 { .exti = 25, .irq_parent = 114, .chip = &stm32_exti_h_chip_direct },
241 { .exti = 26, .irq_parent = 38, .chip = &stm32_exti_h_chip_direct },
242 { .exti = 27, .irq_parent = 39, .chip = &stm32_exti_h_chip_direct },
243 { .exti = 28, .irq_parent = 40, .chip = &stm32_exti_h_chip_direct },
244 { .exti = 29, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
245 { .exti = 30, .irq_parent = 53, .chip = &stm32_exti_h_chip_direct },
246 { .exti = 31, .irq_parent = 54, .chip = &stm32_exti_h_chip_direct },
247 { .exti = 32, .irq_parent = 83, .chip = &stm32_exti_h_chip_direct },
248 { .exti = 33, .irq_parent = 84, .chip = &stm32_exti_h_chip_direct },
249 { .exti = 44, .irq_parent = 96, .chip = &stm32_exti_h_chip_direct },
250 { .exti = 47, .irq_parent = 92, .chip = &stm32_exti_h_chip_direct },
251 { .exti = 48, .irq_parent = 116, .chip = &stm32_exti_h_chip_direct },
252 { .exti = 50, .irq_parent = 117, .chip = &stm32_exti_h_chip_direct },
253 { .exti = 52, .irq_parent = 118, .chip = &stm32_exti_h_chip_direct },
254 { .exti = 53, .irq_parent = 119, .chip = &stm32_exti_h_chip_direct },
255 { .exti = 68, .irq_parent = 63, .chip = &stm32_exti_h_chip_direct },
256 { .exti = 70, .irq_parent = 98, .chip = &stm32_exti_h_chip_direct },
257};
258
259static const struct stm32_exti_drv_data stm32mp1_drv_data = {
260 .exti_banks = stm32mp1_exti_banks,
261 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
262 .desc_irqs = stm32mp1_desc_irq,
263 .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
264};
265
266static const struct stm32_exti_drv_data stm32mp13_drv_data = {
267 .exti_banks = stm32mp1_exti_banks,
268 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
269 .desc_irqs = stm32mp13_desc_irq,
270 .irq_nr = ARRAY_SIZE(stm32mp13_desc_irq),
271};
272
273static const struct
274stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data,
275 irq_hw_number_t hwirq)
276{
277 const struct stm32_desc_irq *desc = NULL;
278 int i;
279
280 if (!drv_data->desc_irqs)
281 return NULL;
282
283 for (i = 0; i < drv_data->irq_nr; i++) {
284 desc = &drv_data->desc_irqs[i];
285 if (desc->exti == hwirq)
286 break;
287 }
288
289 return desc;
290}
291
292static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
293{
294 struct stm32_exti_chip_data *chip_data = gc->private;
295 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
296 unsigned long pending;
297
298 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
299 if (stm32_bank->fpr_ofst != UNDEF_REG)
300 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
301
302 return pending;
303}
304
305static void stm32_irq_handler(struct irq_desc *desc)
306{
307 struct irq_domain *domain = irq_desc_get_handler_data(desc);
308 struct irq_chip *chip = irq_desc_get_chip(desc);
309 unsigned int nbanks = domain->gc->num_chips;
310 struct irq_chip_generic *gc;
311 unsigned long pending;
312 int n, i, irq_base = 0;
313
314 chained_irq_enter(chip, desc);
315
316 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
317 gc = irq_get_domain_generic_chip(domain, irq_base);
318
319 while ((pending = stm32_exti_pending(gc))) {
320 for_each_set_bit(n, &pending, IRQS_PER_BANK)
321 generic_handle_domain_irq(domain, irq_base + n);
322 }
323 }
324
325 chained_irq_exit(chip, desc);
326}
327
328static int stm32_exti_set_type(struct irq_data *d,
329 unsigned int type, u32 *rtsr, u32 *ftsr)
330{
331 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
332
333 switch (type) {
334 case IRQ_TYPE_EDGE_RISING:
335 *rtsr |= mask;
336 *ftsr &= ~mask;
337 break;
338 case IRQ_TYPE_EDGE_FALLING:
339 *rtsr &= ~mask;
340 *ftsr |= mask;
341 break;
342 case IRQ_TYPE_EDGE_BOTH:
343 *rtsr |= mask;
344 *ftsr |= mask;
345 break;
346 default:
347 return -EINVAL;
348 }
349
350 return 0;
351}
352
353static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
354{
355 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
356 struct stm32_exti_chip_data *chip_data = gc->private;
357 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
358 struct hwspinlock *hwlock = chip_data->host_data->hwlock;
359 u32 rtsr, ftsr;
360 int err;
361
362 irq_gc_lock(gc);
363
364 if (hwlock) {
365 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
366 if (err) {
367 pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
368 goto unlock;
369 }
370 }
371
372 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
373 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
374
375 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
376 if (err)
377 goto unspinlock;
378
379 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
380 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
381
382unspinlock:
383 if (hwlock)
384 hwspin_unlock_in_atomic(hwlock);
385unlock:
386 irq_gc_unlock(gc);
387
388 return err;
389}
390
391static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
392 u32 wake_active)
393{
394 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
395 void __iomem *base = chip_data->host_data->base;
396
397
398 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
399 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
400
401 writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
402}
403
404static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
405 u32 mask_cache)
406{
407 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
408 void __iomem *base = chip_data->host_data->base;
409
410
411 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
412 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
413
414 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
415}
416
417static void stm32_irq_suspend(struct irq_chip_generic *gc)
418{
419 struct stm32_exti_chip_data *chip_data = gc->private;
420
421 irq_gc_lock(gc);
422 stm32_chip_suspend(chip_data, gc->wake_active);
423 irq_gc_unlock(gc);
424}
425
426static void stm32_irq_resume(struct irq_chip_generic *gc)
427{
428 struct stm32_exti_chip_data *chip_data = gc->private;
429
430 irq_gc_lock(gc);
431 stm32_chip_resume(chip_data, gc->mask_cache);
432 irq_gc_unlock(gc);
433}
434
435static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
436 unsigned int nr_irqs, void *data)
437{
438 struct irq_fwspec *fwspec = data;
439 irq_hw_number_t hwirq;
440
441 hwirq = fwspec->param[0];
442
443 irq_map_generic_chip(d, virq, hwirq);
444
445 return 0;
446}
447
448static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
449 unsigned int nr_irqs)
450{
451 struct irq_data *data = irq_domain_get_irq_data(d, virq);
452
453 irq_domain_reset_irq_data(data);
454}
455
456static const struct irq_domain_ops irq_exti_domain_ops = {
457 .map = irq_map_generic_chip,
458 .alloc = stm32_exti_alloc,
459 .free = stm32_exti_free,
460};
461
462static void stm32_irq_ack(struct irq_data *d)
463{
464 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
465 struct stm32_exti_chip_data *chip_data = gc->private;
466 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
467
468 irq_gc_lock(gc);
469
470 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
471 if (stm32_bank->fpr_ofst != UNDEF_REG)
472 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
473
474 irq_gc_unlock(gc);
475}
476
477
478static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
479{
480 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
481 void __iomem *base = chip_data->host_data->base;
482 u32 val = BIT(d->hwirq % IRQS_PER_BANK);
483
484 writel_relaxed(val, base + reg);
485}
486
487static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
488{
489 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
490 void __iomem *base = chip_data->host_data->base;
491 u32 val;
492
493 val = readl_relaxed(base + reg);
494 val |= BIT(d->hwirq % IRQS_PER_BANK);
495 writel_relaxed(val, base + reg);
496
497 return val;
498}
499
500static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
501{
502 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
503 void __iomem *base = chip_data->host_data->base;
504 u32 val;
505
506 val = readl_relaxed(base + reg);
507 val &= ~BIT(d->hwirq % IRQS_PER_BANK);
508 writel_relaxed(val, base + reg);
509
510 return val;
511}
512
513static void stm32_exti_h_eoi(struct irq_data *d)
514{
515 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
516 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
517
518 raw_spin_lock(&chip_data->rlock);
519
520 stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
521 if (stm32_bank->fpr_ofst != UNDEF_REG)
522 stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
523
524 raw_spin_unlock(&chip_data->rlock);
525
526 if (d->parent_data->chip)
527 irq_chip_eoi_parent(d);
528}
529
530static void stm32_exti_h_mask(struct irq_data *d)
531{
532 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
533 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
534
535 raw_spin_lock(&chip_data->rlock);
536 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
537 raw_spin_unlock(&chip_data->rlock);
538
539 if (d->parent_data->chip)
540 irq_chip_mask_parent(d);
541}
542
543static void stm32_exti_h_unmask(struct irq_data *d)
544{
545 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
546 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
547
548 raw_spin_lock(&chip_data->rlock);
549 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
550 raw_spin_unlock(&chip_data->rlock);
551
552 if (d->parent_data->chip)
553 irq_chip_unmask_parent(d);
554}
555
556static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
557{
558 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
559 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
560 struct hwspinlock *hwlock = chip_data->host_data->hwlock;
561 void __iomem *base = chip_data->host_data->base;
562 u32 rtsr, ftsr;
563 int err;
564
565 raw_spin_lock(&chip_data->rlock);
566
567 if (hwlock) {
568 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
569 if (err) {
570 pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
571 goto unlock;
572 }
573 }
574
575 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
576 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
577
578 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
579 if (err)
580 goto unspinlock;
581
582 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
583 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
584
585unspinlock:
586 if (hwlock)
587 hwspin_unlock_in_atomic(hwlock);
588unlock:
589 raw_spin_unlock(&chip_data->rlock);
590
591 return err;
592}
593
594static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
595{
596 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
597 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
598
599 raw_spin_lock(&chip_data->rlock);
600
601 if (on)
602 chip_data->wake_active |= mask;
603 else
604 chip_data->wake_active &= ~mask;
605
606 raw_spin_unlock(&chip_data->rlock);
607
608 return 0;
609}
610
611static int stm32_exti_h_set_affinity(struct irq_data *d,
612 const struct cpumask *dest, bool force)
613{
614 if (d->parent_data->chip)
615 return irq_chip_set_affinity_parent(d, dest, force);
616
617 return -EINVAL;
618}
619
620static int __maybe_unused stm32_exti_h_suspend(void)
621{
622 struct stm32_exti_chip_data *chip_data;
623 int i;
624
625 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
626 chip_data = &stm32_host_data->chips_data[i];
627 raw_spin_lock(&chip_data->rlock);
628 stm32_chip_suspend(chip_data, chip_data->wake_active);
629 raw_spin_unlock(&chip_data->rlock);
630 }
631
632 return 0;
633}
634
635static void __maybe_unused stm32_exti_h_resume(void)
636{
637 struct stm32_exti_chip_data *chip_data;
638 int i;
639
640 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
641 chip_data = &stm32_host_data->chips_data[i];
642 raw_spin_lock(&chip_data->rlock);
643 stm32_chip_resume(chip_data, chip_data->mask_cache);
644 raw_spin_unlock(&chip_data->rlock);
645 }
646}
647
648static struct syscore_ops stm32_exti_h_syscore_ops = {
649#ifdef CONFIG_PM_SLEEP
650 .suspend = stm32_exti_h_suspend,
651 .resume = stm32_exti_h_resume,
652#endif
653};
654
655static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data)
656{
657 stm32_host_data = host_data;
658 register_syscore_ops(&stm32_exti_h_syscore_ops);
659}
660
661static void stm32_exti_h_syscore_deinit(void)
662{
663 unregister_syscore_ops(&stm32_exti_h_syscore_ops);
664}
665
666static int stm32_exti_h_retrigger(struct irq_data *d)
667{
668 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
669 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
670 void __iomem *base = chip_data->host_data->base;
671 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
672
673 writel_relaxed(mask, base + stm32_bank->swier_ofst);
674
675 return 0;
676}
677
678static struct irq_chip stm32_exti_h_chip = {
679 .name = "stm32-exti-h",
680 .irq_eoi = stm32_exti_h_eoi,
681 .irq_mask = stm32_exti_h_mask,
682 .irq_unmask = stm32_exti_h_unmask,
683 .irq_retrigger = stm32_exti_h_retrigger,
684 .irq_set_type = stm32_exti_h_set_type,
685 .irq_set_wake = stm32_exti_h_set_wake,
686 .flags = IRQCHIP_MASK_ON_SUSPEND,
687 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
688};
689
690static struct irq_chip stm32_exti_h_chip_direct = {
691 .name = "stm32-exti-h-direct",
692 .irq_eoi = irq_chip_eoi_parent,
693 .irq_ack = irq_chip_ack_parent,
694 .irq_mask = irq_chip_mask_parent,
695 .irq_unmask = irq_chip_unmask_parent,
696 .irq_retrigger = irq_chip_retrigger_hierarchy,
697 .irq_set_type = irq_chip_set_type_parent,
698 .irq_set_wake = stm32_exti_h_set_wake,
699 .flags = IRQCHIP_MASK_ON_SUSPEND,
700 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
701};
702
703static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
704 unsigned int virq,
705 unsigned int nr_irqs, void *data)
706{
707 struct stm32_exti_host_data *host_data = dm->host_data;
708 struct stm32_exti_chip_data *chip_data;
709 const struct stm32_desc_irq *desc;
710 struct irq_fwspec *fwspec = data;
711 struct irq_fwspec p_fwspec;
712 irq_hw_number_t hwirq;
713 int bank;
714
715 hwirq = fwspec->param[0];
716 bank = hwirq / IRQS_PER_BANK;
717 chip_data = &host_data->chips_data[bank];
718
719
720 desc = stm32_exti_get_desc(host_data->drv_data, hwirq);
721 if (!desc)
722 return -EINVAL;
723
724 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip,
725 chip_data);
726 if (desc->irq_parent) {
727 p_fwspec.fwnode = dm->parent->fwnode;
728 p_fwspec.param_count = 3;
729 p_fwspec.param[0] = GIC_SPI;
730 p_fwspec.param[1] = desc->irq_parent;
731 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
732
733 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
734 }
735
736 return 0;
737}
738
739static struct
740stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
741 struct device_node *node)
742{
743 struct stm32_exti_host_data *host_data;
744
745 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
746 if (!host_data)
747 return NULL;
748
749 host_data->drv_data = dd;
750 host_data->chips_data = kcalloc(dd->bank_nr,
751 sizeof(struct stm32_exti_chip_data),
752 GFP_KERNEL);
753 if (!host_data->chips_data)
754 goto free_host_data;
755
756 host_data->base = of_iomap(node, 0);
757 if (!host_data->base) {
758 pr_err("%pOF: Unable to map registers\n", node);
759 goto free_chips_data;
760 }
761
762 stm32_host_data = host_data;
763
764 return host_data;
765
766free_chips_data:
767 kfree(host_data->chips_data);
768free_host_data:
769 kfree(host_data);
770
771 return NULL;
772}
773
774static struct
775stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
776 u32 bank_idx,
777 struct device_node *node)
778{
779 const struct stm32_exti_bank *stm32_bank;
780 struct stm32_exti_chip_data *chip_data;
781 void __iomem *base = h_data->base;
782
783 stm32_bank = h_data->drv_data->exti_banks[bank_idx];
784 chip_data = &h_data->chips_data[bank_idx];
785 chip_data->host_data = h_data;
786 chip_data->reg_bank = stm32_bank;
787
788 raw_spin_lock_init(&chip_data->rlock);
789
790
791
792
793
794 writel_relaxed(0, base + stm32_bank->imr_ofst);
795 writel_relaxed(0, base + stm32_bank->emr_ofst);
796
797 pr_info("%pOF: bank%d\n", node, bank_idx);
798
799 return chip_data;
800}
801
802static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
803 struct device_node *node)
804{
805 struct stm32_exti_host_data *host_data;
806 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
807 int nr_irqs, ret, i;
808 struct irq_chip_generic *gc;
809 struct irq_domain *domain;
810
811 host_data = stm32_exti_host_init(drv_data, node);
812 if (!host_data)
813 return -ENOMEM;
814
815 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
816 &irq_exti_domain_ops, NULL);
817 if (!domain) {
818 pr_err("%pOFn: Could not register interrupt domain.\n",
819 node);
820 ret = -ENOMEM;
821 goto out_unmap;
822 }
823
824 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
825 handle_edge_irq, clr, 0, 0);
826 if (ret) {
827 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
828 node);
829 goto out_free_domain;
830 }
831
832 for (i = 0; i < drv_data->bank_nr; i++) {
833 const struct stm32_exti_bank *stm32_bank;
834 struct stm32_exti_chip_data *chip_data;
835
836 stm32_bank = drv_data->exti_banks[i];
837 chip_data = stm32_exti_chip_init(host_data, i, node);
838
839 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
840
841 gc->reg_base = host_data->base;
842 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
843 gc->chip_types->chip.irq_ack = stm32_irq_ack;
844 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
845 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
846 gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
847 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
848 gc->suspend = stm32_irq_suspend;
849 gc->resume = stm32_irq_resume;
850 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
851
852 gc->chip_types->regs.mask = stm32_bank->imr_ofst;
853 gc->private = (void *)chip_data;
854 }
855
856 nr_irqs = of_irq_count(node);
857 for (i = 0; i < nr_irqs; i++) {
858 unsigned int irq = irq_of_parse_and_map(node, i);
859
860 irq_set_handler_data(irq, domain);
861 irq_set_chained_handler(irq, stm32_irq_handler);
862 }
863
864 return 0;
865
866out_free_domain:
867 irq_domain_remove(domain);
868out_unmap:
869 iounmap(host_data->base);
870 kfree(host_data->chips_data);
871 kfree(host_data);
872 return ret;
873}
874
875static const struct irq_domain_ops stm32_exti_h_domain_ops = {
876 .alloc = stm32_exti_h_domain_alloc,
877 .free = irq_domain_free_irqs_common,
878 .xlate = irq_domain_xlate_twocell,
879};
880
881static void stm32_exti_remove_irq(void *data)
882{
883 struct irq_domain *domain = data;
884
885 irq_domain_remove(domain);
886}
887
888static int stm32_exti_remove(struct platform_device *pdev)
889{
890 stm32_exti_h_syscore_deinit();
891 return 0;
892}
893
894static int stm32_exti_probe(struct platform_device *pdev)
895{
896 int ret, i;
897 struct device *dev = &pdev->dev;
898 struct device_node *np = dev->of_node;
899 struct irq_domain *parent_domain, *domain;
900 struct stm32_exti_host_data *host_data;
901 const struct stm32_exti_drv_data *drv_data;
902
903 host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
904 if (!host_data)
905 return -ENOMEM;
906
907
908 ret = of_hwspin_lock_get_id(np, 0);
909 if (ret == -EPROBE_DEFER)
910
911 return ret;
912
913 if (ret >= 0) {
914 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
915 if (!host_data->hwlock) {
916 dev_err(dev, "Failed to request hwspinlock\n");
917 return -EINVAL;
918 }
919 } else if (ret != -ENOENT) {
920
921 dev_err(dev, "Failed to get hwspinlock\n");
922 return ret;
923 }
924
925
926 drv_data = of_device_get_match_data(dev);
927 if (!drv_data) {
928 dev_err(dev, "no of match data\n");
929 return -ENODEV;
930 }
931 host_data->drv_data = drv_data;
932
933 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr,
934 sizeof(*host_data->chips_data),
935 GFP_KERNEL);
936 if (!host_data->chips_data)
937 return -ENOMEM;
938
939 host_data->base = devm_platform_ioremap_resource(pdev, 0);
940 if (IS_ERR(host_data->base))
941 return PTR_ERR(host_data->base);
942
943 for (i = 0; i < drv_data->bank_nr; i++)
944 stm32_exti_chip_init(host_data, i, np);
945
946 parent_domain = irq_find_host(of_irq_find_parent(np));
947 if (!parent_domain) {
948 dev_err(dev, "GIC interrupt-parent not found\n");
949 return -EINVAL;
950 }
951
952 domain = irq_domain_add_hierarchy(parent_domain, 0,
953 drv_data->bank_nr * IRQS_PER_BANK,
954 np, &stm32_exti_h_domain_ops,
955 host_data);
956
957 if (!domain) {
958 dev_err(dev, "Could not register exti domain\n");
959 return -ENOMEM;
960 }
961
962 ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain);
963 if (ret)
964 return ret;
965
966 stm32_exti_h_syscore_init(host_data);
967
968 return 0;
969}
970
971
972static const struct of_device_id stm32_exti_ids[] = {
973 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
974 { .compatible = "st,stm32mp13-exti", .data = &stm32mp13_drv_data},
975 {},
976};
977MODULE_DEVICE_TABLE(of, stm32_exti_ids);
978
979static struct platform_driver stm32_exti_driver = {
980 .probe = stm32_exti_probe,
981 .remove = stm32_exti_remove,
982 .driver = {
983 .name = "stm32_exti",
984 .of_match_table = stm32_exti_ids,
985 },
986};
987
988static int __init stm32_exti_arch_init(void)
989{
990 return platform_driver_register(&stm32_exti_driver);
991}
992
993static void __exit stm32_exti_arch_exit(void)
994{
995 return platform_driver_unregister(&stm32_exti_driver);
996}
997
998arch_initcall(stm32_exti_arch_init);
999module_exit(stm32_exti_arch_exit);
1000
1001
1002static int __init stm32f4_exti_of_init(struct device_node *np,
1003 struct device_node *parent)
1004{
1005 return stm32_exti_init(&stm32f4xx_drv_data, np);
1006}
1007
1008IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
1009
1010static int __init stm32h7_exti_of_init(struct device_node *np,
1011 struct device_node *parent)
1012{
1013 return stm32_exti_init(&stm32h7xx_drv_data, np);
1014}
1015
1016IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
1017
