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6#include <linux/init.h>
7#include <linux/interconnect.h>
8#include <linux/ioctl.h>
9#include <linux/list.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/of_address.h>
14#include <linux/platform_device.h>
15#include <linux/delay.h>
16#include <linux/rational.h>
17#include <linux/time64.h>
18#include <media/videobuf2-v4l2.h>
19#include <media/videobuf2-dma-contig.h>
20#include <linux/videodev2.h>
21#include "vpu.h"
22#include "vpu_rpc.h"
23#include "vpu_defs.h"
24#include "vpu_helpers.h"
25#include "vpu_v4l2.h"
26#include "vpu_cmds.h"
27#include "vpu_imx8q.h"
28#include "vpu_malone.h"
29
30#define CMD_SIZE 25600
31#define MSG_SIZE 25600
32#define CODEC_SIZE 0x1000
33#define JPEG_SIZE 0x1000
34#define SEQ_SIZE 0x1000
35#define GOP_SIZE 0x1000
36#define PIC_SIZE 0x1000
37#define QMETER_SIZE 0x1000
38#define DBGLOG_SIZE 0x10000
39#define DEBUG_SIZE 0x80000
40#define ENG_SIZE 0x1000
41#define MALONE_SKIPPED_FRAME_ID 0x555
42
43#define MALONE_ALIGN_MBI 0x800
44#define MALONE_DCP_CHUNK_BIT 16
45#define MALONE_DCP_SIZE_MAX 0x3000000
46#define MALONE_DCP_SIZE_MIN 0x100000
47#define MALONE_DCP_FIXED_MB_ALLOC 250
48
49#define CONFIG_SET(val, cfg, pos, mask) \
50 (*(cfg) |= (((val) << (pos)) & (mask)))
51
52#define STREAM_CONFIG_FORMAT_SET(x, y) CONFIG_SET(x, y, 0, 0x0000000F)
53#define STREAM_CONFIG_STRBUFIDX_SET(x, y) CONFIG_SET(x, y, 8, 0x00000300)
54#define STREAM_CONFIG_NOSEQ_SET(x, y) CONFIG_SET(x, y, 10, 0x00000400)
55#define STREAM_CONFIG_DEBLOCK_SET(x, y) CONFIG_SET(x, y, 11, 0x00000800)
56#define STREAM_CONFIG_DERING_SET(x, y) CONFIG_SET(x, y, 12, 0x00001000)
57#define STREAM_CONFIG_IBWAIT_SET(x, y) CONFIG_SET(x, y, 13, 0x00002000)
58#define STREAM_CONFIG_FBC_SET(x, y) CONFIG_SET(x, y, 14, 0x00004000)
59#define STREAM_CONFIG_PLAY_MODE_SET(x, y) CONFIG_SET(x, y, 16, 0x00030000)
60#define STREAM_CONFIG_ENABLE_DCP_SET(x, y) CONFIG_SET(x, y, 20, 0x00100000)
61#define STREAM_CONFIG_NUM_STR_BUF_SET(x, y) CONFIG_SET(x, y, 21, 0x00600000)
62#define STREAM_CONFIG_MALONE_USAGE_SET(x, y) CONFIG_SET(x, y, 23, 0x01800000)
63#define STREAM_CONFIG_MULTI_VID_SET(x, y) CONFIG_SET(x, y, 25, 0x02000000)
64#define STREAM_CONFIG_OBFUSC_EN_SET(x, y) CONFIG_SET(x, y, 26, 0x04000000)
65#define STREAM_CONFIG_RC4_EN_SET(x, y) CONFIG_SET(x, y, 27, 0x08000000)
66#define STREAM_CONFIG_MCX_SET(x, y) CONFIG_SET(x, y, 28, 0x10000000)
67#define STREAM_CONFIG_PES_SET(x, y) CONFIG_SET(x, y, 29, 0x20000000)
68#define STREAM_CONFIG_NUM_DBE_SET(x, y) CONFIG_SET(x, y, 30, 0x40000000)
69#define STREAM_CONFIG_FS_CTRL_MODE_SET(x, y) CONFIG_SET(x, y, 31, 0x80000000)
70
71enum vpu_malone_stream_input_mode {
72 INVALID_MODE = 0,
73 FRAME_LVL,
74 NON_FRAME_LVL
75};
76
77enum vpu_malone_format {
78 MALONE_FMT_NULL = 0x0,
79 MALONE_FMT_AVC = 0x1,
80 MALONE_FMT_MP2 = 0x2,
81 MALONE_FMT_VC1 = 0x3,
82 MALONE_FMT_AVS = 0x4,
83 MALONE_FMT_ASP = 0x5,
84 MALONE_FMT_JPG = 0x6,
85 MALONE_FMT_RV = 0x7,
86 MALONE_FMT_VP6 = 0x8,
87 MALONE_FMT_SPK = 0x9,
88 MALONE_FMT_VP8 = 0xA,
89 MALONE_FMT_HEVC = 0xB,
90 MALONE_FMT_LAST = MALONE_FMT_HEVC
91};
92
93enum {
94 VID_API_CMD_NULL = 0x00,
95 VID_API_CMD_PARSE_NEXT_SEQ = 0x01,
96 VID_API_CMD_PARSE_NEXT_I = 0x02,
97 VID_API_CMD_PARSE_NEXT_IP = 0x03,
98 VID_API_CMD_PARSE_NEXT_ANY = 0x04,
99 VID_API_CMD_DEC_PIC = 0x05,
100 VID_API_CMD_UPDATE_ES_WR_PTR = 0x06,
101 VID_API_CMD_UPDATE_ES_RD_PTR = 0x07,
102 VID_API_CMD_UPDATE_UDATA = 0x08,
103 VID_API_CMD_GET_FSINFO = 0x09,
104 VID_API_CMD_SKIP_PIC = 0x0a,
105 VID_API_CMD_DEC_CHUNK = 0x0b,
106 VID_API_CMD_START = 0x10,
107 VID_API_CMD_STOP = 0x11,
108 VID_API_CMD_ABORT = 0x12,
109 VID_API_CMD_RST_BUF = 0x13,
110 VID_API_CMD_FS_RELEASE = 0x15,
111 VID_API_CMD_MEM_REGION_ATTACH = 0x16,
112 VID_API_CMD_MEM_REGION_DETACH = 0x17,
113 VID_API_CMD_MVC_VIEW_SELECT = 0x18,
114 VID_API_CMD_FS_ALLOC = 0x19,
115 VID_API_CMD_DBG_GET_STATUS = 0x1C,
116 VID_API_CMD_DBG_START_LOG = 0x1D,
117 VID_API_CMD_DBG_STOP_LOG = 0x1E,
118 VID_API_CMD_DBG_DUMP_LOG = 0x1F,
119 VID_API_CMD_YUV_READY = 0x20,
120 VID_API_CMD_TS = 0x21,
121
122 VID_API_CMD_FIRM_RESET = 0x40,
123
124 VID_API_CMD_SNAPSHOT = 0xAA,
125 VID_API_CMD_ROLL_SNAPSHOT = 0xAB,
126 VID_API_CMD_LOCK_SCHEDULER = 0xAC,
127 VID_API_CMD_UNLOCK_SCHEDULER = 0xAD,
128 VID_API_CMD_CQ_FIFO_DUMP = 0xAE,
129 VID_API_CMD_DBG_FIFO_DUMP = 0xAF,
130 VID_API_CMD_SVC_ILP = 0xBB,
131 VID_API_CMD_FW_STATUS = 0xF0,
132 VID_API_CMD_INVALID = 0xFF
133};
134
135enum {
136 VID_API_EVENT_NULL = 0x00,
137 VID_API_EVENT_RESET_DONE = 0x01,
138 VID_API_EVENT_SEQ_HDR_FOUND = 0x02,
139 VID_API_EVENT_PIC_HDR_FOUND = 0x03,
140 VID_API_EVENT_PIC_DECODED = 0x04,
141 VID_API_EVENT_FIFO_LOW = 0x05,
142 VID_API_EVENT_FIFO_HIGH = 0x06,
143 VID_API_EVENT_FIFO_EMPTY = 0x07,
144 VID_API_EVENT_FIFO_FULL = 0x08,
145 VID_API_EVENT_BS_ERROR = 0x09,
146 VID_API_EVENT_UDATA_FIFO_UPTD = 0x0A,
147 VID_API_EVENT_RES_CHANGE = 0x0B,
148 VID_API_EVENT_FIFO_OVF = 0x0C,
149 VID_API_EVENT_CHUNK_DECODED = 0x0D,
150 VID_API_EVENT_REQ_FRAME_BUFF = 0x10,
151 VID_API_EVENT_FRAME_BUFF_RDY = 0x11,
152 VID_API_EVENT_REL_FRAME_BUFF = 0x12,
153 VID_API_EVENT_STR_BUF_RST = 0x13,
154 VID_API_EVENT_RET_PING = 0x14,
155 VID_API_EVENT_QMETER = 0x15,
156 VID_API_EVENT_STR_FMT_CHANGE = 0x16,
157 VID_API_EVENT_FIRMWARE_XCPT = 0x17,
158 VID_API_EVENT_START_DONE = 0x18,
159 VID_API_EVENT_STOPPED = 0x19,
160 VID_API_EVENT_ABORT_DONE = 0x1A,
161 VID_API_EVENT_FINISHED = 0x1B,
162 VID_API_EVENT_DBG_STAT_UPDATE = 0x1C,
163 VID_API_EVENT_DBG_LOG_STARTED = 0x1D,
164 VID_API_EVENT_DBG_LOG_STOPPED = 0x1E,
165 VID_API_EVENT_DBG_LOG_UPDATED = 0x1F,
166 VID_API_EVENT_DBG_MSG_DEC = 0x20,
167 VID_API_EVENT_DEC_SC_ERR = 0x21,
168 VID_API_EVENT_CQ_FIFO_DUMP = 0x22,
169 VID_API_EVENT_DBG_FIFO_DUMP = 0x23,
170 VID_API_EVENT_DEC_CHECK_RES = 0x24,
171 VID_API_EVENT_DEC_CFG_INFO = 0x25,
172 VID_API_EVENT_UNSUPPORTED_STREAM = 0x26,
173 VID_API_EVENT_STR_SUSPENDED = 0x30,
174 VID_API_EVENT_SNAPSHOT_DONE = 0x40,
175 VID_API_EVENT_FW_STATUS = 0xF0,
176 VID_API_EVENT_INVALID = 0xFF
177};
178
179struct vpu_malone_buffer_desc {
180 struct vpu_rpc_buffer_desc buffer;
181 u32 low;
182 u32 high;
183};
184
185struct vpu_malone_str_buffer {
186 u32 wptr;
187 u32 rptr;
188 u32 start;
189 u32 end;
190 u32 lwm;
191};
192
193struct vpu_malone_picth_info {
194 u32 frame_pitch;
195};
196
197struct vpu_malone_table_desc {
198 u32 array_base;
199 u32 size;
200};
201
202struct vpu_malone_dbglog_desc {
203 u32 addr;
204 u32 size;
205 u32 level;
206 u32 reserved;
207};
208
209struct vpu_malone_frame_buffer {
210 u32 addr;
211 u32 size;
212};
213
214struct vpu_malone_udata {
215 u32 base;
216 u32 total_size;
217 u32 slot_size;
218};
219
220struct vpu_malone_buffer_info {
221 u32 stream_input_mode;
222 u32 stream_pic_input_count;
223 u32 stream_pic_parsed_count;
224 u32 stream_buffer_threshold;
225 u32 stream_pic_end_flag;
226};
227
228struct vpu_malone_encrypt_info {
229 u32 rec4key[8];
230 u32 obfusc;
231};
232
233struct malone_iface {
234 u32 exec_base_addr;
235 u32 exec_area_size;
236 struct vpu_malone_buffer_desc cmd_buffer_desc;
237 struct vpu_malone_buffer_desc msg_buffer_desc;
238 u32 cmd_int_enable[VID_API_NUM_STREAMS];
239 struct vpu_malone_picth_info stream_pitch_info[VID_API_NUM_STREAMS];
240 u32 stream_config[VID_API_NUM_STREAMS];
241 struct vpu_malone_table_desc codec_param_tab_desc;
242 struct vpu_malone_table_desc jpeg_param_tab_desc;
243 u32 stream_buffer_desc[VID_API_NUM_STREAMS][VID_API_MAX_BUF_PER_STR];
244 struct vpu_malone_table_desc seq_info_tab_desc;
245 struct vpu_malone_table_desc pic_info_tab_desc;
246 struct vpu_malone_table_desc gop_info_tab_desc;
247 struct vpu_malone_table_desc qmeter_info_tab_desc;
248 u32 stream_error[VID_API_NUM_STREAMS];
249 u32 fw_version;
250 u32 fw_offset;
251 u32 max_streams;
252 struct vpu_malone_dbglog_desc dbglog_desc;
253 struct vpu_rpc_buffer_desc api_cmd_buffer_desc[VID_API_NUM_STREAMS];
254 struct vpu_malone_udata udata_buffer[VID_API_NUM_STREAMS];
255 struct vpu_malone_buffer_desc debug_buffer_desc;
256 struct vpu_malone_buffer_desc eng_access_buff_desc[VID_API_NUM_STREAMS];
257 u32 encrypt_info[VID_API_NUM_STREAMS];
258 struct vpu_rpc_system_config system_cfg;
259 u32 api_version;
260 struct vpu_malone_buffer_info stream_buff_info[VID_API_NUM_STREAMS];
261};
262
263struct malone_jpg_params {
264 u32 rotation_angle;
265 u32 horiz_scale_factor;
266 u32 vert_scale_factor;
267 u32 rotation_mode;
268 u32 rgb_mode;
269 u32 chunk_mode;
270 u32 last_chunk;
271 u32 chunk_rows;
272 u32 num_bytes;
273 u32 jpg_crop_x;
274 u32 jpg_crop_y;
275 u32 jpg_crop_width;
276 u32 jpg_crop_height;
277 u32 jpg_mjpeg_mode;
278 u32 jpg_mjpeg_interlaced;
279};
280
281struct malone_codec_params {
282 u32 disp_imm;
283 u32 fourcc;
284 u32 codec_version;
285 u32 frame_rate;
286 u32 dbglog_enable;
287 u32 bsdma_lwm;
288 u32 bbd_coring;
289 u32 bbd_s_thr_row;
290 u32 bbd_p_thr_row;
291 u32 bbd_s_thr_logo_row;
292 u32 bbd_p_thr_logo_row;
293 u32 bbd_s_thr_col;
294 u32 bbd_p_thr_col;
295 u32 bbd_chr_thr_row;
296 u32 bbd_chr_thr_col;
297 u32 bbd_uv_mid_level;
298 u32 bbd_excl_win_mb_left;
299 u32 bbd_excl_win_mb_right;
300};
301
302struct malone_padding_scode {
303 u32 scode_type;
304 u32 pixelformat;
305 u32 data[2];
306};
307
308struct malone_fmt_mapping {
309 u32 pixelformat;
310 enum vpu_malone_format malone_format;
311};
312
313struct malone_scode_t {
314 struct vpu_inst *inst;
315 struct vb2_buffer *vb;
316 u32 wptr;
317 u32 need_data;
318};
319
320struct malone_scode_handler {
321 u32 pixelformat;
322 int (*insert_scode_seq)(struct malone_scode_t *scode);
323 int (*insert_scode_pic)(struct malone_scode_t *scode);
324};
325
326struct vpu_dec_ctrl {
327 struct malone_codec_params *codec_param;
328 struct malone_jpg_params *jpg;
329 void *seq_mem;
330 void *pic_mem;
331 void *gop_mem;
332 void *qmeter_mem;
333 void *dbglog_mem;
334 struct vpu_malone_str_buffer __iomem *str_buf[VID_API_NUM_STREAMS];
335 u32 buf_addr[VID_API_NUM_STREAMS];
336};
337
338u32 vpu_malone_get_data_size(void)
339{
340 return sizeof(struct vpu_dec_ctrl);
341}
342
343void vpu_malone_init_rpc(struct vpu_shared_addr *shared,
344 struct vpu_buffer *rpc, dma_addr_t boot_addr)
345{
346 struct malone_iface *iface;
347 struct vpu_dec_ctrl *hc;
348 unsigned long base_phy_addr;
349 unsigned long phy_addr;
350 unsigned long offset;
351 unsigned int i;
352
353 if (rpc->phys < boot_addr)
354 return;
355
356 iface = rpc->virt;
357 base_phy_addr = rpc->phys - boot_addr;
358 hc = shared->priv;
359
360 shared->iface = iface;
361 shared->boot_addr = boot_addr;
362
363 iface->exec_base_addr = base_phy_addr;
364 iface->exec_area_size = rpc->length;
365
366 offset = sizeof(struct malone_iface);
367 phy_addr = base_phy_addr + offset;
368
369 shared->cmd_desc = &iface->cmd_buffer_desc.buffer;
370 shared->cmd_mem_vir = rpc->virt + offset;
371 iface->cmd_buffer_desc.buffer.start =
372 iface->cmd_buffer_desc.buffer.rptr =
373 iface->cmd_buffer_desc.buffer.wptr = phy_addr;
374 iface->cmd_buffer_desc.buffer.end = iface->cmd_buffer_desc.buffer.start + CMD_SIZE;
375 offset += CMD_SIZE;
376 phy_addr = base_phy_addr + offset;
377
378 shared->msg_desc = &iface->msg_buffer_desc.buffer;
379 shared->msg_mem_vir = rpc->virt + offset;
380 iface->msg_buffer_desc.buffer.start =
381 iface->msg_buffer_desc.buffer.wptr =
382 iface->msg_buffer_desc.buffer.rptr = phy_addr;
383 iface->msg_buffer_desc.buffer.end = iface->msg_buffer_desc.buffer.start + MSG_SIZE;
384 offset += MSG_SIZE;
385 phy_addr = base_phy_addr + offset;
386
387 iface->codec_param_tab_desc.array_base = phy_addr;
388 hc->codec_param = rpc->virt + offset;
389 offset += CODEC_SIZE;
390 phy_addr = base_phy_addr + offset;
391
392 iface->jpeg_param_tab_desc.array_base = phy_addr;
393 hc->jpg = rpc->virt + offset;
394 offset += JPEG_SIZE;
395 phy_addr = base_phy_addr + offset;
396
397 iface->seq_info_tab_desc.array_base = phy_addr;
398 hc->seq_mem = rpc->virt + offset;
399 offset += SEQ_SIZE;
400 phy_addr = base_phy_addr + offset;
401
402 iface->pic_info_tab_desc.array_base = phy_addr;
403 hc->pic_mem = rpc->virt + offset;
404 offset += PIC_SIZE;
405 phy_addr = base_phy_addr + offset;
406
407 iface->gop_info_tab_desc.array_base = phy_addr;
408 hc->gop_mem = rpc->virt + offset;
409 offset += GOP_SIZE;
410 phy_addr = base_phy_addr + offset;
411
412 iface->qmeter_info_tab_desc.array_base = phy_addr;
413 hc->qmeter_mem = rpc->virt + offset;
414 offset += QMETER_SIZE;
415 phy_addr = base_phy_addr + offset;
416
417 iface->dbglog_desc.addr = phy_addr;
418 iface->dbglog_desc.size = DBGLOG_SIZE;
419 hc->dbglog_mem = rpc->virt + offset;
420 offset += DBGLOG_SIZE;
421 phy_addr = base_phy_addr + offset;
422
423 for (i = 0; i < VID_API_NUM_STREAMS; i++) {
424 iface->eng_access_buff_desc[i].buffer.start =
425 iface->eng_access_buff_desc[i].buffer.wptr =
426 iface->eng_access_buff_desc[i].buffer.rptr = phy_addr;
427 iface->eng_access_buff_desc[i].buffer.end =
428 iface->eng_access_buff_desc[i].buffer.start + ENG_SIZE;
429 offset += ENG_SIZE;
430 phy_addr = base_phy_addr + offset;
431 }
432
433 for (i = 0; i < VID_API_NUM_STREAMS; i++) {
434 iface->encrypt_info[i] = phy_addr;
435 offset += sizeof(struct vpu_malone_encrypt_info);
436 phy_addr = base_phy_addr + offset;
437 }
438
439 rpc->bytesused = offset;
440}
441
442void vpu_malone_set_log_buf(struct vpu_shared_addr *shared,
443 struct vpu_buffer *log)
444{
445 struct malone_iface *iface = shared->iface;
446
447 iface->debug_buffer_desc.buffer.start =
448 iface->debug_buffer_desc.buffer.wptr =
449 iface->debug_buffer_desc.buffer.rptr = log->phys - shared->boot_addr;
450 iface->debug_buffer_desc.buffer.end = iface->debug_buffer_desc.buffer.start + log->length;
451}
452
453static u32 get_str_buffer_offset(u32 instance)
454{
455 return DEC_MFD_XREG_SLV_BASE + MFD_MCX + MFD_MCX_OFF * instance;
456}
457
458void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared,
459 u32 regs_base, void __iomem *regs, u32 core_id)
460{
461 struct malone_iface *iface = shared->iface;
462 struct vpu_rpc_system_config *config = &iface->system_cfg;
463 struct vpu_dec_ctrl *hc = shared->priv;
464 int i;
465
466 vpu_imx8q_set_system_cfg_common(config, regs_base, core_id);
467 for (i = 0; i < VID_API_NUM_STREAMS; i++) {
468 u32 offset = get_str_buffer_offset(i);
469
470 hc->buf_addr[i] = regs_base + offset;
471 hc->str_buf[i] = regs + offset;
472 }
473}
474
475u32 vpu_malone_get_version(struct vpu_shared_addr *shared)
476{
477 struct malone_iface *iface = shared->iface;
478
479 return iface->fw_version;
480}
481
482int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared)
483{
484 return 0xc00000;
485}
486
487int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared,
488 u32 instance,
489 struct vpu_buffer *buf)
490{
491 struct malone_iface *iface = shared->iface;
492 struct vpu_dec_ctrl *hc = shared->priv;
493 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
494
495 writel(buf->phys, &str_buf->start);
496 writel(buf->phys, &str_buf->rptr);
497 writel(buf->phys, &str_buf->wptr);
498 writel(buf->phys + buf->length, &str_buf->end);
499 writel(0x1, &str_buf->lwm);
500
501 iface->stream_buffer_desc[instance][0] = hc->buf_addr[instance];
502
503 return 0;
504}
505
506int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared,
507 u32 instance,
508 struct vpu_rpc_buffer_desc *desc)
509{
510 struct vpu_dec_ctrl *hc = shared->priv;
511 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
512
513 if (desc) {
514 desc->wptr = readl(&str_buf->wptr);
515 desc->rptr = readl(&str_buf->rptr);
516 desc->start = readl(&str_buf->start);
517 desc->end = readl(&str_buf->end);
518 }
519
520 return 0;
521}
522
523static void vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 wptr)
524{
525
526 mb();
527 writel(wptr, &str_buf->wptr);
528}
529
530static void vpu_malone_update_rptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 rptr)
531{
532
533 mb();
534 writel(rptr, &str_buf->rptr);
535}
536
537int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared,
538 u32 instance, u32 ptr, bool write)
539{
540 struct vpu_dec_ctrl *hc = shared->priv;
541 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
542
543 if (write)
544 vpu_malone_update_wptr(str_buf, ptr);
545 else
546 vpu_malone_update_rptr(str_buf, ptr);
547
548 return 0;
549}
550
551static struct malone_fmt_mapping fmt_mappings[] = {
552 {V4L2_PIX_FMT_H264, MALONE_FMT_AVC},
553 {V4L2_PIX_FMT_H264_MVC, MALONE_FMT_AVC},
554 {V4L2_PIX_FMT_HEVC, MALONE_FMT_HEVC},
555 {V4L2_PIX_FMT_VC1_ANNEX_G, MALONE_FMT_VC1},
556 {V4L2_PIX_FMT_VC1_ANNEX_L, MALONE_FMT_VC1},
557 {V4L2_PIX_FMT_MPEG2, MALONE_FMT_MP2},
558 {V4L2_PIX_FMT_MPEG4, MALONE_FMT_ASP},
559 {V4L2_PIX_FMT_XVID, MALONE_FMT_ASP},
560 {V4L2_PIX_FMT_H263, MALONE_FMT_ASP},
561 {V4L2_PIX_FMT_JPEG, MALONE_FMT_JPG},
562 {V4L2_PIX_FMT_VP8, MALONE_FMT_VP8},
563};
564
565static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat)
566{
567 u32 i;
568
569 for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) {
570 if (pixelformat == fmt_mappings[i].pixelformat)
571 return fmt_mappings[i].malone_format;
572 }
573
574 return MALONE_FMT_NULL;
575}
576
577static void vpu_malone_set_stream_cfg(struct vpu_shared_addr *shared,
578 u32 instance,
579 enum vpu_malone_format malone_format)
580{
581 struct malone_iface *iface = shared->iface;
582 u32 *curr_str_cfg = &iface->stream_config[instance];
583
584 *curr_str_cfg = 0;
585 STREAM_CONFIG_FORMAT_SET(malone_format, curr_str_cfg);
586 STREAM_CONFIG_STRBUFIDX_SET(0, curr_str_cfg);
587 STREAM_CONFIG_NOSEQ_SET(0, curr_str_cfg);
588 STREAM_CONFIG_DEBLOCK_SET(0, curr_str_cfg);
589 STREAM_CONFIG_DERING_SET(0, curr_str_cfg);
590 STREAM_CONFIG_PLAY_MODE_SET(0x3, curr_str_cfg);
591 STREAM_CONFIG_FS_CTRL_MODE_SET(0x1, curr_str_cfg);
592 STREAM_CONFIG_ENABLE_DCP_SET(1, curr_str_cfg);
593 STREAM_CONFIG_NUM_STR_BUF_SET(1, curr_str_cfg);
594 STREAM_CONFIG_MALONE_USAGE_SET(1, curr_str_cfg);
595 STREAM_CONFIG_MULTI_VID_SET(0, curr_str_cfg);
596 STREAM_CONFIG_OBFUSC_EN_SET(0, curr_str_cfg);
597 STREAM_CONFIG_RC4_EN_SET(0, curr_str_cfg);
598 STREAM_CONFIG_MCX_SET(1, curr_str_cfg);
599 STREAM_CONFIG_PES_SET(0, curr_str_cfg);
600 STREAM_CONFIG_NUM_DBE_SET(1, curr_str_cfg);
601}
602
603static int vpu_malone_set_params(struct vpu_shared_addr *shared,
604 u32 instance,
605 struct vpu_decode_params *params)
606{
607 struct malone_iface *iface = shared->iface;
608 struct vpu_dec_ctrl *hc = shared->priv;
609 enum vpu_malone_format malone_format;
610
611 malone_format = vpu_malone_format_remap(params->codec_format);
612 iface->udata_buffer[instance].base = params->udata.base;
613 iface->udata_buffer[instance].slot_size = params->udata.size;
614
615 vpu_malone_set_stream_cfg(shared, instance, malone_format);
616
617 if (malone_format == MALONE_FMT_JPG) {
618
619 hc->jpg[instance].jpg_mjpeg_mode = 1;
620
621 hc->jpg[instance].jpg_mjpeg_interlaced = 0;
622 }
623
624 hc->codec_param[instance].disp_imm = params->b_dis_reorder ? 1 : 0;
625 hc->codec_param[instance].dbglog_enable = 0;
626 iface->dbglog_desc.level = 0;
627
628 if (params->b_non_frame)
629 iface->stream_buff_info[instance].stream_input_mode = NON_FRAME_LVL;
630 else
631 iface->stream_buff_info[instance].stream_input_mode = FRAME_LVL;
632 iface->stream_buff_info[instance].stream_buffer_threshold = 0;
633 iface->stream_buff_info[instance].stream_pic_input_count = 0;
634
635 return 0;
636}
637
638static bool vpu_malone_is_non_frame_mode(struct vpu_shared_addr *shared, u32 instance)
639{
640 struct malone_iface *iface = shared->iface;
641
642 if (iface->stream_buff_info[instance].stream_input_mode == NON_FRAME_LVL)
643 return true;
644
645 return false;
646}
647
648static int vpu_malone_update_params(struct vpu_shared_addr *shared,
649 u32 instance,
650 struct vpu_decode_params *params)
651{
652 struct malone_iface *iface = shared->iface;
653
654 if (params->end_flag)
655 iface->stream_buff_info[instance].stream_pic_end_flag = params->end_flag;
656 params->end_flag = 0;
657
658 return 0;
659}
660
661int vpu_malone_set_decode_params(struct vpu_shared_addr *shared,
662 u32 instance,
663 struct vpu_decode_params *params,
664 u32 update)
665{
666 if (!params)
667 return -EINVAL;
668
669 if (!update)
670 return vpu_malone_set_params(shared, instance, params);
671 else
672 return vpu_malone_update_params(shared, instance, params);
673}
674
675static struct vpu_pair malone_cmds[] = {
676 {VPU_CMD_ID_START, VID_API_CMD_START},
677 {VPU_CMD_ID_STOP, VID_API_CMD_STOP},
678 {VPU_CMD_ID_ABORT, VID_API_CMD_ABORT},
679 {VPU_CMD_ID_RST_BUF, VID_API_CMD_RST_BUF},
680 {VPU_CMD_ID_SNAPSHOT, VID_API_CMD_SNAPSHOT},
681 {VPU_CMD_ID_FIRM_RESET, VID_API_CMD_FIRM_RESET},
682 {VPU_CMD_ID_FS_ALLOC, VID_API_CMD_FS_ALLOC},
683 {VPU_CMD_ID_FS_RELEASE, VID_API_CMD_FS_RELEASE},
684 {VPU_CMD_ID_TIMESTAMP, VID_API_CMD_TS},
685 {VPU_CMD_ID_DEBUG, VID_API_CMD_FW_STATUS},
686};
687
688static struct vpu_pair malone_msgs[] = {
689 {VPU_MSG_ID_RESET_DONE, VID_API_EVENT_RESET_DONE},
690 {VPU_MSG_ID_START_DONE, VID_API_EVENT_START_DONE},
691 {VPU_MSG_ID_STOP_DONE, VID_API_EVENT_STOPPED},
692 {VPU_MSG_ID_ABORT_DONE, VID_API_EVENT_ABORT_DONE},
693 {VPU_MSG_ID_BUF_RST, VID_API_EVENT_STR_BUF_RST},
694 {VPU_MSG_ID_PIC_EOS, VID_API_EVENT_FINISHED},
695 {VPU_MSG_ID_SEQ_HDR_FOUND, VID_API_EVENT_SEQ_HDR_FOUND},
696 {VPU_MSG_ID_RES_CHANGE, VID_API_EVENT_RES_CHANGE},
697 {VPU_MSG_ID_PIC_HDR_FOUND, VID_API_EVENT_PIC_HDR_FOUND},
698 {VPU_MSG_ID_PIC_DECODED, VID_API_EVENT_PIC_DECODED},
699 {VPU_MSG_ID_DEC_DONE, VID_API_EVENT_FRAME_BUFF_RDY},
700 {VPU_MSG_ID_FRAME_REQ, VID_API_EVENT_REQ_FRAME_BUFF},
701 {VPU_MSG_ID_FRAME_RELEASE, VID_API_EVENT_REL_FRAME_BUFF},
702 {VPU_MSG_ID_FIFO_LOW, VID_API_EVENT_FIFO_LOW},
703 {VPU_MSG_ID_BS_ERROR, VID_API_EVENT_BS_ERROR},
704 {VPU_MSG_ID_UNSUPPORTED, VID_API_EVENT_UNSUPPORTED_STREAM},
705 {VPU_MSG_ID_FIRMWARE_XCPT, VID_API_EVENT_FIRMWARE_XCPT},
706};
707
708static void vpu_malone_pack_fs_alloc(struct vpu_rpc_event *pkt,
709 struct vpu_fs_info *fs)
710{
711 const u32 fs_type[] = {
712 [MEM_RES_FRAME] = 0,
713 [MEM_RES_MBI] = 1,
714 [MEM_RES_DCP] = 2,
715 };
716
717 pkt->hdr.num = 7;
718 pkt->data[0] = fs->id | (fs->tag << 24);
719 pkt->data[1] = fs->luma_addr;
720 if (fs->type == MEM_RES_FRAME) {
721
722
723
724
725
726
727 if (fs->luma_addr == fs->chroma_addr)
728 fs->chroma_addr = fs->luma_addr + fs->luma_size;
729 pkt->data[2] = fs->luma_addr + fs->luma_size / 2;
730 pkt->data[3] = fs->chroma_addr;
731 pkt->data[4] = fs->chroma_addr + fs->chromau_size / 2;
732 pkt->data[5] = fs->bytesperline;
733 } else {
734 pkt->data[2] = fs->luma_size;
735 pkt->data[3] = 0;
736 pkt->data[4] = 0;
737 pkt->data[5] = 0;
738 }
739 pkt->data[6] = fs_type[fs->type];
740}
741
742static void vpu_malone_pack_fs_release(struct vpu_rpc_event *pkt,
743 struct vpu_fs_info *fs)
744{
745 pkt->hdr.num = 1;
746 pkt->data[0] = fs->id | (fs->tag << 24);
747}
748
749static void vpu_malone_pack_timestamp(struct vpu_rpc_event *pkt,
750 struct vpu_ts_info *info)
751{
752 struct timespec64 ts = ns_to_timespec64(info->timestamp);
753
754 pkt->hdr.num = 3;
755
756 pkt->data[0] = ts.tv_sec;
757 pkt->data[1] = ts.tv_nsec;
758 pkt->data[2] = info->size;
759}
760
761int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data)
762{
763 int ret;
764
765 ret = vpu_find_dst_by_src(malone_cmds, ARRAY_SIZE(malone_cmds), id);
766 if (ret < 0)
767 return ret;
768
769 pkt->hdr.id = ret;
770 pkt->hdr.num = 0;
771 pkt->hdr.index = index;
772
773 switch (id) {
774 case VPU_CMD_ID_FS_ALLOC:
775 vpu_malone_pack_fs_alloc(pkt, data);
776 break;
777 case VPU_CMD_ID_FS_RELEASE:
778 vpu_malone_pack_fs_release(pkt, data);
779 break;
780 case VPU_CMD_ID_TIMESTAMP:
781 vpu_malone_pack_timestamp(pkt, data);
782 break;
783 }
784
785 pkt->hdr.index = index;
786 return 0;
787}
788
789int vpu_malone_convert_msg_id(u32 id)
790{
791 return vpu_find_src_by_dst(malone_msgs, ARRAY_SIZE(malone_msgs), id);
792}
793
794static void vpu_malone_fill_planes(struct vpu_dec_codec_info *info)
795{
796 u32 interlaced = info->progressive ? 0 : 1;
797
798 info->bytesperline[0] = 0;
799 info->sizeimage[0] = vpu_helper_get_plane_size(info->pixfmt,
800 info->decoded_width,
801 info->decoded_height,
802 0,
803 info->stride,
804 interlaced,
805 &info->bytesperline[0]);
806 info->bytesperline[1] = 0;
807 info->sizeimage[1] = vpu_helper_get_plane_size(info->pixfmt,
808 info->decoded_width,
809 info->decoded_height,
810 1,
811 info->stride,
812 interlaced,
813 &info->bytesperline[1]);
814}
815
816static void vpu_malone_init_seq_hdr(struct vpu_dec_codec_info *info)
817{
818 u32 chunks = info->num_dfe_area >> MALONE_DCP_CHUNK_BIT;
819
820 vpu_malone_fill_planes(info);
821
822 info->mbi_size = (info->sizeimage[0] + info->sizeimage[1]) >> 2;
823 info->mbi_size = ALIGN(info->mbi_size, MALONE_ALIGN_MBI);
824
825 info->dcp_size = MALONE_DCP_SIZE_MAX;
826 if (chunks) {
827 u32 mb_num;
828 u32 mb_w;
829 u32 mb_h;
830
831 mb_w = DIV_ROUND_UP(info->decoded_width, 16);
832 mb_h = DIV_ROUND_UP(info->decoded_height, 16);
833 mb_num = mb_w * mb_h;
834 info->dcp_size = mb_num * MALONE_DCP_FIXED_MB_ALLOC * chunks;
835 info->dcp_size = clamp_t(u32, info->dcp_size,
836 MALONE_DCP_SIZE_MIN, MALONE_DCP_SIZE_MAX);
837 }
838}
839
840static void vpu_malone_unpack_seq_hdr(struct vpu_rpc_event *pkt,
841 struct vpu_dec_codec_info *info)
842{
843 info->num_ref_frms = pkt->data[0];
844 info->num_dpb_frms = pkt->data[1];
845 info->num_dfe_area = pkt->data[2];
846 info->progressive = pkt->data[3];
847 info->width = pkt->data[5];
848 info->height = pkt->data[4];
849 info->decoded_width = pkt->data[12];
850 info->decoded_height = pkt->data[11];
851 info->frame_rate.numerator = 1000;
852 info->frame_rate.denominator = pkt->data[8];
853 info->dsp_asp_ratio = pkt->data[9];
854 info->level_idc = pkt->data[10];
855 info->bit_depth_luma = pkt->data[13];
856 info->bit_depth_chroma = pkt->data[14];
857 info->chroma_fmt = pkt->data[15];
858 info->color_primaries = vpu_color_cvrt_primaries_i2v(pkt->data[16]);
859 info->transfer_chars = vpu_color_cvrt_transfers_i2v(pkt->data[17]);
860 info->matrix_coeffs = vpu_color_cvrt_matrix_i2v(pkt->data[18]);
861 info->full_range = vpu_color_cvrt_full_range_i2v(pkt->data[19]);
862 info->vui_present = pkt->data[20];
863 info->mvc_num_views = pkt->data[21];
864 info->offset_x = pkt->data[23];
865 info->offset_y = pkt->data[25];
866 info->tag = pkt->data[27];
867 if (info->bit_depth_luma > 8)
868 info->pixfmt = V4L2_PIX_FMT_NV12M_10BE_8L128;
869 else
870 info->pixfmt = V4L2_PIX_FMT_NV12M_8L128;
871 if (info->frame_rate.numerator && info->frame_rate.denominator) {
872 unsigned long n, d;
873
874 rational_best_approximation(info->frame_rate.numerator,
875 info->frame_rate.denominator,
876 info->frame_rate.numerator,
877 info->frame_rate.denominator,
878 &n, &d);
879 info->frame_rate.numerator = n;
880 info->frame_rate.denominator = d;
881 }
882 vpu_malone_init_seq_hdr(info);
883}
884
885static void vpu_malone_unpack_pic_info(struct vpu_rpc_event *pkt,
886 struct vpu_dec_pic_info *info)
887{
888 info->id = pkt->data[7];
889 info->luma = pkt->data[0];
890 info->start = pkt->data[10];
891 info->end = pkt->data[12];
892 info->pic_size = pkt->data[11];
893 info->stride = pkt->data[5];
894 info->consumed_count = pkt->data[13];
895 if (info->id == MALONE_SKIPPED_FRAME_ID)
896 info->skipped = 1;
897 else
898 info->skipped = 0;
899}
900
901static void vpu_malone_unpack_req_frame(struct vpu_rpc_event *pkt,
902 struct vpu_fs_info *info)
903{
904 info->type = pkt->data[1];
905}
906
907static void vpu_malone_unpack_rel_frame(struct vpu_rpc_event *pkt,
908 struct vpu_fs_info *info)
909{
910 info->id = pkt->data[0];
911 info->type = pkt->data[1];
912 info->not_displayed = pkt->data[2];
913}
914
915static void vpu_malone_unpack_buff_rdy(struct vpu_rpc_event *pkt,
916 struct vpu_dec_pic_info *info)
917{
918 struct timespec64 ts = { pkt->data[9], pkt->data[10] };
919
920 info->id = pkt->data[0];
921 info->luma = pkt->data[1];
922 info->stride = pkt->data[3];
923 if (info->id == MALONE_SKIPPED_FRAME_ID)
924 info->skipped = 1;
925 else
926 info->skipped = 0;
927
928 info->timestamp = timespec64_to_ns(&ts);
929}
930
931int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data)
932{
933 if (!pkt || !data)
934 return -EINVAL;
935
936 switch (pkt->hdr.id) {
937 case VID_API_EVENT_SEQ_HDR_FOUND:
938 vpu_malone_unpack_seq_hdr(pkt, data);
939 break;
940 case VID_API_EVENT_PIC_DECODED:
941 vpu_malone_unpack_pic_info(pkt, data);
942 break;
943 case VID_API_EVENT_REQ_FRAME_BUFF:
944 vpu_malone_unpack_req_frame(pkt, data);
945 break;
946 case VID_API_EVENT_REL_FRAME_BUFF:
947 vpu_malone_unpack_rel_frame(pkt, data);
948 break;
949 case VID_API_EVENT_FRAME_BUFF_RDY:
950 vpu_malone_unpack_buff_rdy(pkt, data);
951 break;
952 }
953
954 return 0;
955}
956
957static const struct malone_padding_scode padding_scodes[] = {
958 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264, {0x0B010000, 0}},
959 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}},
960 {SCODE_PADDING_EOS, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}},
961 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}},
962 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}},
963 {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG2, {0xCC010000, 0x0}},
964 {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}},
965 {SCODE_PADDING_EOS, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}},
966 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}},
967 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}},
968 {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0xefff0000, 0x0}},
969 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264, {0x0B010000, 0}},
970 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}},
971 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}},
972 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}},
973 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}},
974 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG2, {0xb7010000, 0x0}},
975 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}},
976 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}},
977 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}},
978 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}},
979 {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0x0, 0x0}},
980 {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264, {0x15010000, 0x0}},
981 {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264_MVC, {0x15010000, 0x0}},
982};
983
984static const struct malone_padding_scode padding_scode_dft = {0x0, 0x0};
985
986static const struct malone_padding_scode *get_padding_scode(u32 type, u32 fmt)
987{
988 const struct malone_padding_scode *s;
989 int i;
990
991 for (i = 0; i < ARRAY_SIZE(padding_scodes); i++) {
992 s = &padding_scodes[i];
993
994 if (s->scode_type == type && s->pixelformat == fmt)
995 return s;
996 }
997
998 if (type != SCODE_PADDING_BUFFLUSH)
999 return &padding_scode_dft;
1000
1001 return NULL;
1002}
1003
1004static int vpu_malone_add_padding_scode(struct vpu_buffer *stream_buffer,
1005 struct vpu_malone_str_buffer __iomem *str_buf,
1006 u32 pixelformat, u32 scode_type)
1007{
1008 u32 wptr;
1009 int size;
1010 int total_size = 0;
1011 const struct malone_padding_scode *ps;
1012 const u32 padding_size = 4096;
1013 int ret;
1014
1015 ps = get_padding_scode(scode_type, pixelformat);
1016 if (!ps)
1017 return -EINVAL;
1018
1019 wptr = readl(&str_buf->wptr);
1020 if (wptr < stream_buffer->phys || wptr > stream_buffer->phys + stream_buffer->length)
1021 return -EINVAL;
1022 if (wptr == stream_buffer->phys + stream_buffer->length)
1023 wptr = stream_buffer->phys;
1024 size = ALIGN(wptr, 4) - wptr;
1025 if (size)
1026 vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size);
1027 total_size += size;
1028
1029 size = sizeof(ps->data);
1030 ret = vpu_helper_copy_to_stream_buffer(stream_buffer, &wptr, size, (void *)ps->data);
1031 if (ret < 0)
1032 return -EINVAL;
1033 total_size += size;
1034
1035 size = padding_size - sizeof(ps->data);
1036 vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size);
1037 total_size += size;
1038
1039 vpu_malone_update_wptr(str_buf, wptr);
1040 return total_size;
1041}
1042
1043int vpu_malone_add_scode(struct vpu_shared_addr *shared,
1044 u32 instance,
1045 struct vpu_buffer *stream_buffer,
1046 u32 pixelformat,
1047 u32 scode_type)
1048{
1049 struct vpu_dec_ctrl *hc = shared->priv;
1050 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
1051 int ret = -EINVAL;
1052
1053 switch (scode_type) {
1054 case SCODE_PADDING_EOS:
1055 case SCODE_PADDING_ABORT:
1056 case SCODE_PADDING_BUFFLUSH:
1057 ret = vpu_malone_add_padding_scode(stream_buffer, str_buf, pixelformat, scode_type);
1058 break;
1059 default:
1060 break;
1061 }
1062
1063 return ret;
1064}
1065
1066#define MALONE_PAYLOAD_HEADER_SIZE 16
1067#define MALONE_CODEC_VERSION_ID 0x1
1068#define MALONE_CODEC_ID_VC1_SIMPLE 0x10
1069#define MALONE_CODEC_ID_VC1_MAIN 0x11
1070#define MALONE_CODEC_ID_ARV8 0x28
1071#define MALONE_CODEC_ID_ARV9 0x29
1072#define MALONE_CODEC_ID_VP6 0x36
1073#define MALONE_CODEC_ID_VP8 0x36
1074#define MALONE_CODEC_ID_DIVX3 0x38
1075#define MALONE_CODEC_ID_SPK 0x39
1076
1077#define MALONE_VP8_IVF_SEQ_HEADER_LEN 32
1078#define MALONE_VP8_IVF_FRAME_HEADER_LEN 8
1079
1080#define MALONE_VC1_RCV_CODEC_V1_VERSION 0x85
1081#define MALONE_VC1_RCV_CODEC_V2_VERSION 0xC5
1082#define MALONE_VC1_RCV_NUM_FRAMES 0xFF
1083#define MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE 4
1084#define MALONE_VC1_RCV_SEQ_HEADER_LEN 20
1085#define MALONE_VC1_RCV_PIC_HEADER_LEN 4
1086#define MALONE_VC1_NAL_HEADER_LEN 4
1087#define MALONE_VC1_CONTAIN_NAL(data) (((data) & 0x00FFFFFF) == 0x00010000)
1088
1089static void set_payload_hdr(u8 *dst, u32 scd_type, u32 codec_id,
1090 u32 buffer_size, u32 width, u32 height)
1091{
1092 unsigned int payload_size;
1093
1094 payload_size = buffer_size + 12;
1095
1096 dst[0] = 0x00;
1097 dst[1] = 0x00;
1098 dst[2] = 0x01;
1099 dst[3] = scd_type;
1100
1101
1102 dst[4] = ((payload_size >> 16) & 0xff);
1103 dst[5] = ((payload_size >> 8) & 0xff);
1104 dst[6] = 0x4e;
1105 dst[7] = ((payload_size >> 0) & 0xff);
1106
1107
1108 dst[8] = codec_id;
1109 dst[9] = MALONE_CODEC_VERSION_ID;
1110
1111
1112 dst[10] = ((width >> 8) & 0xff);
1113 dst[11] = ((width >> 0) & 0xff);
1114 dst[12] = 0x58;
1115
1116
1117 dst[13] = ((height >> 8) & 0xff);
1118 dst[14] = ((height >> 0) & 0xff);
1119 dst[15] = 0x50;
1120}
1121
1122static void set_vp8_ivf_seqhdr(u8 *dst, u32 width, u32 height)
1123{
1124
1125 dst[0] = 0x44;
1126 dst[1] = 0x4b;
1127 dst[2] = 0x49;
1128 dst[3] = 0x46;
1129
1130 dst[4] = 0x00;
1131 dst[5] = 0x00;
1132
1133 dst[6] = MALONE_VP8_IVF_SEQ_HEADER_LEN;
1134 dst[7] = MALONE_VP8_IVF_SEQ_HEADER_LEN >> 8;
1135
1136 dst[8] = 0x56;
1137 dst[9] = 0x50;
1138 dst[10] = 0x38;
1139 dst[11] = 0x30;
1140
1141 dst[12] = width;
1142 dst[13] = width >> 8;
1143
1144 dst[14] = height;
1145 dst[15] = height >> 8;
1146
1147 dst[16] = 0xe8;
1148 dst[17] = 0x03;
1149 dst[18] = 0x00;
1150 dst[19] = 0x00;
1151
1152 dst[20] = 0x01;
1153 dst[21] = 0x00;
1154 dst[22] = 0x00;
1155 dst[23] = 0x00;
1156
1157 dst[24] = 0xdf;
1158 dst[25] = 0xf9;
1159 dst[26] = 0x09;
1160 dst[27] = 0x00;
1161
1162}
1163
1164static void set_vp8_ivf_pichdr(u8 *dst, u32 frame_size)
1165{
1166
1167
1168
1169
1170
1171}
1172
1173static void set_vc1_rcv_seqhdr(u8 *dst, u8 *src, u32 width, u32 height)
1174{
1175 u32 frames = MALONE_VC1_RCV_NUM_FRAMES;
1176 u32 ext_data_size = MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE;
1177
1178
1179 dst[0] = frames;
1180 dst[1] = frames >> 8;
1181 dst[2] = frames >> 16;
1182
1183
1184 dst[3] = MALONE_VC1_RCV_CODEC_V1_VERSION;
1185
1186
1187 dst[4] = ext_data_size;
1188 dst[5] = ext_data_size >> 8;
1189 dst[6] = ext_data_size >> 16;
1190 dst[7] = ext_data_size >> 24;
1191
1192 dst[8] = src[0];
1193 dst[9] = src[1];
1194 dst[10] = src[2];
1195 dst[11] = src[3];
1196
1197
1198 dst[12] = height;
1199 dst[13] = (height >> 8) & 0xff;
1200 dst[14] = (height >> 16) & 0xff;
1201 dst[15] = (height >> 24) & 0xff;
1202
1203 dst[16] = width;
1204 dst[17] = (width >> 8) & 0xff;
1205 dst[18] = (width >> 16) & 0xff;
1206 dst[19] = (width >> 24) & 0xff;
1207}
1208
1209static void set_vc1_rcv_pichdr(u8 *dst, u32 buffer_size)
1210{
1211 dst[0] = buffer_size;
1212 dst[1] = buffer_size >> 8;
1213 dst[2] = buffer_size >> 16;
1214 dst[3] = buffer_size >> 24;
1215}
1216
1217static void create_vc1_nal_pichdr(u8 *dst)
1218{
1219
1220 dst[0] = 0x0;
1221 dst[1] = 0x0;
1222 dst[2] = 0x01;
1223 dst[3] = 0x0D;
1224}
1225
1226static int vpu_malone_insert_scode_seq(struct malone_scode_t *scode, u32 codec_id, u32 ext_size)
1227{
1228 u8 hdr[MALONE_PAYLOAD_HEADER_SIZE];
1229 int ret;
1230
1231 set_payload_hdr(hdr,
1232 SCODE_SEQUENCE,
1233 codec_id,
1234 ext_size,
1235 scode->inst->out_format.width,
1236 scode->inst->out_format.height);
1237 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1238 &scode->wptr,
1239 sizeof(hdr),
1240 hdr);
1241 if (ret < 0)
1242 return ret;
1243 return sizeof(hdr);
1244}
1245
1246static int vpu_malone_insert_scode_pic(struct malone_scode_t *scode, u32 codec_id, u32 ext_size)
1247{
1248 u8 hdr[MALONE_PAYLOAD_HEADER_SIZE];
1249 int ret;
1250
1251 set_payload_hdr(hdr,
1252 SCODE_PICTURE,
1253 codec_id,
1254 ext_size + vb2_get_plane_payload(scode->vb, 0),
1255 scode->inst->out_format.width,
1256 scode->inst->out_format.height);
1257 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1258 &scode->wptr,
1259 sizeof(hdr),
1260 hdr);
1261 if (ret < 0)
1262 return ret;
1263 return sizeof(hdr);
1264}
1265
1266static int vpu_malone_insert_scode_vc1_g_pic(struct malone_scode_t *scode)
1267{
1268 struct vb2_v4l2_buffer *vbuf;
1269 u8 nal_hdr[MALONE_VC1_NAL_HEADER_LEN];
1270 u32 *data = NULL;
1271 int ret;
1272
1273 vbuf = to_vb2_v4l2_buffer(scode->vb);
1274 data = vb2_plane_vaddr(scode->vb, 0);
1275
1276 if (vbuf->sequence == 0 || vpu_vb_is_codecconfig(vbuf))
1277 return 0;
1278 if (MALONE_VC1_CONTAIN_NAL(*data))
1279 return 0;
1280
1281 create_vc1_nal_pichdr(nal_hdr);
1282 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1283 &scode->wptr,
1284 sizeof(nal_hdr),
1285 nal_hdr);
1286 if (ret < 0)
1287 return ret;
1288 return sizeof(nal_hdr);
1289}
1290
1291static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode)
1292{
1293 int ret;
1294 int size = 0;
1295 u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN];
1296
1297 scode->need_data = 0;
1298
1299 ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VC1_SIMPLE, sizeof(rcv_seqhdr));
1300 if (ret < 0)
1301 return ret;
1302 size = ret;
1303
1304 set_vc1_rcv_seqhdr(rcv_seqhdr,
1305 vb2_plane_vaddr(scode->vb, 0),
1306 scode->inst->out_format.width,
1307 scode->inst->out_format.height);
1308 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1309 &scode->wptr,
1310 sizeof(rcv_seqhdr),
1311 rcv_seqhdr);
1312
1313 if (ret < 0)
1314 return ret;
1315 size += sizeof(rcv_seqhdr);
1316 return size;
1317}
1318
1319static int vpu_malone_insert_scode_vc1_l_pic(struct malone_scode_t *scode)
1320{
1321 int ret;
1322 int size = 0;
1323 u8 rcv_pichdr[MALONE_VC1_RCV_PIC_HEADER_LEN];
1324
1325 ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VC1_SIMPLE,
1326 sizeof(rcv_pichdr));
1327 if (ret < 0)
1328 return ret;
1329 size = ret;
1330
1331 set_vc1_rcv_pichdr(rcv_pichdr, vb2_get_plane_payload(scode->vb, 0));
1332 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1333 &scode->wptr,
1334 sizeof(rcv_pichdr),
1335 rcv_pichdr);
1336 if (ret < 0)
1337 return ret;
1338 size += sizeof(rcv_pichdr);
1339 return size;
1340}
1341
1342static int vpu_malone_insert_scode_vp8_seq(struct malone_scode_t *scode)
1343{
1344 int ret;
1345 int size = 0;
1346 u8 ivf_hdr[MALONE_VP8_IVF_SEQ_HEADER_LEN];
1347
1348 ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr));
1349 if (ret < 0)
1350 return ret;
1351 size = ret;
1352
1353 set_vp8_ivf_seqhdr(ivf_hdr,
1354 scode->inst->out_format.width,
1355 scode->inst->out_format.height);
1356 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1357 &scode->wptr,
1358 sizeof(ivf_hdr),
1359 ivf_hdr);
1360 if (ret < 0)
1361 return ret;
1362 size += sizeof(ivf_hdr);
1363
1364 return size;
1365}
1366
1367static int vpu_malone_insert_scode_vp8_pic(struct malone_scode_t *scode)
1368{
1369 int ret;
1370 int size = 0;
1371 u8 ivf_hdr[MALONE_VP8_IVF_FRAME_HEADER_LEN] = {0};
1372
1373 ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr));
1374 if (ret < 0)
1375 return ret;
1376 size = ret;
1377
1378 set_vp8_ivf_pichdr(ivf_hdr, vb2_get_plane_payload(scode->vb, 0));
1379 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1380 &scode->wptr,
1381 sizeof(ivf_hdr),
1382 ivf_hdr);
1383 if (ret < 0)
1384 return ret;
1385 size += sizeof(ivf_hdr);
1386
1387 return size;
1388}
1389
1390static const struct malone_scode_handler scode_handlers[] = {
1391 {
1392
1393 .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_L,
1394 .insert_scode_seq = vpu_malone_insert_scode_vc1_l_seq,
1395 .insert_scode_pic = vpu_malone_insert_scode_vc1_l_pic,
1396 },
1397 {
1398 .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_G,
1399 .insert_scode_pic = vpu_malone_insert_scode_vc1_g_pic,
1400 },
1401 {
1402 .pixelformat = V4L2_PIX_FMT_VP8,
1403 .insert_scode_seq = vpu_malone_insert_scode_vp8_seq,
1404 .insert_scode_pic = vpu_malone_insert_scode_vp8_pic,
1405 },
1406};
1407
1408static const struct malone_scode_handler *get_scode_handler(u32 pixelformat)
1409{
1410 int i;
1411
1412 for (i = 0; i < ARRAY_SIZE(scode_handlers); i++) {
1413 if (scode_handlers[i].pixelformat == pixelformat)
1414 return &scode_handlers[i];
1415 }
1416
1417 return NULL;
1418}
1419
1420static int vpu_malone_insert_scode(struct malone_scode_t *scode, u32 type)
1421{
1422 const struct malone_scode_handler *handler;
1423 int ret = 0;
1424
1425 if (!scode || !scode->inst || !scode->vb)
1426 return 0;
1427
1428 scode->need_data = 1;
1429 handler = get_scode_handler(scode->inst->out_format.pixfmt);
1430 if (!handler)
1431 return 0;
1432
1433 switch (type) {
1434 case SCODE_SEQUENCE:
1435 if (handler->insert_scode_seq)
1436 ret = handler->insert_scode_seq(scode);
1437 break;
1438 case SCODE_PICTURE:
1439 if (handler->insert_scode_pic)
1440 ret = handler->insert_scode_pic(scode);
1441 break;
1442 default:
1443 break;
1444 }
1445
1446 return ret;
1447}
1448
1449static int vpu_malone_input_frame_data(struct vpu_malone_str_buffer __iomem *str_buf,
1450 struct vpu_inst *inst, struct vb2_buffer *vb,
1451 u32 disp_imm)
1452{
1453 struct malone_scode_t scode;
1454 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1455 u32 wptr = readl(&str_buf->wptr);
1456 int size = 0;
1457 int ret = 0;
1458
1459
1460 scode.inst = inst;
1461 scode.vb = vb;
1462 scode.wptr = wptr;
1463 scode.need_data = 1;
1464 if (vbuf->sequence == 0 || vpu_vb_is_codecconfig(vbuf))
1465 ret = vpu_malone_insert_scode(&scode, SCODE_SEQUENCE);
1466
1467 if (ret < 0)
1468 return -ENOMEM;
1469 size += ret;
1470 wptr = scode.wptr;
1471 if (!scode.need_data) {
1472 vpu_malone_update_wptr(str_buf, wptr);
1473 return size;
1474 }
1475
1476 ret = vpu_malone_insert_scode(&scode, SCODE_PICTURE);
1477 if (ret < 0)
1478 return -ENOMEM;
1479 size += ret;
1480 wptr = scode.wptr;
1481
1482 ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer,
1483 &wptr,
1484 vb2_get_plane_payload(vb, 0),
1485 vb2_plane_vaddr(vb, 0));
1486 if (ret < 0)
1487 return -ENOMEM;
1488 size += vb2_get_plane_payload(vb, 0);
1489
1490 vpu_malone_update_wptr(str_buf, wptr);
1491
1492 if (disp_imm && !vpu_vb_is_codecconfig(vbuf)) {
1493 ret = vpu_malone_add_scode(inst->core->iface,
1494 inst->id,
1495 &inst->stream_buffer,
1496 inst->out_format.pixfmt,
1497 SCODE_PADDING_BUFFLUSH);
1498 if (ret < 0)
1499 return ret;
1500 size += ret;
1501 }
1502
1503 return size;
1504}
1505
1506static int vpu_malone_input_stream_data(struct vpu_malone_str_buffer __iomem *str_buf,
1507 struct vpu_inst *inst, struct vb2_buffer *vb)
1508{
1509 u32 wptr = readl(&str_buf->wptr);
1510 int ret = 0;
1511
1512 ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer,
1513 &wptr,
1514 vb2_get_plane_payload(vb, 0),
1515 vb2_plane_vaddr(vb, 0));
1516 if (ret < 0)
1517 return -ENOMEM;
1518
1519 vpu_malone_update_wptr(str_buf, wptr);
1520
1521 return ret;
1522}
1523
1524static int vpu_malone_input_ts(struct vpu_inst *inst, s64 timestamp, u32 size)
1525{
1526 struct vpu_ts_info info;
1527
1528 memset(&info, 0, sizeof(info));
1529 info.timestamp = timestamp;
1530 info.size = size;
1531
1532 return vpu_session_fill_timestamp(inst, &info);
1533}
1534
1535int vpu_malone_input_frame(struct vpu_shared_addr *shared,
1536 struct vpu_inst *inst, struct vb2_buffer *vb)
1537{
1538 struct vpu_dec_ctrl *hc = shared->priv;
1539 struct vb2_v4l2_buffer *vbuf;
1540 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[inst->id];
1541 u32 disp_imm = hc->codec_param[inst->id].disp_imm;
1542 u32 size;
1543 int ret;
1544
1545 if (vpu_malone_is_non_frame_mode(shared, inst->id))
1546 ret = vpu_malone_input_stream_data(str_buf, inst, vb);
1547 else
1548 ret = vpu_malone_input_frame_data(str_buf, inst, vb, disp_imm);
1549 if (ret < 0)
1550 return ret;
1551 size = ret;
1552
1553
1554
1555
1556
1557
1558 vbuf = to_vb2_v4l2_buffer(vb);
1559 if (vpu_vb_is_codecconfig(vbuf) && (s64)vb->timestamp < 0) {
1560 inst->extra_size += size;
1561 return 0;
1562 }
1563 if (inst->extra_size) {
1564 size += inst->extra_size;
1565 inst->extra_size = 0;
1566 }
1567
1568 ret = vpu_malone_input_ts(inst, vb->timestamp, size);
1569 if (ret)
1570 return ret;
1571
1572 return 0;
1573}
1574
1575static bool vpu_malone_check_ready(struct vpu_shared_addr *shared, u32 instance)
1576{
1577 struct malone_iface *iface = shared->iface;
1578 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1579 u32 size = desc->end - desc->start;
1580 u32 rptr = desc->rptr;
1581 u32 wptr = desc->wptr;
1582 u32 used;
1583
1584 if (!size)
1585 return true;
1586
1587 used = (wptr + size - rptr) % size;
1588 if (used < (size / 2))
1589 return true;
1590
1591 return false;
1592}
1593
1594bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance)
1595{
1596 u32 cnt = 0;
1597
1598 while (!vpu_malone_check_ready(shared, instance)) {
1599 if (cnt > 30)
1600 return false;
1601 mdelay(1);
1602 cnt++;
1603 }
1604 return true;
1605}
1606
1607int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance)
1608{
1609 if (!vpu_malone_is_ready(shared, instance))
1610 return -EINVAL;
1611
1612 return 0;
1613}
1614
1615int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance)
1616{
1617 struct malone_iface *iface = shared->iface;
1618 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1619
1620 desc->wptr++;
1621 if (desc->wptr == desc->end)
1622 desc->wptr = desc->start;
1623
1624 return 0;
1625}
1626
1627int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance)
1628{
1629 struct malone_iface *iface = shared->iface;
1630 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1631
1632 desc->wptr = desc->rptr;
1633 if (desc->wptr == desc->end)
1634 desc->wptr = desc->start;
1635
1636 return 0;
1637}
1638
1639u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared)
1640{
1641 struct malone_iface *iface = shared->iface;
1642
1643 return iface->max_streams;
1644}
1645
