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10#ifndef _DW_MMC_H_
11#define _DW_MMC_H_
12
13#include <linux/scatterlist.h>
14#include <linux/mmc/core.h>
15#include <linux/dmaengine.h>
16#include <linux/reset.h>
17#include <linux/fault-inject.h>
18#include <linux/hrtimer.h>
19#include <linux/interrupt.h>
20
21enum dw_mci_state {
22 STATE_IDLE = 0,
23 STATE_SENDING_CMD,
24 STATE_SENDING_DATA,
25 STATE_DATA_BUSY,
26 STATE_SENDING_STOP,
27 STATE_DATA_ERROR,
28 STATE_SENDING_CMD11,
29 STATE_WAITING_CMD11_DONE,
30};
31
32enum {
33 EVENT_CMD_COMPLETE = 0,
34 EVENT_XFER_COMPLETE,
35 EVENT_DATA_COMPLETE,
36 EVENT_DATA_ERROR,
37};
38
39enum dw_mci_cookie {
40 COOKIE_UNMAPPED,
41 COOKIE_PRE_MAPPED,
42 COOKIE_MAPPED,
43};
44
45struct mmc_data;
46
47enum {
48 TRANS_MODE_PIO = 0,
49 TRANS_MODE_IDMAC,
50 TRANS_MODE_EDMAC
51};
52
53struct dw_mci_dma_slave {
54 struct dma_chan *ch;
55 enum dma_transfer_direction direction;
56};
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159struct dw_mci {
160 spinlock_t lock;
161 spinlock_t irq_lock;
162 void __iomem *regs;
163 void __iomem *fifo_reg;
164 u32 data_addr_override;
165 bool wm_aligned;
166
167 struct scatterlist *sg;
168 struct sg_mapping_iter sg_miter;
169
170 struct mmc_request *mrq;
171 struct mmc_command *cmd;
172 struct mmc_data *data;
173 struct mmc_command stop_abort;
174 unsigned int prev_blksz;
175 unsigned char timing;
176
177
178 int use_dma;
179 int using_dma;
180 int dma_64bit_address;
181
182 dma_addr_t sg_dma;
183 void *sg_cpu;
184 const struct dw_mci_dma_ops *dma_ops;
185
186 unsigned int ring_size;
187
188
189 struct dw_mci_dma_slave *dms;
190
191 resource_size_t phy_regs;
192
193 u32 cmd_status;
194 u32 data_status;
195 u32 stop_cmdr;
196 u32 dir_status;
197 struct tasklet_struct tasklet;
198 unsigned long pending_events;
199 unsigned long completed_events;
200 enum dw_mci_state state;
201 struct list_head queue;
202
203 u32 bus_hz;
204 u32 current_speed;
205 u32 minimum_speed;
206 u32 fifoth_val;
207 u16 verid;
208 struct device *dev;
209 struct dw_mci_board *pdata;
210 const struct dw_mci_drv_data *drv_data;
211 void *priv;
212 struct clk *biu_clk;
213 struct clk *ciu_clk;
214 struct dw_mci_slot *slot;
215
216
217 int fifo_depth;
218 int data_shift;
219 u8 part_buf_start;
220 u8 part_buf_count;
221 union {
222 u16 part_buf16;
223 u32 part_buf32;
224 u64 part_buf;
225 };
226 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
227 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
228
229 u32 quirks;
230 bool vqmmc_enabled;
231 unsigned long irq_flags;
232 int irq;
233
234 int sdio_id0;
235
236 struct timer_list cmd11_timer;
237 struct timer_list cto_timer;
238 struct timer_list dto_timer;
239
240#ifdef CONFIG_FAULT_INJECTION
241 struct fault_attr fail_data_crc;
242 struct hrtimer fault_timer;
243#endif
244};
245
246
247struct dw_mci_dma_ops {
248
249 int (*init)(struct dw_mci *host);
250 int (*start)(struct dw_mci *host, unsigned int sg_len);
251 void (*complete)(void *host);
252 void (*stop)(struct dw_mci *host);
253 void (*cleanup)(struct dw_mci *host);
254 void (*exit)(struct dw_mci *host);
255};
256
257struct dma_pdata;
258
259
260struct dw_mci_board {
261 unsigned int bus_hz;
262
263 u32 caps;
264 u32 caps2;
265 u32 pm_caps;
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271 unsigned int fifo_depth;
272
273
274 u32 detect_delay_ms;
275
276 struct reset_control *rstc;
277 struct dw_mci_dma_ops *dma_ops;
278 struct dma_pdata *data;
279};
280
281
282#define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0)
283
284#define DW_MMC_240A 0x240a
285#define DW_MMC_280A 0x280a
286
287#define SDMMC_CTRL 0x000
288#define SDMMC_PWREN 0x004
289#define SDMMC_CLKDIV 0x008
290#define SDMMC_CLKSRC 0x00c
291#define SDMMC_CLKENA 0x010
292#define SDMMC_TMOUT 0x014
293#define SDMMC_CTYPE 0x018
294#define SDMMC_BLKSIZ 0x01c
295#define SDMMC_BYTCNT 0x020
296#define SDMMC_INTMASK 0x024
297#define SDMMC_CMDARG 0x028
298#define SDMMC_CMD 0x02c
299#define SDMMC_RESP0 0x030
300#define SDMMC_RESP1 0x034
301#define SDMMC_RESP2 0x038
302#define SDMMC_RESP3 0x03c
303#define SDMMC_MINTSTS 0x040
304#define SDMMC_RINTSTS 0x044
305#define SDMMC_STATUS 0x048
306#define SDMMC_FIFOTH 0x04c
307#define SDMMC_CDETECT 0x050
308#define SDMMC_WRTPRT 0x054
309#define SDMMC_GPIO 0x058
310#define SDMMC_TCBCNT 0x05c
311#define SDMMC_TBBCNT 0x060
312#define SDMMC_DEBNCE 0x064
313#define SDMMC_USRID 0x068
314#define SDMMC_VERID 0x06c
315#define SDMMC_HCON 0x070
316#define SDMMC_UHS_REG 0x074
317#define SDMMC_RST_N 0x078
318#define SDMMC_BMOD 0x080
319#define SDMMC_PLDMND 0x084
320#define SDMMC_DBADDR 0x088
321#define SDMMC_IDSTS 0x08c
322#define SDMMC_IDINTEN 0x090
323#define SDMMC_DSCADDR 0x094
324#define SDMMC_BUFADDR 0x098
325#define SDMMC_CDTHRCTL 0x100
326#define SDMMC_UHS_REG_EXT 0x108
327#define SDMMC_DDR_REG 0x10c
328#define SDMMC_ENABLE_SHIFT 0x110
329#define SDMMC_DATA(x) (x)
330
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332
333#define SDMMC_DBADDRL 0x088
334#define SDMMC_DBADDRU 0x08c
335#define SDMMC_IDSTS64 0x090
336#define SDMMC_IDINTEN64 0x094
337#define SDMMC_DSCADDRL 0x098
338#define SDMMC_DSCADDRU 0x09c
339#define SDMMC_BUFADDRL 0x0A0
340#define SDMMC_BUFADDRU 0x0A4
341
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344
345
346#define DATA_OFFSET 0x100
347#define DATA_240A_OFFSET 0x200
348
349
350#define _SBF(f, v) ((v) << (f))
351
352
353#define SDMMC_CTRL_USE_IDMAC BIT(25)
354#define SDMMC_CTRL_CEATA_INT_EN BIT(11)
355#define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
356#define SDMMC_CTRL_SEND_CCSD BIT(9)
357#define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
358#define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
359#define SDMMC_CTRL_READ_WAIT BIT(6)
360#define SDMMC_CTRL_DMA_ENABLE BIT(5)
361#define SDMMC_CTRL_INT_ENABLE BIT(4)
362#define SDMMC_CTRL_DMA_RESET BIT(2)
363#define SDMMC_CTRL_FIFO_RESET BIT(1)
364#define SDMMC_CTRL_RESET BIT(0)
365
366#define SDMMC_CLKEN_LOW_PWR BIT(16)
367#define SDMMC_CLKEN_ENABLE BIT(0)
368
369#define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
370#define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
371#define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
372#define SDMMC_TMOUT_RESP_MSK 0xFF
373
374#define SDMMC_CTYPE_8BIT BIT(16)
375#define SDMMC_CTYPE_4BIT BIT(0)
376#define SDMMC_CTYPE_1BIT 0
377
378#define SDMMC_INT_SDIO(n) BIT(16 + (n))
379#define SDMMC_INT_EBE BIT(15)
380#define SDMMC_INT_ACD BIT(14)
381#define SDMMC_INT_SBE BIT(13)
382#define SDMMC_INT_HLE BIT(12)
383#define SDMMC_INT_FRUN BIT(11)
384#define SDMMC_INT_HTO BIT(10)
385#define SDMMC_INT_VOLT_SWITCH BIT(10)
386#define SDMMC_INT_DRTO BIT(9)
387#define SDMMC_INT_RTO BIT(8)
388#define SDMMC_INT_DCRC BIT(7)
389#define SDMMC_INT_RCRC BIT(6)
390#define SDMMC_INT_RXDR BIT(5)
391#define SDMMC_INT_TXDR BIT(4)
392#define SDMMC_INT_DATA_OVER BIT(3)
393#define SDMMC_INT_CMD_DONE BIT(2)
394#define SDMMC_INT_RESP_ERR BIT(1)
395#define SDMMC_INT_CD BIT(0)
396#define SDMMC_INT_ERROR 0xbfc2
397
398#define SDMMC_CMD_START BIT(31)
399#define SDMMC_CMD_USE_HOLD_REG BIT(29)
400#define SDMMC_CMD_VOLT_SWITCH BIT(28)
401#define SDMMC_CMD_CCS_EXP BIT(23)
402#define SDMMC_CMD_CEATA_RD BIT(22)
403#define SDMMC_CMD_UPD_CLK BIT(21)
404#define SDMMC_CMD_INIT BIT(15)
405#define SDMMC_CMD_STOP BIT(14)
406#define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
407#define SDMMC_CMD_SEND_STOP BIT(12)
408#define SDMMC_CMD_STRM_MODE BIT(11)
409#define SDMMC_CMD_DAT_WR BIT(10)
410#define SDMMC_CMD_DAT_EXP BIT(9)
411#define SDMMC_CMD_RESP_CRC BIT(8)
412#define SDMMC_CMD_RESP_LONG BIT(7)
413#define SDMMC_CMD_RESP_EXP BIT(6)
414#define SDMMC_CMD_INDX(n) ((n) & 0x1F)
415
416#define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
417#define SDMMC_STATUS_DMA_REQ BIT(31)
418#define SDMMC_STATUS_BUSY BIT(9)
419
420#define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
421 ((r) & 0xFFF) << 16 | \
422 ((t) & 0xFFF))
423
424#define DMA_INTERFACE_IDMA (0x0)
425#define DMA_INTERFACE_DWDMA (0x1)
426#define DMA_INTERFACE_GDMA (0x2)
427#define DMA_INTERFACE_NODMA (0x3)
428#define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
429#define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
430#define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
431#define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
432
433#define SDMMC_IDMAC_INT_AI BIT(9)
434#define SDMMC_IDMAC_INT_NI BIT(8)
435#define SDMMC_IDMAC_INT_CES BIT(5)
436#define SDMMC_IDMAC_INT_DU BIT(4)
437#define SDMMC_IDMAC_INT_FBE BIT(2)
438#define SDMMC_IDMAC_INT_RI BIT(1)
439#define SDMMC_IDMAC_INT_TI BIT(0)
440
441#define SDMMC_IDMAC_ENABLE BIT(7)
442#define SDMMC_IDMAC_FB BIT(1)
443#define SDMMC_IDMAC_SWRESET BIT(0)
444
445#define SDMMC_RST_HWACTIVE 0x1
446
447#define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
448
449#define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
450#define SDMMC_CARD_WR_THR_EN BIT(2)
451#define SDMMC_CARD_RD_THR_EN BIT(0)
452
453#define SDMMC_UHS_DDR BIT(16)
454#define SDMMC_UHS_18V BIT(0)
455
456#define SDMMC_DDR_HS400 BIT(31)
457
458#define SDMMC_ENABLE_PHASE BIT(0)
459
460#define SDMMC_CTRL_ALL_RESET_FLAGS \
461 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
462
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465
466#define mci_fifo_readw(__reg) __raw_readw(__reg)
467#define mci_fifo_readl(__reg) __raw_readl(__reg)
468#define mci_fifo_readq(__reg) __raw_readq(__reg)
469
470#define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
471#define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
472#define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
473
474
475#define mci_readl(dev, reg) \
476 readl_relaxed((dev)->regs + SDMMC_##reg)
477#define mci_writel(dev, reg, value) \
478 writel_relaxed((value), (dev)->regs + SDMMC_##reg)
479
480
481#define mci_readw(dev, reg) \
482 readw_relaxed((dev)->regs + SDMMC_##reg)
483#define mci_writew(dev, reg, value) \
484 writew_relaxed((value), (dev)->regs + SDMMC_##reg)
485
486
487#ifdef readq
488#define mci_readq(dev, reg) \
489 readq_relaxed((dev)->regs + SDMMC_##reg)
490#define mci_writeq(dev, reg, value) \
491 writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
492#else
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501#define mci_readq(dev, reg) \
502 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
503#define mci_writeq(dev, reg, value) \
504 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
505
506#define __raw_writeq(__value, __reg) \
507 (*(volatile u64 __force *)(__reg) = (__value))
508#define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
509#endif
510
511extern int dw_mci_probe(struct dw_mci *host);
512extern void dw_mci_remove(struct dw_mci *host);
513#ifdef CONFIG_PM
514extern int dw_mci_runtime_suspend(struct device *device);
515extern int dw_mci_runtime_resume(struct device *device);
516#endif
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534struct dw_mci_slot {
535 struct mmc_host *mmc;
536 struct dw_mci *host;
537
538 u32 ctype;
539
540 struct mmc_request *mrq;
541 struct list_head queue_node;
542
543 unsigned int clock;
544 unsigned int __clk_old;
545
546 unsigned long flags;
547#define DW_MMC_CARD_PRESENT 0
548#define DW_MMC_CARD_NEED_INIT 1
549#define DW_MMC_CARD_NO_LOW_PWR 2
550#define DW_MMC_CARD_NO_USE_HOLD 3
551#define DW_MMC_CARD_NEEDS_POLL 4
552 int id;
553 int sdio_id;
554};
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573struct dw_mci_drv_data {
574 unsigned long *caps;
575 u32 num_caps;
576 u32 common_caps;
577 int (*init)(struct dw_mci *host);
578 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
579 int (*parse_dt)(struct dw_mci *host);
580 int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode);
581 int (*prepare_hs400_tuning)(struct dw_mci *host,
582 struct mmc_ios *ios);
583 int (*switch_voltage)(struct mmc_host *mmc,
584 struct mmc_ios *ios);
585 void (*set_data_timeout)(struct dw_mci *host,
586 unsigned int timeout_ns);
587 u32 (*get_drto_clks)(struct dw_mci *host);
588};
589#endif
590