LXR linux/drivers/mmc/host/mmci.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 *  linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
   4 *
   5 *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
   6 */
   7#define MMCIPOWER               0x000
   8#define MCI_PWR_OFF             0x00
   9#define MCI_PWR_UP              0x02
  10#define MCI_PWR_ON              0x03
  11#define MCI_OD                  (1 << 6)
  12#define MCI_ROD                 (1 << 7)
  13/*
  14 * The ST Micro version does not have ROD and reuse the voltage registers for
  15 * direction settings.
  16 */
  17#define MCI_ST_DATA2DIREN       (1 << 2)
  18#define MCI_ST_CMDDIREN         (1 << 3)
  19#define MCI_ST_DATA0DIREN       (1 << 4)
  20#define MCI_ST_DATA31DIREN      (1 << 5)
  21#define MCI_ST_FBCLKEN          (1 << 7)
  22#define MCI_ST_DATA74DIREN      (1 << 8)
  23/*
  24 * The STM32 sdmmc does not have PWR_UP/OD/ROD
  25 * and uses the power register for
  26 */
  27#define MCI_STM32_PWR_CYC       0x02
  28#define MCI_STM32_VSWITCH       BIT(2)
  29#define MCI_STM32_VSWITCHEN     BIT(3)
  30#define MCI_STM32_DIRPOL        BIT(4)
  31
  32#define MMCICLOCK               0x004
  33#define MCI_CLK_ENABLE          (1 << 8)
  34#define MCI_CLK_PWRSAVE         (1 << 9)
  35#define MCI_CLK_BYPASS          (1 << 10)
  36#define MCI_4BIT_BUS            (1 << 11)
  37/*
  38 * 8bit wide buses, hardware flow contronl, negative edges and clock inversion
  39 * supported in ST Micro U300 and Ux500 versions
  40 */
  41#define MCI_ST_8BIT_BUS         (1 << 12)
  42#define MCI_ST_U300_HWFCEN      (1 << 13)
  43#define MCI_ST_UX500_NEG_EDGE   (1 << 13)
  44#define MCI_ST_UX500_HWFCEN     (1 << 14)
  45#define MCI_ST_UX500_CLK_INV    (1 << 15)
  46/* Modified PL180 on Versatile Express platform */
  47#define MCI_ARM_HWFCEN          (1 << 12)
  48
  49/* Modified on Qualcomm Integrations */
  50#define MCI_QCOM_CLK_WIDEBUS_8  (BIT(10) | BIT(11))
  51#define MCI_QCOM_CLK_FLOWENA    BIT(12)
  52#define MCI_QCOM_CLK_INVERTOUT  BIT(13)
  53
  54/* select in latch data and command in */
  55#define MCI_QCOM_CLK_SELECT_IN_FBCLK    BIT(15)
  56#define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15))
  57
  58/* Modified on STM32 sdmmc */
  59#define MCI_STM32_CLK_CLKDIV_MSK        GENMASK(9, 0)
  60#define MCI_STM32_CLK_WIDEBUS_4         BIT(14)
  61#define MCI_STM32_CLK_WIDEBUS_8         BIT(15)
  62#define MCI_STM32_CLK_NEGEDGE           BIT(16)
  63#define MCI_STM32_CLK_HWFCEN            BIT(17)
  64#define MCI_STM32_CLK_DDR               BIT(18)
  65#define MCI_STM32_CLK_BUSSPEED          BIT(19)
  66#define MCI_STM32_CLK_SEL_MSK           GENMASK(21, 20)
  67#define MCI_STM32_CLK_SELCK             (0 << 20)
  68#define MCI_STM32_CLK_SELCKIN           (1 << 20)
  69#define MCI_STM32_CLK_SELFBCK           (2 << 20)
  70
  71#define MMCIARGUMENT            0x008
  72
  73/* The command register controls the Command Path State Machine (CPSM) */
  74#define MMCICOMMAND             0x00c
  75#define MCI_CPSM_RESPONSE       BIT(6)
  76#define MCI_CPSM_LONGRSP        BIT(7)
  77#define MCI_CPSM_INTERRUPT      BIT(8)
  78#define MCI_CPSM_PENDING        BIT(9)
  79#define MCI_CPSM_ENABLE         BIT(10)
  80/* Command register flag extenstions in the ST Micro versions */
  81#define MCI_CPSM_ST_SDIO_SUSP           BIT(11)
  82#define MCI_CPSM_ST_ENCMD_COMPL         BIT(12)
  83#define MCI_CPSM_ST_NIEN                BIT(13)
  84#define MCI_CPSM_ST_CE_ATACMD           BIT(14)
  85/* Command register flag extensions in the Qualcomm versions */
  86#define MCI_CPSM_QCOM_PROGENA           BIT(11)
  87#define MCI_CPSM_QCOM_DATCMD            BIT(12)
  88#define MCI_CPSM_QCOM_MCIABORT          BIT(13)
  89#define MCI_CPSM_QCOM_CCSENABLE         BIT(14)
  90#define MCI_CPSM_QCOM_CCSDISABLE        BIT(15)
  91#define MCI_CPSM_QCOM_AUTO_CMD19        BIT(16)
  92#define MCI_CPSM_QCOM_AUTO_CMD21        BIT(21)
  93/* Command register in STM32 sdmmc versions */
  94#define MCI_CPSM_STM32_CMDTRANS         BIT(6)
  95#define MCI_CPSM_STM32_CMDSTOP          BIT(7)
  96#define MCI_CPSM_STM32_WAITRESP_MASK    GENMASK(9, 8)
  97#define MCI_CPSM_STM32_NORSP            (0 << 8)
  98#define MCI_CPSM_STM32_SRSP_CRC         (1 << 8)
  99#define MCI_CPSM_STM32_SRSP             (2 << 8)
 100#define MCI_CPSM_STM32_LRSP_CRC         (3 << 8)
 101#define MCI_CPSM_STM32_ENABLE           BIT(12)
 102
 103#define MMCIRESPCMD             0x010
 104#define MMCIRESPONSE0           0x014
 105#define MMCIRESPONSE1           0x018
 106#define MMCIRESPONSE2           0x01c
 107#define MMCIRESPONSE3           0x020
 108#define MMCIDATATIMER           0x024
 109#define MMCIDATALENGTH          0x028
 110
 111/* The data control register controls the Data Path State Machine (DPSM) */
 112#define MMCIDATACTRL            0x02c
 113#define MCI_DPSM_ENABLE         BIT(0)
 114#define MCI_DPSM_DIRECTION      BIT(1)
 115#define MCI_DPSM_MODE           BIT(2)
 116#define MCI_DPSM_DMAENABLE      BIT(3)
 117#define MCI_DPSM_BLOCKSIZE      BIT(4)
 118/* Control register extensions in the ST Micro U300 and Ux500 versions */
 119#define MCI_DPSM_ST_RWSTART     BIT(8)
 120#define MCI_DPSM_ST_RWSTOP      BIT(9)
 121#define MCI_DPSM_ST_RWMOD       BIT(10)
 122#define MCI_DPSM_ST_SDIOEN      BIT(11)
 123/* Control register extensions in the ST Micro Ux500 versions */
 124#define MCI_DPSM_ST_DMAREQCTL   BIT(12)
 125#define MCI_DPSM_ST_DBOOTMODEEN BIT(13)
 126#define MCI_DPSM_ST_BUSYMODE    BIT(14)
 127#define MCI_DPSM_ST_DDRMODE     BIT(15)
 128/* Control register extensions in the Qualcomm versions */
 129#define MCI_DPSM_QCOM_DATA_PEND BIT(17)
 130#define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20)
 131/* Control register extensions in STM32 versions */
 132#define MCI_DPSM_STM32_MODE_BLOCK       (0 << 2)
 133#define MCI_DPSM_STM32_MODE_SDIO        (1 << 2)
 134#define MCI_DPSM_STM32_MODE_STREAM      (2 << 2)
 135#define MCI_DPSM_STM32_MODE_BLOCK_STOP  (3 << 2)
 136
 137#define MMCIDATACNT             0x030
 138#define MMCISTATUS              0x034
 139#define MCI_CMDCRCFAIL          (1 << 0)
 140#define MCI_DATACRCFAIL         (1 << 1)
 141#define MCI_CMDTIMEOUT          (1 << 2)
 142#define MCI_DATATIMEOUT         (1 << 3)
 143#define MCI_TXUNDERRUN          (1 << 4)
 144#define MCI_RXOVERRUN           (1 << 5)
 145#define MCI_CMDRESPEND          (1 << 6)
 146#define MCI_CMDSENT             (1 << 7)
 147#define MCI_DATAEND             (1 << 8)
 148#define MCI_STARTBITERR         (1 << 9)
 149#define MCI_DATABLOCKEND        (1 << 10)
 150#define MCI_CMDACTIVE           (1 << 11)
 151#define MCI_TXACTIVE            (1 << 12)
 152#define MCI_RXACTIVE            (1 << 13)
 153#define MCI_TXFIFOHALFEMPTY     (1 << 14)
 154#define MCI_RXFIFOHALFFULL      (1 << 15)
 155#define MCI_TXFIFOFULL          (1 << 16)
 156#define MCI_RXFIFOFULL          (1 << 17)
 157#define MCI_TXFIFOEMPTY         (1 << 18)
 158#define MCI_RXFIFOEMPTY         (1 << 19)
 159#define MCI_TXDATAAVLBL         (1 << 20)
 160#define MCI_RXDATAAVLBL         (1 << 21)
 161/* Extended status bits for the ST Micro variants */
 162#define MCI_ST_SDIOIT           (1 << 22)
 163#define MCI_ST_CEATAEND         (1 << 23)
 164#define MCI_ST_CARDBUSY         (1 << 24)
 165/* Extended status bits for the STM32 variants */
 166#define MCI_STM32_BUSYD0        BIT(20)
 167#define MCI_STM32_BUSYD0END     BIT(21)
 168#define MCI_STM32_VSWEND        BIT(25)
 169
 170#define MMCICLEAR               0x038
 171#define MCI_CMDCRCFAILCLR       (1 << 0)
 172#define MCI_DATACRCFAILCLR      (1 << 1)
 173#define MCI_CMDTIMEOUTCLR       (1 << 2)
 174#define MCI_DATATIMEOUTCLR      (1 << 3)
 175#define MCI_TXUNDERRUNCLR       (1 << 4)
 176#define MCI_RXOVERRUNCLR        (1 << 5)
 177#define MCI_CMDRESPENDCLR       (1 << 6)
 178#define MCI_CMDSENTCLR          (1 << 7)
 179#define MCI_DATAENDCLR          (1 << 8)
 180#define MCI_STARTBITERRCLR      (1 << 9)
 181#define MCI_DATABLOCKENDCLR     (1 << 10)
 182/* Extended status bits for the ST Micro variants */
 183#define MCI_ST_SDIOITC          (1 << 22)
 184#define MCI_ST_CEATAENDC        (1 << 23)
 185#define MCI_ST_BUSYENDC         (1 << 24)
 186/* Extended clear bits for the STM32 variants */
 187#define MCI_STM32_VSWENDC       BIT(25)
 188#define MCI_STM32_CKSTOPC       BIT(26)
 189
 190#define MMCIMASK0               0x03c
 191#define MCI_CMDCRCFAILMASK      (1 << 0)
 192#define MCI_DATACRCFAILMASK     (1 << 1)
 193#define MCI_CMDTIMEOUTMASK      (1 << 2)
 194#define MCI_DATATIMEOUTMASK     (1 << 3)
 195#define MCI_TXUNDERRUNMASK      (1 << 4)
 196#define MCI_RXOVERRUNMASK       (1 << 5)
 197#define MCI_CMDRESPENDMASK      (1 << 6)
 198#define MCI_CMDSENTMASK         (1 << 7)
 199#define MCI_DATAENDMASK         (1 << 8)
 200#define MCI_STARTBITERRMASK     (1 << 9)
 201#define MCI_DATABLOCKENDMASK    (1 << 10)
 202#define MCI_CMDACTIVEMASK       (1 << 11)
 203#define MCI_TXACTIVEMASK        (1 << 12)
 204#define MCI_RXACTIVEMASK        (1 << 13)
 205#define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
 206#define MCI_RXFIFOHALFFULLMASK  (1 << 15)
 207#define MCI_TXFIFOFULLMASK      (1 << 16)
 208#define MCI_RXFIFOFULLMASK      (1 << 17)
 209#define MCI_TXFIFOEMPTYMASK     (1 << 18)
 210#define MCI_RXFIFOEMPTYMASK     (1 << 19)
 211#define MCI_TXDATAAVLBLMASK     (1 << 20)
 212#define MCI_RXDATAAVLBLMASK     (1 << 21)
 213/* Extended status bits for the ST Micro variants */
 214#define MCI_ST_SDIOITMASK       (1 << 22)
 215#define MCI_ST_CEATAENDMASK     (1 << 23)
 216#define MCI_ST_BUSYENDMASK      (1 << 24)
 217/* Extended status bits for the STM32 variants */
 218#define MCI_STM32_BUSYD0ENDMASK BIT(21)
 219
 220#define MMCIMASK1               0x040
 221#define MMCIFIFOCNT             0x048
 222#define MMCIFIFO                0x080 /* to 0x0bc */
 223
 224/* STM32 sdmmc registers for IDMA (Internal DMA) */
 225#define MMCI_STM32_IDMACTRLR    0x050
 226#define MMCI_STM32_IDMAEN       BIT(0)
 227#define MMCI_STM32_IDMALLIEN    BIT(1)
 228
 229#define MMCI_STM32_IDMABSIZER           0x054
 230#define MMCI_STM32_IDMABNDT_SHIFT       5
 231#define MMCI_STM32_IDMABNDT_MASK        GENMASK(12, 5)
 232
 233#define MMCI_STM32_IDMABASE0R   0x058
 234
 235#define MMCI_STM32_IDMALAR      0x64
 236#define MMCI_STM32_IDMALA_MASK  GENMASK(13, 0)
 237#define MMCI_STM32_ABR          BIT(29)
 238#define MMCI_STM32_ULS          BIT(30)
 239#define MMCI_STM32_ULA          BIT(31)
 240
 241#define MMCI_STM32_IDMABAR      0x68
 242
 243#define MCI_IRQENABLE   \
 244        (MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \
 245        MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK |  \
 246        MCI_CMDRESPENDMASK | MCI_CMDSENTMASK)
 247
 248/* These interrupts are directed to IRQ1 when two IRQ lines are available */
 249#define MCI_IRQ_PIO_MASK \
 250        (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
 251         MCI_TXFIFOHALFEMPTYMASK)
 252
 253#define MCI_IRQ_PIO_STM32_MASK \
 254        (MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK)
 255
 256#define NR_SG           128
 257
 258#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
 259
 260struct clk;
 261struct dma_chan;
 262struct mmci_host;
 263
 264/**
 265 * struct variant_data - MMCI variant-specific quirks
 266 * @clkreg: default value for MCICLOCK register
 267 * @clkreg_enable: enable value for MMCICLOCK register
 268 * @clkreg_8bit_bus_enable: enable value for 8 bit bus
 269 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
 270 * @cmdreg_cpsm_enable: enable value for CPSM
 271 * @cmdreg_lrsp_crc: enable value for long response with crc
 272 * @cmdreg_srsp_crc: enable value for short response with crc
 273 * @cmdreg_srsp: enable value for short response without crc
 274 * @cmdreg_stop: enable value for stop and abort transmission
 275 * @datalength_bits: number of bits in the MMCIDATALENGTH register
 276 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
 277 *            is asserted (likewise for RX)
 278 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
 279 *                is asserted (likewise for RX)
 280 * @data_cmd_enable: enable value for data commands.
 281 * @st_sdio: enable ST specific SDIO logic
 282 * @st_clkdiv: true if using a ST-specific clock divider algorithm
 283 * @stm32_clkdiv: true if using a STM32-specific clock divider algorithm
 284 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
 285 * @datactrl_mask_sdio: SDIO enable mask in datactrl register
 286 * @datactrl_blocksz: block size in power of two
 287 * @datactrl_any_blocksz: true if block any block sizes are accepted by
 288 *                hardware, such as with some SDIO traffic that send
 289 *                odd packets.
 290 * @dma_power_of_2: DMA only works with blocks that are a power of 2.
 291 * @datactrl_first: true if data must be setup before send command
 292 * @datacnt_useless: true if you could not use datacnt register to read
 293 *                   remaining data
 294 * @pwrreg_powerup: power up value for MMCIPOWER register
 295 * @f_max: maximum clk frequency supported by the controller.
 296 * @signal_direction: input/out direction of bus signals can be indicated
 297 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
 298 * @busy_detect: true if the variant supports busy detection on DAT0.
 299 * @busy_timeout: true if the variant starts data timer when the DPSM
 300 *                enter in Wait_R or Busy state.
 301 * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
 302 * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
 303 *                    indicating that the card is busy
 304 * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for
 305 *                    getting busy end detection interrupts
 306 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
 307 * @explicit_mclk_control: enable explicit mclk control in driver.
 308 * @qcom_fifo: enables qcom specific fifo pio read logic.
 309 * @qcom_dml: enables qcom specific dma glue for dma transfers.
 310 * @reversed_irq_handling: handle data irq before cmd irq.
 311 * @mmcimask1: true if variant have a MMCIMASK1 register.
 312 * @irq_pio_mask: bitmask used to manage interrupt pio transfert in mmcimask
 313 *                register
 314 * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS
 315 *             register.
 316 * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
 317 * @dma_lli: true if variant has dma link list feature.
 318 * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.
 319 */
 320struct variant_data {
 321        unsigned int            clkreg;
 322        unsigned int            clkreg_enable;
 323        unsigned int            clkreg_8bit_bus_enable;
 324        unsigned int            clkreg_neg_edge_enable;
 325        unsigned int            cmdreg_cpsm_enable;
 326        unsigned int            cmdreg_lrsp_crc;
 327        unsigned int            cmdreg_srsp_crc;
 328        unsigned int            cmdreg_srsp;
 329        unsigned int            cmdreg_stop;
 330        unsigned int            datalength_bits;
 331        unsigned int            fifosize;
 332        unsigned int            fifohalfsize;
 333        unsigned int            data_cmd_enable;
 334        unsigned int            datactrl_mask_ddrmode;
 335        unsigned int            datactrl_mask_sdio;
 336        unsigned int            datactrl_blocksz;
 337        u8                      datactrl_any_blocksz:1;
 338        u8                      dma_power_of_2:1;
 339        u8                      datactrl_first:1;
 340        u8                      datacnt_useless:1;
 341        u8                      st_sdio:1;
 342        u8                      st_clkdiv:1;
 343        u8                      stm32_clkdiv:1;
 344        u32                     pwrreg_powerup;
 345        u32                     f_max;
 346        u8                      signal_direction:1;
 347        u8                      pwrreg_clkgate:1;
 348        u8                      busy_detect:1;
 349        u8                      busy_timeout:1;
 350        u32                     busy_dpsm_flag;
 351        u32                     busy_detect_flag;
 352        u32                     busy_detect_mask;
 353        u8                      pwrreg_nopower:1;
 354        u8                      explicit_mclk_control:1;
 355        u8                      qcom_fifo:1;
 356        u8                      qcom_dml:1;
 357        u8                      reversed_irq_handling:1;
 358        u8                      mmcimask1:1;
 359        unsigned int            irq_pio_mask;
 360        u32                     start_err;
 361        u32                     opendrain;
 362        u8                      dma_lli:1;
 363        u32                     stm32_idmabsize_mask;
 364        void (*init)(struct mmci_host *host);
 365};
 366
 367/* mmci variant callbacks */
 368struct mmci_host_ops {
 369        int (*validate_data)(struct mmci_host *host, struct mmc_data *data);
 370        int (*prep_data)(struct mmci_host *host, struct mmc_data *data,
 371                         bool next);
 372        void (*unprep_data)(struct mmci_host *host, struct mmc_data *data,
 373                            int err);
 374        u32 (*get_datactrl_cfg)(struct mmci_host *host);
 375        void (*get_next_data)(struct mmci_host *host, struct mmc_data *data);
 376        int (*dma_setup)(struct mmci_host *host);
 377        void (*dma_release)(struct mmci_host *host);
 378        int (*dma_start)(struct mmci_host *host, unsigned int *datactrl);
 379        void (*dma_finalize)(struct mmci_host *host, struct mmc_data *data);
 380        void (*dma_error)(struct mmci_host *host);
 381        void (*set_clkreg)(struct mmci_host *host, unsigned int desired);
 382        void (*set_pwrreg)(struct mmci_host *host, unsigned int pwr);
 383        bool (*busy_complete)(struct mmci_host *host, u32 status, u32 err_msk);
 384        void (*pre_sig_volt_switch)(struct mmci_host *host);
 385        int (*post_sig_volt_switch)(struct mmci_host *host, struct mmc_ios *ios);
 386};
 387
 388struct mmci_host {
 389        phys_addr_t             phybase;
 390        void __iomem            *base;
 391        struct mmc_request      *mrq;
 392        struct mmc_command      *cmd;
 393        struct mmc_command      stop_abort;
 394        struct mmc_data         *data;
 395        struct mmc_host         *mmc;
 396        struct clk              *clk;
 397        u8                      singleirq:1;
 398
 399        struct reset_control    *rst;
 400
 401        spinlock_t              lock;
 402
 403        unsigned int            mclk;
 404        /* cached value of requested clk in set_ios */
 405        unsigned int            clock_cache;
 406        unsigned int            cclk;
 407        u32                     pwr_reg;
 408        u32                     pwr_reg_add;
 409        u32                     clk_reg;
 410        u32                     clk_reg_add;
 411        u32                     datactrl_reg;
 412        u32                     busy_status;
 413        u32                     mask1_reg;
 414        u8                      vqmmc_enabled:1;
 415        struct mmci_platform_data *plat;
 416        struct mmc_host_ops     *mmc_ops;
 417        struct mmci_host_ops    *ops;
 418        struct variant_data     *variant;
 419        void                    *variant_priv;
 420        struct pinctrl          *pinctrl;
 421        struct pinctrl_state    *pins_opendrain;
 422
 423        u8                      hw_designer;
 424        u8                      hw_revision:4;
 425
 426        struct timer_list       timer;
 427        unsigned int            oldstat;
 428        u32                     irq_action;
 429
 430        /* pio stuff */
 431        struct sg_mapping_iter  sg_miter;
 432        unsigned int            size;
 433        int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain);
 434
 435        u8                      use_dma:1;
 436        u8                      dma_in_progress:1;
 437        void                    *dma_priv;
 438
 439        s32                     next_cookie;
 440};
 441
 442#define dma_inprogress(host)    ((host)->dma_in_progress)
 443
 444void mmci_write_clkreg(struct mmci_host *host, u32 clk);
 445void mmci_write_pwrreg(struct mmci_host *host, u32 pwr);
 446
 447static inline u32 mmci_dctrl_blksz(struct mmci_host *host)
 448{
 449        return (ffs(host->data->blksz) - 1) << 4;
 450}
 451
 452#ifdef CONFIG_DMA_ENGINE
 453int mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
 454                        bool next);
 455void mmci_dmae_unprep_data(struct mmci_host *host, struct mmc_data *data,
 456                           int err);
 457void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data);
 458int mmci_dmae_setup(struct mmci_host *host);
 459void mmci_dmae_release(struct mmci_host *host);
 460int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl);
 461void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data);
 462void mmci_dmae_error(struct mmci_host *host);
 463#endif
 464
 465#ifdef CONFIG_MMC_QCOM_DML
 466void qcom_variant_init(struct mmci_host *host);
 467#else
 468static inline void qcom_variant_init(struct mmci_host *host) {}
 469#endif
 470
 471#ifdef CONFIG_MMC_STM32_SDMMC
 472void sdmmc_variant_init(struct mmci_host *host);
 473#else
 474static inline void sdmmc_variant_init(struct mmci_host *host) {}
 475#endif
 476