LXR linux/drivers/mtd/nand/raw/cs553x

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * (C) 2005, 2006 Red Hat Inc.
   4 *
   5 * Author: David Woodhouse <dwmw2@infradead.org>
   6 *         Tom Sylla <tom.sylla@amd.com>
   7 *
   8 *  Overview:
   9 *   This is a device driver for the NAND flash controller found on
  10 *   the AMD CS5535/CS5536 companion chipsets for the Geode processor.
  11 *   mtd-id for command line partitioning is cs553x_nand_cs[0-3]
  12 *   where 0-3 reflects the chip select for NAND.
  13 */
  14
  15#include <linux/kernel.h>
  16#include <linux/slab.h>
  17#include <linux/init.h>
  18#include <linux/module.h>
  19#include <linux/delay.h>
  20#include <linux/mtd/mtd.h>
  21#include <linux/mtd/rawnand.h>
  22#include <linux/mtd/partitions.h>
  23#include <linux/iopoll.h>
  24
  25#include <asm/msr.h>
  26
  27#define NR_CS553X_CONTROLLERS   4
  28
  29#define MSR_DIVIL_GLD_CAP       0x51400000      /* DIVIL capabilitiies */
  30#define CAP_CS5535              0x2df000ULL
  31#define CAP_CS5536              0x5df500ULL
  32
  33/* NAND Timing MSRs */
  34#define MSR_NANDF_DATA          0x5140001b      /* NAND Flash Data Timing MSR */
  35#define MSR_NANDF_CTL           0x5140001c      /* NAND Flash Control Timing */
  36#define MSR_NANDF_RSVD          0x5140001d      /* Reserved */
  37
  38/* NAND BAR MSRs */
  39#define MSR_DIVIL_LBAR_FLSH0    0x51400010      /* Flash Chip Select 0 */
  40#define MSR_DIVIL_LBAR_FLSH1    0x51400011      /* Flash Chip Select 1 */
  41#define MSR_DIVIL_LBAR_FLSH2    0x51400012      /* Flash Chip Select 2 */
  42#define MSR_DIVIL_LBAR_FLSH3    0x51400013      /* Flash Chip Select 3 */
  43        /* Each made up of... */
  44#define FLSH_LBAR_EN            (1ULL<<32)
  45#define FLSH_NOR_NAND           (1ULL<<33)      /* 1 for NAND */
  46#define FLSH_MEM_IO             (1ULL<<34)      /* 1 for MMIO */
  47        /* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */
  48        /* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */
  49
  50/* Pin function selection MSR (IDE vs. flash on the IDE pins) */
  51#define MSR_DIVIL_BALL_OPTS     0x51400015
  52#define PIN_OPT_IDE             (1<<0)  /* 0 for flash, 1 for IDE */
  53
  54/* Registers within the NAND flash controller BAR -- memory mapped */
  55#define MM_NAND_DATA            0x00    /* 0 to 0x7ff, in fact */
  56#define MM_NAND_CTL             0x800   /* Any even address 0x800-0x80e */
  57#define MM_NAND_IO              0x801   /* Any odd address 0x801-0x80f */
  58#define MM_NAND_STS             0x810
  59#define MM_NAND_ECC_LSB         0x811
  60#define MM_NAND_ECC_MSB         0x812
  61#define MM_NAND_ECC_COL         0x813
  62#define MM_NAND_LAC             0x814
  63#define MM_NAND_ECC_CTL         0x815
  64
  65/* Registers within the NAND flash controller BAR -- I/O mapped */
  66#define IO_NAND_DATA            0x00    /* 0 to 3, in fact */
  67#define IO_NAND_CTL             0x04
  68#define IO_NAND_IO              0x05
  69#define IO_NAND_STS             0x06
  70#define IO_NAND_ECC_CTL         0x08
  71#define IO_NAND_ECC_LSB         0x09
  72#define IO_NAND_ECC_MSB         0x0a
  73#define IO_NAND_ECC_COL         0x0b
  74#define IO_NAND_LAC             0x0c
  75
  76#define CS_NAND_CTL_DIST_EN     (1<<4)  /* Enable NAND Distract interrupt */
  77#define CS_NAND_CTL_RDY_INT_MASK        (1<<3)  /* Enable RDY/BUSY# interrupt */
  78#define CS_NAND_CTL_ALE         (1<<2)
  79#define CS_NAND_CTL_CLE         (1<<1)
  80#define CS_NAND_CTL_CE          (1<<0)  /* Keep low; 1 to reset */
  81
  82#define CS_NAND_STS_FLASH_RDY   (1<<3)
  83#define CS_NAND_CTLR_BUSY       (1<<2)
  84#define CS_NAND_CMD_COMP        (1<<1)
  85#define CS_NAND_DIST_ST         (1<<0)
  86
  87#define CS_NAND_ECC_PARITY      (1<<2)
  88#define CS_NAND_ECC_CLRECC      (1<<1)
  89#define CS_NAND_ECC_ENECC       (1<<0)
  90
  91struct cs553x_nand_controller {
  92        struct nand_controller base;
  93        struct nand_chip chip;
  94        void __iomem *mmio;
  95};
  96
  97static struct cs553x_nand_controller *
  98to_cs553x(struct nand_controller *controller)
  99{
 100        return container_of(controller, struct cs553x_nand_controller, base);
 101}
 102
 103static int cs553x_write_ctrl_byte(struct cs553x_nand_controller *cs553x,
 104                                  u32 ctl, u8 data)
 105{
 106        u8 status;
 107        int ret;
 108
 109        writeb(ctl, cs553x->mmio + MM_NAND_CTL);
 110        writeb(data, cs553x->mmio + MM_NAND_IO);
 111        ret = readb_poll_timeout_atomic(cs553x->mmio + MM_NAND_STS, status,
 112                                        !(status & CS_NAND_CTLR_BUSY), 1,
 113                                        100000);
 114        if (ret)
 115                return ret;
 116
 117        return 0;
 118}
 119
 120static void cs553x_data_in(struct cs553x_nand_controller *cs553x, void *buf,
 121                           unsigned int len)
 122{
 123        writeb(0, cs553x->mmio + MM_NAND_CTL);
 124        while (unlikely(len > 0x800)) {
 125                memcpy_fromio(buf, cs553x->mmio, 0x800);
 126                buf += 0x800;
 127                len -= 0x800;
 128        }
 129        memcpy_fromio(buf, cs553x->mmio, len);
 130}
 131
 132static void cs553x_data_out(struct cs553x_nand_controller *cs553x,
 133                            const void *buf, unsigned int len)
 134{
 135        writeb(0, cs553x->mmio + MM_NAND_CTL);
 136        while (unlikely(len > 0x800)) {
 137                memcpy_toio(cs553x->mmio, buf, 0x800);
 138                buf += 0x800;
 139                len -= 0x800;
 140        }
 141        memcpy_toio(cs553x->mmio, buf, len);
 142}
 143
 144static int cs553x_wait_ready(struct cs553x_nand_controller *cs553x,
 145                             unsigned int timeout_ms)
 146{
 147        u8 mask = CS_NAND_CTLR_BUSY | CS_NAND_STS_FLASH_RDY;
 148        u8 status;
 149
 150        return readb_poll_timeout(cs553x->mmio + MM_NAND_STS, status,
 151                                  (status & mask) == CS_NAND_STS_FLASH_RDY, 100,
 152                                  timeout_ms * 1000);
 153}
 154
 155static int cs553x_exec_instr(struct cs553x_nand_controller *cs553x,
 156                             const struct nand_op_instr *instr)
 157{
 158        unsigned int i;
 159        int ret = 0;
 160
 161        switch (instr->type) {
 162        case NAND_OP_CMD_INSTR:
 163                ret = cs553x_write_ctrl_byte(cs553x, CS_NAND_CTL_CLE,
 164                                             instr->ctx.cmd.opcode);
 165                break;
 166
 167        case NAND_OP_ADDR_INSTR:
 168                for (i = 0; i < instr->ctx.addr.naddrs; i++) {
 169                        ret = cs553x_write_ctrl_byte(cs553x, CS_NAND_CTL_ALE,
 170                                                     instr->ctx.addr.addrs[i]);
 171                        if (ret)
 172                                break;
 173                }
 174                break;
 175
 176        case NAND_OP_DATA_IN_INSTR:
 177                cs553x_data_in(cs553x, instr->ctx.data.buf.in,
 178                               instr->ctx.data.len);
 179                break;
 180
 181        case NAND_OP_DATA_OUT_INSTR:
 182                cs553x_data_out(cs553x, instr->ctx.data.buf.out,
 183                                instr->ctx.data.len);
 184                break;
 185
 186        case NAND_OP_WAITRDY_INSTR:
 187                ret = cs553x_wait_ready(cs553x, instr->ctx.waitrdy.timeout_ms);
 188                break;
 189        }
 190
 191        if (instr->delay_ns)
 192                ndelay(instr->delay_ns);
 193
 194        return ret;
 195}
 196
 197static int cs553x_exec_op(struct nand_chip *this,
 198                          const struct nand_operation *op,
 199                          bool check_only)
 200{
 201        struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);
 202        unsigned int i;
 203        int ret;
 204
 205        if (check_only)
 206                return true;
 207
 208        /* De-assert the CE pin */
 209        writeb(0, cs553x->mmio + MM_NAND_CTL);
 210        for (i = 0; i < op->ninstrs; i++) {
 211                ret = cs553x_exec_instr(cs553x, &op->instrs[i]);
 212                if (ret)
 213                        break;
 214        }
 215
 216        /* Re-assert the CE pin. */
 217        writeb(CS_NAND_CTL_CE, cs553x->mmio + MM_NAND_CTL);
 218
 219        return ret;
 220}
 221
 222static void cs_enable_hwecc(struct nand_chip *this, int mode)
 223{
 224        struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);
 225
 226        writeb(0x07, cs553x->mmio + MM_NAND_ECC_CTL);
 227}
 228
 229static int cs_calculate_ecc(struct nand_chip *this, const u_char *dat,
 230                            u_char *ecc_code)
 231{
 232        struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);
 233        uint32_t ecc;
 234
 235        ecc = readl(cs553x->mmio + MM_NAND_STS);
 236
 237        ecc_code[1] = ecc >> 8;
 238        ecc_code[0] = ecc >> 16;
 239        ecc_code[2] = ecc >> 24;
 240        return 0;
 241}
 242
 243static struct cs553x_nand_controller *controllers[4];
 244
 245static int cs553x_attach_chip(struct nand_chip *chip)
 246{
 247        if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
 248                return 0;
 249
 250        chip->ecc.size = 256;
 251        chip->ecc.bytes = 3;
 252        chip->ecc.hwctl  = cs_enable_hwecc;
 253        chip->ecc.calculate = cs_calculate_ecc;
 254        chip->ecc.correct  = rawnand_sw_hamming_correct;
 255        chip->ecc.strength = 1;
 256
 257        return 0;
 258}
 259
 260static const struct nand_controller_ops cs553x_nand_controller_ops = {
 261        .exec_op = cs553x_exec_op,
 262        .attach_chip = cs553x_attach_chip,
 263};
 264
 265static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
 266{
 267        struct cs553x_nand_controller *controller;
 268        int err = 0;
 269        struct nand_chip *this;
 270        struct mtd_info *new_mtd;
 271
 272        pr_notice("Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n",
 273                  cs, mmio ? "MM" : "P", adr);
 274
 275        if (!mmio) {
 276                pr_notice("PIO mode not yet implemented for CS553X NAND controller\n");
 277                return -ENXIO;
 278        }
 279
 280        /* Allocate memory for MTD device structure and private data */
 281        controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 282        if (!controller) {
 283                err = -ENOMEM;
 284                goto out;
 285        }
 286
 287        this = &controller->chip;
 288        nand_controller_init(&controller->base);
 289        controller->base.ops = &cs553x_nand_controller_ops;
 290        this->controller = &controller->base;
 291        new_mtd = nand_to_mtd(this);
 292
 293        /* Link the private data with the MTD structure */
 294        new_mtd->owner = THIS_MODULE;
 295
 296        /* map physical address */
 297        controller->mmio = ioremap(adr, 4096);
 298        if (!controller->mmio) {
 299                pr_warn("ioremap cs553x NAND @0x%08lx failed\n", adr);
 300                err = -EIO;
 301                goto out_mtd;
 302        }
 303
 304        /* Enable the following for a flash based bad block table */
 305        this->bbt_options = NAND_BBT_USE_FLASH;
 306
 307        new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs);
 308        if (!new_mtd->name) {
 309                err = -ENOMEM;
 310                goto out_ior;
 311        }
 312
 313        /* Scan to find existence of the device */
 314        err = nand_scan(this, 1);
 315        if (err)
 316                goto out_free;
 317
 318        controllers[cs] = controller;
 319        goto out;
 320
 321out_free:
 322        kfree(new_mtd->name);
 323out_ior:
 324        iounmap(controller->mmio);
 325out_mtd:
 326        kfree(controller);
 327out:
 328        return err;
 329}
 330
 331static int is_geode(void)
 332{
 333        /* These are the CPUs which will have a CS553[56] companion chip */
 334        if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
 335            boot_cpu_data.x86 == 5 &&
 336            boot_cpu_data.x86_model == 10)
 337                return 1; /* Geode LX */
 338
 339        if ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC ||
 340             boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX) &&
 341            boot_cpu_data.x86 == 5 &&
 342            boot_cpu_data.x86_model == 5)
 343                return 1; /* Geode GX (née GX2) */
 344
 345        return 0;
 346}
 347
 348static int __init cs553x_init(void)
 349{
 350        int err = -ENXIO;
 351        int i;
 352        uint64_t val;
 353
 354        /* If the CPU isn't a Geode GX or LX, abort */
 355        if (!is_geode())
 356                return -ENXIO;
 357
 358        /* If it doesn't have the CS553[56], abort */
 359        rdmsrl(MSR_DIVIL_GLD_CAP, val);
 360        val &= ~0xFFULL;
 361        if (val != CAP_CS5535 && val != CAP_CS5536)
 362                return -ENXIO;
 363
 364        /* If it doesn't have the NAND controller enabled, abort */
 365        rdmsrl(MSR_DIVIL_BALL_OPTS, val);
 366        if (val & PIN_OPT_IDE) {
 367                pr_info("CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
 368                return -ENXIO;
 369        }
 370
 371        for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
 372                rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val);
 373
 374                if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
 375                        err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
 376        }
 377
 378        /* Register all devices together here. This means we can easily hack it to
 379           do mtdconcat etc. if we want to. */
 380        for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
 381                if (controllers[i]) {
 382                        /* If any devices registered, return success. Else the last error. */
 383                        mtd_device_register(nand_to_mtd(&controllers[i]->chip),
 384                                            NULL, 0);
 385                        err = 0;
 386                }
 387        }
 388
 389        return err;
 390}
 391
 392module_init(cs553x_init);
 393
 394static void __exit cs553x_cleanup(void)
 395{
 396        int i;
 397
 398        for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
 399                struct cs553x_nand_controller *controller = controllers[i];
 400                struct nand_chip *this = &controller->chip;
 401                struct mtd_info *mtd = nand_to_mtd(this);
 402                int ret;
 403
 404                if (!mtd)
 405                        continue;
 406
 407                /* Release resources, unregister device */
 408                ret = mtd_device_unregister(mtd);
 409                WARN_ON(ret);
 410                nand_cleanup(this);
 411                kfree(mtd->name);
 412                controllers[i] = NULL;
 413
 414                /* unmap physical address */
 415                iounmap(controller->mmio);
 416
 417                /* Free the MTD device structure */
 418                kfree(controller);
 419        }
 420}
 421
 422module_exit(cs553x_cleanup);
 423
 424MODULE_LICENSE("GPL");
 425MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
 426MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");
 427