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23
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#define DRV_NAME "pcnet32"
27#define DRV_RELDATE "21.Apr.2008"
28#define PFX DRV_NAME ": "
29
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/sched.h>
33#include <linux/string.h>
34#include <linux/errno.h>
35#include <linux/ioport.h>
36#include <linux/slab.h>
37#include <linux/interrupt.h>
38#include <linux/pci.h>
39#include <linux/delay.h>
40#include <linux/init.h>
41#include <linux/ethtool.h>
42#include <linux/mii.h>
43#include <linux/crc32.h>
44#include <linux/netdevice.h>
45#include <linux/etherdevice.h>
46#include <linux/if_ether.h>
47#include <linux/skbuff.h>
48#include <linux/spinlock.h>
49#include <linux/moduleparam.h>
50#include <linux/bitops.h>
51#include <linux/io.h>
52#include <linux/uaccess.h>
53
54#include <asm/dma.h>
55#include <asm/irq.h>
56
57
58
59
60static const struct pci_device_id pcnet32_pci_tbl[] = {
61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
63
64
65
66
67
68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
70
71 { }
72};
73
74MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
75
76static int cards_found;
77
78
79
80
81static unsigned int pcnet32_portlist[] =
82 { 0x300, 0x320, 0x340, 0x360, 0 };
83
84static int pcnet32_debug;
85static int tx_start = 1;
86static int pcnet32vlb;
87
88static struct net_device *pcnet32_dev;
89
90static int max_interrupt_work = 2;
91static int rx_copybreak = 200;
92
93#define PCNET32_PORT_AUI 0x00
94#define PCNET32_PORT_10BT 0x01
95#define PCNET32_PORT_GPSI 0x02
96#define PCNET32_PORT_MII 0x03
97
98#define PCNET32_PORT_PORTSEL 0x03
99#define PCNET32_PORT_ASEL 0x04
100#define PCNET32_PORT_100 0x40
101#define PCNET32_PORT_FD 0x80
102
103#define PCNET32_DMA_MASK 0xffffffff
104
105#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
107
108
109
110
111
112static const unsigned char options_mapping[] = {
113 PCNET32_PORT_ASEL,
114 PCNET32_PORT_AUI,
115 PCNET32_PORT_AUI,
116 PCNET32_PORT_ASEL,
117 PCNET32_PORT_10BT | PCNET32_PORT_FD,
118 PCNET32_PORT_ASEL,
119 PCNET32_PORT_ASEL,
120 PCNET32_PORT_ASEL,
121 PCNET32_PORT_ASEL,
122 PCNET32_PORT_MII,
123 PCNET32_PORT_MII | PCNET32_PORT_FD,
124 PCNET32_PORT_MII,
125 PCNET32_PORT_10BT,
126 PCNET32_PORT_MII | PCNET32_PORT_100,
127
128 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
129 PCNET32_PORT_ASEL
130};
131
132static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
133 "Loopback test (offline)"
134};
135
136#define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test)
137
138#define PCNET32_NUM_REGS 136
139
140#define MAX_UNITS 8
141static int options[MAX_UNITS];
142static int full_duplex[MAX_UNITS];
143static int homepna[MAX_UNITS];
144
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158
159
160#ifndef PCNET32_LOG_TX_BUFFERS
161#define PCNET32_LOG_TX_BUFFERS 4
162#define PCNET32_LOG_RX_BUFFERS 5
163#define PCNET32_LOG_MAX_TX_BUFFERS 9
164#define PCNET32_LOG_MAX_RX_BUFFERS 9
165#endif
166
167#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
168#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
169
170#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
171#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
172
173#define PKT_BUF_SKB 1544
174
175#define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)
176
177#define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)
178
179
180#define PCNET32_WIO_RDP 0x10
181#define PCNET32_WIO_RAP 0x12
182#define PCNET32_WIO_RESET 0x14
183#define PCNET32_WIO_BDP 0x16
184
185#define PCNET32_DWIO_RDP 0x10
186#define PCNET32_DWIO_RAP 0x14
187#define PCNET32_DWIO_RESET 0x18
188#define PCNET32_DWIO_BDP 0x1C
189
190#define PCNET32_TOTAL_SIZE 0x20
191
192#define CSR0 0
193#define CSR0_INIT 0x1
194#define CSR0_START 0x2
195#define CSR0_STOP 0x4
196#define CSR0_TXPOLL 0x8
197#define CSR0_INTEN 0x40
198#define CSR0_IDON 0x0100
199#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
200#define PCNET32_INIT_LOW 1
201#define PCNET32_INIT_HIGH 2
202#define CSR3 3
203#define CSR4 4
204#define CSR5 5
205#define CSR5_SUSPEND 0x0001
206#define CSR15 15
207#define PCNET32_MC_FILTER 8
208
209#define PCNET32_79C970A 0x2621
210
211
212struct pcnet32_rx_head {
213 __le32 base;
214 __le16 buf_length;
215 __le16 status;
216 __le32 msg_length;
217 __le32 reserved;
218};
219
220struct pcnet32_tx_head {
221 __le32 base;
222 __le16 length;
223 __le16 status;
224 __le32 misc;
225 __le32 reserved;
226};
227
228
229struct pcnet32_init_block {
230 __le16 mode;
231 __le16 tlen_rlen;
232 u8 phys_addr[6];
233 __le16 reserved;
234 __le32 filter[2];
235
236 __le32 rx_ring;
237 __le32 tx_ring;
238};
239
240
241struct pcnet32_access {
242 u16 (*read_csr) (unsigned long, int);
243 void (*write_csr) (unsigned long, int, u16);
244 u16 (*read_bcr) (unsigned long, int);
245 void (*write_bcr) (unsigned long, int, u16);
246 u16 (*read_rap) (unsigned long);
247 void (*write_rap) (unsigned long, u16);
248 void (*reset) (unsigned long);
249};
250
251
252
253
254
255struct pcnet32_private {
256 struct pcnet32_init_block *init_block;
257
258 struct pcnet32_rx_head *rx_ring;
259 struct pcnet32_tx_head *tx_ring;
260 dma_addr_t init_dma_addr;
261
262 struct pci_dev *pci_dev;
263 const char *name;
264
265 struct sk_buff **tx_skbuff;
266 struct sk_buff **rx_skbuff;
267 dma_addr_t *tx_dma_addr;
268 dma_addr_t *rx_dma_addr;
269 const struct pcnet32_access *a;
270 spinlock_t lock;
271 unsigned int cur_rx, cur_tx;
272 unsigned int rx_ring_size;
273 unsigned int tx_ring_size;
274 unsigned int rx_mod_mask;
275 unsigned int tx_mod_mask;
276 unsigned short rx_len_bits;
277 unsigned short tx_len_bits;
278 dma_addr_t rx_ring_dma_addr;
279 dma_addr_t tx_ring_dma_addr;
280 unsigned int dirty_rx,
281 dirty_tx;
282
283 struct net_device *dev;
284 struct napi_struct napi;
285 char tx_full;
286 char phycount;
287 int options;
288 unsigned int shared_irq:1,
289 dxsuflo:1,
290 mii:1,
291 autoneg:1,
292 port_tp:1,
293 fdx:1;
294 struct net_device *next;
295 struct mii_if_info mii_if;
296 struct timer_list watchdog_timer;
297 u32 msg_enable;
298
299
300 u32 phymask;
301 unsigned short chip_version;
302
303
304 u16 save_regs[4];
305};
306
307static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
308static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
309static int pcnet32_open(struct net_device *);
310static int pcnet32_init_ring(struct net_device *);
311static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
312 struct net_device *);
313static void pcnet32_tx_timeout(struct net_device *dev, unsigned int txqueue);
314static irqreturn_t pcnet32_interrupt(int, void *);
315static int pcnet32_close(struct net_device *);
316static struct net_device_stats *pcnet32_get_stats(struct net_device *);
317static void pcnet32_load_multicast(struct net_device *dev);
318static void pcnet32_set_multicast_list(struct net_device *);
319static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
320static void pcnet32_watchdog(struct timer_list *);
321static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
322static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
323 int val);
324static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
325static void pcnet32_ethtool_test(struct net_device *dev,
326 struct ethtool_test *eth_test, u64 * data);
327static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
328static int pcnet32_get_regs_len(struct net_device *dev);
329static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
330 void *ptr);
331static void pcnet32_purge_tx_ring(struct net_device *dev);
332static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
333static void pcnet32_free_ring(struct net_device *dev);
334static void pcnet32_check_media(struct net_device *dev, int verbose);
335
336static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
337{
338 outw(index, addr + PCNET32_WIO_RAP);
339 return inw(addr + PCNET32_WIO_RDP);
340}
341
342static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
343{
344 outw(index, addr + PCNET32_WIO_RAP);
345 outw(val, addr + PCNET32_WIO_RDP);
346}
347
348static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
349{
350 outw(index, addr + PCNET32_WIO_RAP);
351 return inw(addr + PCNET32_WIO_BDP);
352}
353
354static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
355{
356 outw(index, addr + PCNET32_WIO_RAP);
357 outw(val, addr + PCNET32_WIO_BDP);
358}
359
360static u16 pcnet32_wio_read_rap(unsigned long addr)
361{
362 return inw(addr + PCNET32_WIO_RAP);
363}
364
365static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
366{
367 outw(val, addr + PCNET32_WIO_RAP);
368}
369
370static void pcnet32_wio_reset(unsigned long addr)
371{
372 inw(addr + PCNET32_WIO_RESET);
373}
374
375static int pcnet32_wio_check(unsigned long addr)
376{
377 outw(88, addr + PCNET32_WIO_RAP);
378 return inw(addr + PCNET32_WIO_RAP) == 88;
379}
380
381static const struct pcnet32_access pcnet32_wio = {
382 .read_csr = pcnet32_wio_read_csr,
383 .write_csr = pcnet32_wio_write_csr,
384 .read_bcr = pcnet32_wio_read_bcr,
385 .write_bcr = pcnet32_wio_write_bcr,
386 .read_rap = pcnet32_wio_read_rap,
387 .write_rap = pcnet32_wio_write_rap,
388 .reset = pcnet32_wio_reset
389};
390
391static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
392{
393 outl(index, addr + PCNET32_DWIO_RAP);
394 return inl(addr + PCNET32_DWIO_RDP) & 0xffff;
395}
396
397static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
398{
399 outl(index, addr + PCNET32_DWIO_RAP);
400 outl(val, addr + PCNET32_DWIO_RDP);
401}
402
403static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
404{
405 outl(index, addr + PCNET32_DWIO_RAP);
406 return inl(addr + PCNET32_DWIO_BDP) & 0xffff;
407}
408
409static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
410{
411 outl(index, addr + PCNET32_DWIO_RAP);
412 outl(val, addr + PCNET32_DWIO_BDP);
413}
414
415static u16 pcnet32_dwio_read_rap(unsigned long addr)
416{
417 return inl(addr + PCNET32_DWIO_RAP) & 0xffff;
418}
419
420static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
421{
422 outl(val, addr + PCNET32_DWIO_RAP);
423}
424
425static void pcnet32_dwio_reset(unsigned long addr)
426{
427 inl(addr + PCNET32_DWIO_RESET);
428}
429
430static int pcnet32_dwio_check(unsigned long addr)
431{
432 outl(88, addr + PCNET32_DWIO_RAP);
433 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88;
434}
435
436static const struct pcnet32_access pcnet32_dwio = {
437 .read_csr = pcnet32_dwio_read_csr,
438 .write_csr = pcnet32_dwio_write_csr,
439 .read_bcr = pcnet32_dwio_read_bcr,
440 .write_bcr = pcnet32_dwio_write_bcr,
441 .read_rap = pcnet32_dwio_read_rap,
442 .write_rap = pcnet32_dwio_write_rap,
443 .reset = pcnet32_dwio_reset
444};
445
446static void pcnet32_netif_stop(struct net_device *dev)
447{
448 struct pcnet32_private *lp = netdev_priv(dev);
449
450 netif_trans_update(dev);
451 napi_disable(&lp->napi);
452 netif_tx_disable(dev);
453}
454
455static void pcnet32_netif_start(struct net_device *dev)
456{
457 struct pcnet32_private *lp = netdev_priv(dev);
458 ulong ioaddr = dev->base_addr;
459 u16 val;
460
461 netif_wake_queue(dev);
462 val = lp->a->read_csr(ioaddr, CSR3);
463 val &= 0x00ff;
464 lp->a->write_csr(ioaddr, CSR3, val);
465 napi_enable(&lp->napi);
466}
467
468
469
470
471
472
473
474
475static void pcnet32_realloc_tx_ring(struct net_device *dev,
476 struct pcnet32_private *lp,
477 unsigned int size)
478{
479 dma_addr_t new_ring_dma_addr;
480 dma_addr_t *new_dma_addr_list;
481 struct pcnet32_tx_head *new_tx_ring;
482 struct sk_buff **new_skb_list;
483 unsigned int entries = BIT(size);
484
485 pcnet32_purge_tx_ring(dev);
486
487 new_tx_ring =
488 dma_alloc_coherent(&lp->pci_dev->dev,
489 sizeof(struct pcnet32_tx_head) * entries,
490 &new_ring_dma_addr, GFP_ATOMIC);
491 if (new_tx_ring == NULL)
492 return;
493
494 new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);
495 if (!new_dma_addr_list)
496 goto free_new_tx_ring;
497
498 new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);
499 if (!new_skb_list)
500 goto free_new_lists;
501
502 kfree(lp->tx_skbuff);
503 kfree(lp->tx_dma_addr);
504 dma_free_coherent(&lp->pci_dev->dev,
505 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
506 lp->tx_ring, lp->tx_ring_dma_addr);
507
508 lp->tx_ring_size = entries;
509 lp->tx_mod_mask = lp->tx_ring_size - 1;
510 lp->tx_len_bits = (size << 12);
511 lp->tx_ring = new_tx_ring;
512 lp->tx_ring_dma_addr = new_ring_dma_addr;
513 lp->tx_dma_addr = new_dma_addr_list;
514 lp->tx_skbuff = new_skb_list;
515 return;
516
517free_new_lists:
518 kfree(new_dma_addr_list);
519free_new_tx_ring:
520 dma_free_coherent(&lp->pci_dev->dev,
521 sizeof(struct pcnet32_tx_head) * entries,
522 new_tx_ring, new_ring_dma_addr);
523}
524
525
526
527
528
529
530
531
532
533
534
535static void pcnet32_realloc_rx_ring(struct net_device *dev,
536 struct pcnet32_private *lp,
537 unsigned int size)
538{
539 dma_addr_t new_ring_dma_addr;
540 dma_addr_t *new_dma_addr_list;
541 struct pcnet32_rx_head *new_rx_ring;
542 struct sk_buff **new_skb_list;
543 int new, overlap;
544 unsigned int entries = BIT(size);
545
546 new_rx_ring =
547 dma_alloc_coherent(&lp->pci_dev->dev,
548 sizeof(struct pcnet32_rx_head) * entries,
549 &new_ring_dma_addr, GFP_ATOMIC);
550 if (new_rx_ring == NULL)
551 return;
552
553 new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);
554 if (!new_dma_addr_list)
555 goto free_new_rx_ring;
556
557 new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);
558 if (!new_skb_list)
559 goto free_new_lists;
560
561
562 overlap = min(entries, lp->rx_ring_size);
563 for (new = 0; new < overlap; new++) {
564 new_rx_ring[new] = lp->rx_ring[new];
565 new_dma_addr_list[new] = lp->rx_dma_addr[new];
566 new_skb_list[new] = lp->rx_skbuff[new];
567 }
568
569 for (; new < entries; new++) {
570 struct sk_buff *rx_skbuff;
571 new_skb_list[new] = netdev_alloc_skb(dev, PKT_BUF_SKB);
572 rx_skbuff = new_skb_list[new];
573 if (!rx_skbuff) {
574
575 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
576 __func__);
577 goto free_all_new;
578 }
579 skb_reserve(rx_skbuff, NET_IP_ALIGN);
580
581 new_dma_addr_list[new] =
582 dma_map_single(&lp->pci_dev->dev, rx_skbuff->data,
583 PKT_BUF_SIZE, DMA_FROM_DEVICE);
584 if (dma_mapping_error(&lp->pci_dev->dev, new_dma_addr_list[new])) {
585 netif_err(lp, drv, dev, "%s dma mapping failed\n",
586 __func__);
587 dev_kfree_skb(new_skb_list[new]);
588 goto free_all_new;
589 }
590 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
591 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
592 new_rx_ring[new].status = cpu_to_le16(0x8000);
593 }
594
595 for (; new < lp->rx_ring_size; new++) {
596 if (lp->rx_skbuff[new]) {
597 if (!dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[new]))
598 dma_unmap_single(&lp->pci_dev->dev,
599 lp->rx_dma_addr[new],
600 PKT_BUF_SIZE,
601 DMA_FROM_DEVICE);
602 dev_kfree_skb(lp->rx_skbuff[new]);
603 }
604 }
605
606 kfree(lp->rx_skbuff);
607 kfree(lp->rx_dma_addr);
608 dma_free_coherent(&lp->pci_dev->dev,
609 sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
610 lp->rx_ring, lp->rx_ring_dma_addr);
611
612 lp->rx_ring_size = entries;
613 lp->rx_mod_mask = lp->rx_ring_size - 1;
614 lp->rx_len_bits = (size << 4);
615 lp->rx_ring = new_rx_ring;
616 lp->rx_ring_dma_addr = new_ring_dma_addr;
617 lp->rx_dma_addr = new_dma_addr_list;
618 lp->rx_skbuff = new_skb_list;
619 return;
620
621free_all_new:
622 while (--new >= lp->rx_ring_size) {
623 if (new_skb_list[new]) {
624 if (!dma_mapping_error(&lp->pci_dev->dev, new_dma_addr_list[new]))
625 dma_unmap_single(&lp->pci_dev->dev,
626 new_dma_addr_list[new],
627 PKT_BUF_SIZE,
628 DMA_FROM_DEVICE);
629 dev_kfree_skb(new_skb_list[new]);
630 }
631 }
632 kfree(new_skb_list);
633free_new_lists:
634 kfree(new_dma_addr_list);
635free_new_rx_ring:
636 dma_free_coherent(&lp->pci_dev->dev,
637 sizeof(struct pcnet32_rx_head) * entries,
638 new_rx_ring, new_ring_dma_addr);
639}
640
641static void pcnet32_purge_rx_ring(struct net_device *dev)
642{
643 struct pcnet32_private *lp = netdev_priv(dev);
644 int i;
645
646
647 for (i = 0; i < lp->rx_ring_size; i++) {
648 lp->rx_ring[i].status = 0;
649 wmb();
650 if (lp->rx_skbuff[i]) {
651 if (!dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[i]))
652 dma_unmap_single(&lp->pci_dev->dev,
653 lp->rx_dma_addr[i],
654 PKT_BUF_SIZE,
655 DMA_FROM_DEVICE);
656 dev_kfree_skb_any(lp->rx_skbuff[i]);
657 }
658 lp->rx_skbuff[i] = NULL;
659 lp->rx_dma_addr[i] = 0;
660 }
661}
662
663#ifdef CONFIG_NET_POLL_CONTROLLER
664static void pcnet32_poll_controller(struct net_device *dev)
665{
666 disable_irq(dev->irq);
667 pcnet32_interrupt(0, dev);
668 enable_irq(dev->irq);
669}
670#endif
671
672
673
674
675static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
676 int can_sleep)
677{
678 int csr5;
679 struct pcnet32_private *lp = netdev_priv(dev);
680 const struct pcnet32_access *a = lp->a;
681 ulong ioaddr = dev->base_addr;
682 int ticks;
683
684
685 if (lp->chip_version < PCNET32_79C970A)
686 return 0;
687
688
689 csr5 = a->read_csr(ioaddr, CSR5);
690 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
691
692
693 ticks = 0;
694 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
695 spin_unlock_irqrestore(&lp->lock, *flags);
696 if (can_sleep)
697 msleep(1);
698 else
699 mdelay(1);
700 spin_lock_irqsave(&lp->lock, *flags);
701 ticks++;
702 if (ticks > 200) {
703 netif_printk(lp, hw, KERN_DEBUG, dev,
704 "Error getting into suspend!\n");
705 return 0;
706 }
707 }
708 return 1;
709}
710
711static void pcnet32_clr_suspend(struct pcnet32_private *lp, ulong ioaddr)
712{
713 int csr5 = lp->a->read_csr(ioaddr, CSR5);
714
715 lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND);
716}
717
718static int pcnet32_get_link_ksettings(struct net_device *dev,
719 struct ethtool_link_ksettings *cmd)
720{
721 struct pcnet32_private *lp = netdev_priv(dev);
722 unsigned long flags;
723
724 spin_lock_irqsave(&lp->lock, flags);
725 if (lp->mii) {
726 mii_ethtool_get_link_ksettings(&lp->mii_if, cmd);
727 } else if (lp->chip_version == PCNET32_79C970A) {
728 if (lp->autoneg) {
729 cmd->base.autoneg = AUTONEG_ENABLE;
730 if (lp->a->read_bcr(dev->base_addr, 4) == 0xc0)
731 cmd->base.port = PORT_AUI;
732 else
733 cmd->base.port = PORT_TP;
734 } else {
735 cmd->base.autoneg = AUTONEG_DISABLE;
736 cmd->base.port = lp->port_tp ? PORT_TP : PORT_AUI;
737 }
738 cmd->base.duplex = lp->fdx ? DUPLEX_FULL : DUPLEX_HALF;
739 cmd->base.speed = SPEED_10;
740 ethtool_convert_legacy_u32_to_link_mode(
741 cmd->link_modes.supported,
742 SUPPORTED_TP | SUPPORTED_AUI);
743 }
744 spin_unlock_irqrestore(&lp->lock, flags);
745 return 0;
746}
747
748static int pcnet32_set_link_ksettings(struct net_device *dev,
749 const struct ethtool_link_ksettings *cmd)
750{
751 struct pcnet32_private *lp = netdev_priv(dev);
752 ulong ioaddr = dev->base_addr;
753 unsigned long flags;
754 int r = -EOPNOTSUPP;
755 int suspended, bcr2, bcr9, csr15;
756
757 spin_lock_irqsave(&lp->lock, flags);
758 if (lp->mii) {
759 r = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd);
760 } else if (lp->chip_version == PCNET32_79C970A) {
761 suspended = pcnet32_suspend(dev, &flags, 0);
762 if (!suspended)
763 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
764
765 lp->autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
766 bcr2 = lp->a->read_bcr(ioaddr, 2);
767 if (cmd->base.autoneg == AUTONEG_ENABLE) {
768 lp->a->write_bcr(ioaddr, 2, bcr2 | 0x0002);
769 } else {
770 lp->a->write_bcr(ioaddr, 2, bcr2 & ~0x0002);
771
772 lp->port_tp = cmd->base.port == PORT_TP;
773 csr15 = lp->a->read_csr(ioaddr, CSR15) & ~0x0180;
774 if (cmd->base.port == PORT_TP)
775 csr15 |= 0x0080;
776 lp->a->write_csr(ioaddr, CSR15, csr15);
777 lp->init_block->mode = cpu_to_le16(csr15);
778
779 lp->fdx = cmd->base.duplex == DUPLEX_FULL;
780 bcr9 = lp->a->read_bcr(ioaddr, 9) & ~0x0003;
781 if (cmd->base.duplex == DUPLEX_FULL)
782 bcr9 |= 0x0003;
783 lp->a->write_bcr(ioaddr, 9, bcr9);
784 }
785 if (suspended)
786 pcnet32_clr_suspend(lp, ioaddr);
787 else if (netif_running(dev))
788 pcnet32_restart(dev, CSR0_NORMAL);
789 r = 0;
790 }
791 spin_unlock_irqrestore(&lp->lock, flags);
792 return r;
793}
794
795static void pcnet32_get_drvinfo(struct net_device *dev,
796 struct ethtool_drvinfo *info)
797{
798 struct pcnet32_private *lp = netdev_priv(dev);
799
800 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
801 if (lp->pci_dev)
802 strlcpy(info->bus_info, pci_name(lp->pci_dev),
803 sizeof(info->bus_info));
804 else
805 snprintf(info->bus_info, sizeof(info->bus_info),
806 "VLB 0x%lx", dev->base_addr);
807}
808
809static u32 pcnet32_get_link(struct net_device *dev)
810{
811 struct pcnet32_private *lp = netdev_priv(dev);
812 unsigned long flags;
813 int r;
814
815 spin_lock_irqsave(&lp->lock, flags);
816 if (lp->mii) {
817 r = mii_link_ok(&lp->mii_if);
818 } else if (lp->chip_version == PCNET32_79C970A) {
819 ulong ioaddr = dev->base_addr;
820
821 if (!lp->autoneg && lp->port_tp)
822 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
823 else
824 r = 1;
825 } else if (lp->chip_version > PCNET32_79C970A) {
826 ulong ioaddr = dev->base_addr;
827 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
828 } else {
829 r = 1;
830 }
831 spin_unlock_irqrestore(&lp->lock, flags);
832
833 return r;
834}
835
836static u32 pcnet32_get_msglevel(struct net_device *dev)
837{
838 struct pcnet32_private *lp = netdev_priv(dev);
839 return lp->msg_enable;
840}
841
842static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
843{
844 struct pcnet32_private *lp = netdev_priv(dev);
845 lp->msg_enable = value;
846}
847
848static int pcnet32_nway_reset(struct net_device *dev)
849{
850 struct pcnet32_private *lp = netdev_priv(dev);
851 unsigned long flags;
852 int r = -EOPNOTSUPP;
853
854 if (lp->mii) {
855 spin_lock_irqsave(&lp->lock, flags);
856 r = mii_nway_restart(&lp->mii_if);
857 spin_unlock_irqrestore(&lp->lock, flags);
858 }
859 return r;
860}
861
862static void pcnet32_get_ringparam(struct net_device *dev,
863 struct ethtool_ringparam *ering,
864 struct kernel_ethtool_ringparam *kernel_ering,
865 struct netlink_ext_ack *extack)
866{
867 struct pcnet32_private *lp = netdev_priv(dev);
868
869 ering->tx_max_pending = TX_MAX_RING_SIZE;
870 ering->tx_pending = lp->tx_ring_size;
871 ering->rx_max_pending = RX_MAX_RING_SIZE;
872 ering->rx_pending = lp->rx_ring_size;
873}
874
875static int pcnet32_set_ringparam(struct net_device *dev,
876 struct ethtool_ringparam *ering,
877 struct kernel_ethtool_ringparam *kernel_ering,
878 struct netlink_ext_ack *extack)
879{
880 struct pcnet32_private *lp = netdev_priv(dev);
881 unsigned long flags;
882 unsigned int size;
883 ulong ioaddr = dev->base_addr;
884 int i;
885
886 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
887 return -EINVAL;
888
889 if (netif_running(dev))
890 pcnet32_netif_stop(dev);
891
892 spin_lock_irqsave(&lp->lock, flags);
893 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
894
895 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
896
897
898
899
900 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
901 if (size <= (1 << i))
902 break;
903 }
904 if ((1 << i) != lp->tx_ring_size)
905 pcnet32_realloc_tx_ring(dev, lp, i);
906
907 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
908 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
909 if (size <= (1 << i))
910 break;
911 }
912 if ((1 << i) != lp->rx_ring_size)
913 pcnet32_realloc_rx_ring(dev, lp, i);
914
915 lp->napi.weight = lp->rx_ring_size / 2;
916
917 if (netif_running(dev)) {
918 pcnet32_netif_start(dev);
919 pcnet32_restart(dev, CSR0_NORMAL);
920 }
921
922 spin_unlock_irqrestore(&lp->lock, flags);
923
924 netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n",
925 lp->rx_ring_size, lp->tx_ring_size);
926
927 return 0;
928}
929
930static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
931 u8 *data)
932{
933 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
934}
935
936static int pcnet32_get_sset_count(struct net_device *dev, int sset)
937{
938 switch (sset) {
939 case ETH_SS_TEST:
940 return PCNET32_TEST_LEN;
941 default:
942 return -EOPNOTSUPP;
943 }
944}
945
946static void pcnet32_ethtool_test(struct net_device *dev,
947 struct ethtool_test *test, u64 * data)
948{
949 struct pcnet32_private *lp = netdev_priv(dev);
950 int rc;
951
952 if (test->flags == ETH_TEST_FL_OFFLINE) {
953 rc = pcnet32_loopback_test(dev, data);
954 if (rc) {
955 netif_printk(lp, hw, KERN_DEBUG, dev,
956 "Loopback test failed\n");
957 test->flags |= ETH_TEST_FL_FAILED;
958 } else
959 netif_printk(lp, hw, KERN_DEBUG, dev,
960 "Loopback test passed\n");
961 } else
962 netif_printk(lp, hw, KERN_DEBUG, dev,
963 "No tests to run (specify 'Offline' on ethtool)\n");
964}
965
966static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
967{
968 struct pcnet32_private *lp = netdev_priv(dev);
969 const struct pcnet32_access *a = lp->a;
970 ulong ioaddr = dev->base_addr;
971 struct sk_buff *skb;
972 int x, i;
973 int numbuffs = 4;
974 u16 status = 0x8300;
975 __le16 teststatus;
976 int rc;
977 int size;
978 unsigned char *packet;
979 static const int data_len = 60;
980 unsigned long flags;
981 unsigned long ticks;
982
983 rc = 1;
984
985 if (netif_running(dev))
986 pcnet32_netif_stop(dev);
987
988 spin_lock_irqsave(&lp->lock, flags);
989 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
990
991 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
992
993
994 lp->a->reset(ioaddr);
995 lp->a->write_csr(ioaddr, CSR4, 0x0915);
996
997
998 lp->a->write_bcr(ioaddr, 20, 2);
999
1000
1001 pcnet32_restart(dev, 0x0000);
1002
1003 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
1004
1005
1006 size = data_len + 15;
1007 for (x = 0; x < numbuffs; x++) {
1008 skb = netdev_alloc_skb(dev, size);
1009 if (!skb) {
1010 netif_printk(lp, hw, KERN_DEBUG, dev,
1011 "Cannot allocate skb at line: %d!\n",
1012 __LINE__);
1013 goto clean_up;
1014 }
1015 packet = skb->data;
1016 skb_put(skb, size);
1017 lp->tx_skbuff[x] = skb;
1018 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
1019 lp->tx_ring[x].misc = 0;
1020
1021
1022 for (i = 0; i < 6; i++)
1023 *packet++ = dev->dev_addr[i];
1024 for (i = 0; i < 6; i++)
1025 *packet++ = dev->dev_addr[i];
1026
1027 *packet++ = 0x08;
1028 *packet++ = 0x06;
1029
1030 *packet++ = x;
1031
1032 for (i = 0; i < data_len; i++)
1033 *packet++ = i;
1034
1035 lp->tx_dma_addr[x] =
1036 dma_map_single(&lp->pci_dev->dev, skb->data, skb->len,
1037 DMA_TO_DEVICE);
1038 if (dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[x])) {
1039 netif_printk(lp, hw, KERN_DEBUG, dev,
1040 "DMA mapping error at line: %d!\n",
1041 __LINE__);
1042 goto clean_up;
1043 }
1044 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
1045 wmb();
1046 lp->tx_ring[x].status = cpu_to_le16(status);
1047 }
1048
1049 x = a->read_bcr(ioaddr, 32);
1050 a->write_bcr(ioaddr, 32, x | 0x0002);
1051
1052
1053 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
1054 lp->a->write_csr(ioaddr, CSR15, x | 0x0044);
1055
1056 teststatus = cpu_to_le16(0x8000);
1057 lp->a->write_csr(ioaddr, CSR0, CSR0_START);
1058
1059
1060 for (x = 0; x < numbuffs; x++) {
1061 ticks = 0;
1062 rmb();
1063 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
1064 spin_unlock_irqrestore(&lp->lock, flags);
1065 msleep(1);
1066 spin_lock_irqsave(&lp->lock, flags);
1067 rmb();
1068 ticks++;
1069 }
1070 if (ticks == 200) {
1071 netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x);
1072 break;
1073 }
1074 }
1075
1076 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
1077 wmb();
1078 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
1079 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n");
1080
1081 for (x = 0; x < numbuffs; x++) {
1082 netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x);
1083 skb = lp->rx_skbuff[x];
1084 for (i = 0; i < size; i++)
1085 pr_cont(" %02x", *(skb->data + i));
1086 pr_cont("\n");
1087 }
1088 }
1089
1090 x = 0;
1091 rc = 0;
1092 while (x < numbuffs && !rc) {
1093 skb = lp->rx_skbuff[x];
1094 packet = lp->tx_skbuff[x]->data;
1095 for (i = 0; i < size; i++) {
1096 if (*(skb->data + i) != packet[i]) {
1097 netif_printk(lp, hw, KERN_DEBUG, dev,
1098 "Error in compare! %2x - %02x %02x\n",
1099 i, *(skb->data + i), packet[i]);
1100 rc = 1;
1101 break;
1102 }
1103 }
1104 x++;
1105 }
1106
1107clean_up:
1108 *data1 = rc;
1109 pcnet32_purge_tx_ring(dev);
1110
1111 x = a->read_csr(ioaddr, CSR15);
1112 a->write_csr(ioaddr, CSR15, (x & ~0x0044));
1113
1114 x = a->read_bcr(ioaddr, 32);
1115 a->write_bcr(ioaddr, 32, (x & ~0x0002));
1116
1117 if (netif_running(dev)) {
1118 pcnet32_netif_start(dev);
1119 pcnet32_restart(dev, CSR0_NORMAL);
1120 } else {
1121 pcnet32_purge_rx_ring(dev);
1122 lp->a->write_bcr(ioaddr, 20, 4);
1123 }
1124 spin_unlock_irqrestore(&lp->lock, flags);
1125
1126 return rc;
1127}
1128
1129static int pcnet32_set_phys_id(struct net_device *dev,
1130 enum ethtool_phys_id_state state)
1131{
1132 struct pcnet32_private *lp = netdev_priv(dev);
1133 const struct pcnet32_access *a = lp->a;
1134 ulong ioaddr = dev->base_addr;
1135 unsigned long flags;
1136 int i;
1137
1138 switch (state) {
1139 case ETHTOOL_ID_ACTIVE:
1140
1141 spin_lock_irqsave(&lp->lock, flags);
1142 for (i = 4; i < 8; i++)
1143 lp->save_regs[i - 4] = a->read_bcr(ioaddr, i);
1144 spin_unlock_irqrestore(&lp->lock, flags);
1145 return 2;
1146
1147 case ETHTOOL_ID_ON:
1148 case ETHTOOL_ID_OFF:
1149
1150 spin_lock_irqsave(&lp->lock, flags);
1151 for (i = 4; i < 8; i++)
1152 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1153 spin_unlock_irqrestore(&lp->lock, flags);
1154 break;
1155
1156 case ETHTOOL_ID_INACTIVE:
1157
1158 spin_lock_irqsave(&lp->lock, flags);
1159 for (i = 4; i < 8; i++)
1160 a->write_bcr(ioaddr, i, lp->save_regs[i - 4]);
1161 spin_unlock_irqrestore(&lp->lock, flags);
1162 }
1163 return 0;
1164}
1165
1166
1167
1168
1169
1170static void pcnet32_rx_entry(struct net_device *dev,
1171 struct pcnet32_private *lp,
1172 struct pcnet32_rx_head *rxp,
1173 int entry)
1174{
1175 int status = (short)le16_to_cpu(rxp->status) >> 8;
1176 int rx_in_place = 0;
1177 struct sk_buff *skb;
1178 short pkt_len;
1179
1180 if (status != 0x03) {
1181
1182
1183
1184
1185
1186
1187 if (status & 0x01)
1188 dev->stats.rx_errors++;
1189 if (status & 0x20)
1190 dev->stats.rx_frame_errors++;
1191 if (status & 0x10)
1192 dev->stats.rx_over_errors++;
1193 if (status & 0x08)
1194 dev->stats.rx_crc_errors++;
1195 if (status & 0x04)
1196 dev->stats.rx_fifo_errors++;
1197 return;
1198 }
1199
1200 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1201
1202
1203 if (unlikely(pkt_len > PKT_BUF_SIZE)) {
1204 netif_err(lp, drv, dev, "Impossible packet size %d!\n",
1205 pkt_len);
1206 dev->stats.rx_errors++;
1207 return;
1208 }
1209 if (pkt_len < 60) {
1210 netif_err(lp, rx_err, dev, "Runt packet!\n");
1211 dev->stats.rx_errors++;
1212 return;
1213 }
1214
1215 if (pkt_len > rx_copybreak) {
1216 struct sk_buff *newskb;
1217 dma_addr_t new_dma_addr;
1218
1219 newskb = netdev_alloc_skb(dev, PKT_BUF_SKB);
1220
1221
1222
1223
1224 if (newskb) {
1225 skb_reserve(newskb, NET_IP_ALIGN);
1226 new_dma_addr = dma_map_single(&lp->pci_dev->dev,
1227 newskb->data,
1228 PKT_BUF_SIZE,
1229 DMA_FROM_DEVICE);
1230 if (dma_mapping_error(&lp->pci_dev->dev, new_dma_addr)) {
1231 netif_err(lp, rx_err, dev,
1232 "DMA mapping error.\n");
1233 dev_kfree_skb(newskb);
1234 skb = NULL;
1235 } else {
1236 skb = lp->rx_skbuff[entry];
1237 dma_unmap_single(&lp->pci_dev->dev,
1238 lp->rx_dma_addr[entry],
1239 PKT_BUF_SIZE,
1240 DMA_FROM_DEVICE);
1241 skb_put(skb, pkt_len);
1242 lp->rx_skbuff[entry] = newskb;
1243 lp->rx_dma_addr[entry] = new_dma_addr;
1244 rxp->base = cpu_to_le32(new_dma_addr);
1245 rx_in_place = 1;
1246 }
1247 } else
1248 skb = NULL;
1249 } else
1250 skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN);
1251
1252 if (skb == NULL) {
1253 dev->stats.rx_dropped++;
1254 return;
1255 }
1256 if (!rx_in_place) {
1257 skb_reserve(skb, NET_IP_ALIGN);
1258 skb_put(skb, pkt_len);
1259 dma_sync_single_for_cpu(&lp->pci_dev->dev,
1260 lp->rx_dma_addr[entry], pkt_len,
1261 DMA_FROM_DEVICE);
1262 skb_copy_to_linear_data(skb,
1263 (unsigned char *)(lp->rx_skbuff[entry]->data),
1264 pkt_len);
1265 dma_sync_single_for_device(&lp->pci_dev->dev,
1266 lp->rx_dma_addr[entry], pkt_len,
1267 DMA_FROM_DEVICE);
1268 }
1269 dev->stats.rx_bytes += skb->len;
1270 skb->protocol = eth_type_trans(skb, dev);
1271 netif_receive_skb(skb);
1272 dev->stats.rx_packets++;
1273}
1274
1275static int pcnet32_rx(struct net_device *dev, int budget)
1276{
1277 struct pcnet32_private *lp = netdev_priv(dev);
1278 int entry = lp->cur_rx & lp->rx_mod_mask;
1279 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1280 int npackets = 0;
1281
1282
1283 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1284 pcnet32_rx_entry(dev, lp, rxp, entry);
1285 npackets += 1;
1286
1287
1288
1289
1290 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
1291 wmb();
1292 rxp->status = cpu_to_le16(0x8000);
1293 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1294 rxp = &lp->rx_ring[entry];
1295 }
1296
1297 return npackets;
1298}
1299
1300static int pcnet32_tx(struct net_device *dev)
1301{
1302 struct pcnet32_private *lp = netdev_priv(dev);
1303 unsigned int dirty_tx = lp->dirty_tx;
1304 int delta;
1305 int must_restart = 0;
1306
1307 while (dirty_tx != lp->cur_tx) {
1308 int entry = dirty_tx & lp->tx_mod_mask;
1309 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1310
1311 if (status < 0)
1312 break;
1313
1314 lp->tx_ring[entry].base = 0;
1315
1316 if (status & 0x4000) {
1317
1318 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1319 dev->stats.tx_errors++;
1320 netif_err(lp, tx_err, dev,
1321 "Tx error status=%04x err_status=%08x\n",
1322 status, err_status);
1323 if (err_status & 0x04000000)
1324 dev->stats.tx_aborted_errors++;
1325 if (err_status & 0x08000000)
1326 dev->stats.tx_carrier_errors++;
1327 if (err_status & 0x10000000)
1328 dev->stats.tx_window_errors++;
1329#ifndef DO_DXSUFLO
1330 if (err_status & 0x40000000) {
1331 dev->stats.tx_fifo_errors++;
1332
1333
1334 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1335 must_restart = 1;
1336 }
1337#else
1338 if (err_status & 0x40000000) {
1339 dev->stats.tx_fifo_errors++;
1340 if (!lp->dxsuflo) {
1341
1342
1343 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1344 must_restart = 1;
1345 }
1346 }
1347#endif
1348 } else {
1349 if (status & 0x1800)
1350 dev->stats.collisions++;
1351 dev->stats.tx_packets++;
1352 }
1353
1354
1355 if (lp->tx_skbuff[entry]) {
1356 dma_unmap_single(&lp->pci_dev->dev,
1357 lp->tx_dma_addr[entry],
1358 lp->tx_skbuff[entry]->len,
1359 DMA_TO_DEVICE);
1360 dev_kfree_skb_any(lp->tx_skbuff[entry]);
1361 lp->tx_skbuff[entry] = NULL;
1362 lp->tx_dma_addr[entry] = 0;
1363 }
1364 dirty_tx++;
1365 }
1366
1367 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1368 if (delta > lp->tx_ring_size) {
1369 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1370 dirty_tx, lp->cur_tx, lp->tx_full);
1371 dirty_tx += lp->tx_ring_size;
1372 delta -= lp->tx_ring_size;
1373 }
1374
1375 if (lp->tx_full &&
1376 netif_queue_stopped(dev) &&
1377 delta < lp->tx_ring_size - 2) {
1378
1379 lp->tx_full = 0;
1380 netif_wake_queue(dev);
1381 }
1382 lp->dirty_tx = dirty_tx;
1383
1384 return must_restart;
1385}
1386
1387static int pcnet32_poll(struct napi_struct *napi, int budget)
1388{
1389 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1390 struct net_device *dev = lp->dev;
1391 unsigned long ioaddr = dev->base_addr;
1392 unsigned long flags;
1393 int work_done;
1394 u16 val;
1395
1396 work_done = pcnet32_rx(dev, budget);
1397
1398 spin_lock_irqsave(&lp->lock, flags);
1399 if (pcnet32_tx(dev)) {
1400
1401 lp->a->reset(ioaddr);
1402 lp->a->write_csr(ioaddr, CSR4, 0x0915);
1403 pcnet32_restart(dev, CSR0_START);
1404 netif_wake_queue(dev);
1405 }
1406
1407 if (work_done < budget && napi_complete_done(napi, work_done)) {
1408
1409 val = lp->a->read_csr(ioaddr, CSR3);
1410 val &= 0x00ff;
1411 lp->a->write_csr(ioaddr, CSR3, val);
1412
1413
1414 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN);
1415 }
1416
1417 spin_unlock_irqrestore(&lp->lock, flags);
1418 return work_done;
1419}
1420
1421#define PCNET32_REGS_PER_PHY 32
1422#define PCNET32_MAX_PHYS 32
1423static int pcnet32_get_regs_len(struct net_device *dev)
1424{
1425 struct pcnet32_private *lp = netdev_priv(dev);
1426 int j = lp->phycount * PCNET32_REGS_PER_PHY;
1427
1428 return (PCNET32_NUM_REGS + j) * sizeof(u16);
1429}
1430
1431static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1432 void *ptr)
1433{
1434 int i, csr0;
1435 u16 *buff = ptr;
1436 struct pcnet32_private *lp = netdev_priv(dev);
1437 const struct pcnet32_access *a = lp->a;
1438 ulong ioaddr = dev->base_addr;
1439 unsigned long flags;
1440
1441 spin_lock_irqsave(&lp->lock, flags);
1442
1443 csr0 = a->read_csr(ioaddr, CSR0);
1444 if (!(csr0 & CSR0_STOP))
1445 pcnet32_suspend(dev, &flags, 1);
1446
1447
1448 for (i = 0; i < 16; i += 2)
1449 *buff++ = inw(ioaddr + i);
1450
1451
1452 for (i = 0; i < 90; i++)
1453 *buff++ = a->read_csr(ioaddr, i);
1454
1455 *buff++ = a->read_csr(ioaddr, 112);
1456 *buff++ = a->read_csr(ioaddr, 114);
1457
1458
1459 for (i = 0; i < 30; i++)
1460 *buff++ = a->read_bcr(ioaddr, i);
1461
1462 *buff++ = 0;
1463
1464 for (i = 31; i < 36; i++)
1465 *buff++ = a->read_bcr(ioaddr, i);
1466
1467
1468 if (lp->mii) {
1469 int j;
1470 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1471 if (lp->phymask & (1 << j)) {
1472 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1473 lp->a->write_bcr(ioaddr, 33,
1474 (j << 5) | i);
1475 *buff++ = lp->a->read_bcr(ioaddr, 34);
1476 }
1477 }
1478 }
1479 }
1480
1481 if (!(csr0 & CSR0_STOP))
1482 pcnet32_clr_suspend(lp, ioaddr);
1483
1484 spin_unlock_irqrestore(&lp->lock, flags);
1485}
1486
1487static const struct ethtool_ops pcnet32_ethtool_ops = {
1488 .get_drvinfo = pcnet32_get_drvinfo,
1489 .get_msglevel = pcnet32_get_msglevel,
1490 .set_msglevel = pcnet32_set_msglevel,
1491 .nway_reset = pcnet32_nway_reset,
1492 .get_link = pcnet32_get_link,
1493 .get_ringparam = pcnet32_get_ringparam,
1494 .set_ringparam = pcnet32_set_ringparam,
1495 .get_strings = pcnet32_get_strings,
1496 .self_test = pcnet32_ethtool_test,
1497 .set_phys_id = pcnet32_set_phys_id,
1498 .get_regs_len = pcnet32_get_regs_len,
1499 .get_regs = pcnet32_get_regs,
1500 .get_sset_count = pcnet32_get_sset_count,
1501 .get_link_ksettings = pcnet32_get_link_ksettings,
1502 .set_link_ksettings = pcnet32_set_link_ksettings,
1503};
1504
1505
1506
1507
1508static void pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1509{
1510 unsigned int *port, ioaddr;
1511
1512
1513 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1514 if (request_region
1515 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1516
1517 if ((inb(ioaddr + 14) == 0x57) &&
1518 (inb(ioaddr + 15) == 0x57)) {
1519 pcnet32_probe1(ioaddr, 0, NULL);
1520 } else {
1521 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1522 }
1523 }
1524 }
1525}
1526
1527static int
1528pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1529{
1530 unsigned long ioaddr;
1531 int err;
1532
1533 err = pci_enable_device(pdev);
1534 if (err < 0) {
1535 if (pcnet32_debug & NETIF_MSG_PROBE)
1536 pr_err("failed to enable device -- err=%d\n", err);
1537 return err;
1538 }
1539 pci_set_master(pdev);
1540
1541 if (!pci_resource_len(pdev, 0)) {
1542 if (pcnet32_debug & NETIF_MSG_PROBE)
1543 pr_err("card has no PCI IO resources, aborting\n");
1544 err = -ENODEV;
1545 goto err_disable_dev;
1546 }
1547
1548 err = dma_set_mask(&pdev->dev, PCNET32_DMA_MASK);
1549 if (err) {
1550 if (pcnet32_debug & NETIF_MSG_PROBE)
1551 pr_err("architecture does not support 32bit PCI busmaster DMA\n");
1552 goto err_disable_dev;
1553 }
1554
1555 ioaddr = pci_resource_start(pdev, 0);
1556 if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) {
1557 if (pcnet32_debug & NETIF_MSG_PROBE)
1558 pr_err("io address range already allocated\n");
1559 err = -EBUSY;
1560 goto err_disable_dev;
1561 }
1562
1563 err = pcnet32_probe1(ioaddr, 1, pdev);
1564
1565err_disable_dev:
1566 if (err < 0)
1567 pci_disable_device(pdev);
1568
1569 return err;
1570}
1571
1572static const struct net_device_ops pcnet32_netdev_ops = {
1573 .ndo_open = pcnet32_open,
1574 .ndo_stop = pcnet32_close,
1575 .ndo_start_xmit = pcnet32_start_xmit,
1576 .ndo_tx_timeout = pcnet32_tx_timeout,
1577 .ndo_get_stats = pcnet32_get_stats,
1578 .ndo_set_rx_mode = pcnet32_set_multicast_list,
1579 .ndo_eth_ioctl = pcnet32_ioctl,
1580 .ndo_set_mac_address = eth_mac_addr,
1581 .ndo_validate_addr = eth_validate_addr,
1582#ifdef CONFIG_NET_POLL_CONTROLLER
1583 .ndo_poll_controller = pcnet32_poll_controller,
1584#endif
1585};
1586
1587
1588
1589
1590
1591static int
1592pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1593{
1594 struct pcnet32_private *lp;
1595 int i, media;
1596 int fdx, mii, fset, dxsuflo, sram;
1597 int chip_version;
1598 char *chipname;
1599 struct net_device *dev;
1600 const struct pcnet32_access *a = NULL;
1601 u8 promaddr[ETH_ALEN];
1602 u8 addr[ETH_ALEN];
1603 int ret = -ENODEV;
1604
1605
1606 pcnet32_wio_reset(ioaddr);
1607
1608
1609 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1610 a = &pcnet32_wio;
1611 } else {
1612 pcnet32_dwio_reset(ioaddr);
1613 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&
1614 pcnet32_dwio_check(ioaddr)) {
1615 a = &pcnet32_dwio;
1616 } else {
1617 if (pcnet32_debug & NETIF_MSG_PROBE)
1618 pr_err("No access methods\n");
1619 goto err_release_region;
1620 }
1621 }
1622
1623 chip_version =
1624 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1625 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1626 pr_info(" PCnet chip version is %#x\n", chip_version);
1627 if ((chip_version & 0xfff) != 0x003) {
1628 if (pcnet32_debug & NETIF_MSG_PROBE)
1629 pr_info("Unsupported chip version\n");
1630 goto err_release_region;
1631 }
1632
1633
1634 fdx = mii = fset = dxsuflo = sram = 0;
1635 chip_version = (chip_version >> 12) & 0xffff;
1636
1637 switch (chip_version) {
1638 case 0x2420:
1639 chipname = "PCnet/PCI 79C970";
1640 break;
1641 case 0x2430:
1642 if (shared)
1643 chipname = "PCnet/PCI 79C970";
1644 else
1645 chipname = "PCnet/32 79C965";
1646 break;
1647 case 0x2621:
1648 chipname = "PCnet/PCI II 79C970A";
1649 fdx = 1;
1650 break;
1651 case 0x2623:
1652 chipname = "PCnet/FAST 79C971";
1653 fdx = 1;
1654 mii = 1;
1655 fset = 1;
1656 break;
1657 case 0x2624:
1658 chipname = "PCnet/FAST+ 79C972";
1659 fdx = 1;
1660 mii = 1;
1661 fset = 1;
1662 break;
1663 case 0x2625:
1664 chipname = "PCnet/FAST III 79C973";
1665 fdx = 1;
1666 mii = 1;
1667 sram = 1;
1668 break;
1669 case 0x2626:
1670 chipname = "PCnet/Home 79C978";
1671 fdx = 1;
1672
1673
1674
1675
1676
1677
1678 media = a->read_bcr(ioaddr, 49);
1679 media &= ~3;
1680 if (cards_found < MAX_UNITS && homepna[cards_found])
1681 media |= 1;
1682 if (pcnet32_debug & NETIF_MSG_PROBE)
1683 printk(KERN_DEBUG PFX "media set to %sMbit mode\n",
1684 (media & 1) ? "1" : "10");
1685 a->write_bcr(ioaddr, 49, media);
1686 break;
1687 case 0x2627:
1688 chipname = "PCnet/FAST III 79C975";
1689 fdx = 1;
1690 mii = 1;
1691 sram = 1;
1692 break;
1693 case 0x2628:
1694 chipname = "PCnet/PRO 79C976";
1695 fdx = 1;
1696 mii = 1;
1697 break;
1698 default:
1699 if (pcnet32_debug & NETIF_MSG_PROBE)
1700 pr_info("PCnet version %#x, no PCnet32 chip\n",
1701 chip_version);
1702 goto err_release_region;
1703 }
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713 if (fset) {
1714 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1715 a->write_csr(ioaddr, 80,
1716 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1717 dxsuflo = 1;
1718 }
1719
1720
1721
1722
1723
1724
1725
1726 if (sram) {
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739 a->write_bcr(ioaddr, 25, 0x17);
1740 a->write_bcr(ioaddr, 26, 0xc);
1741
1742 a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11));
1743 }
1744
1745 dev = alloc_etherdev(sizeof(*lp));
1746 if (!dev) {
1747 ret = -ENOMEM;
1748 goto err_release_region;
1749 }
1750
1751 if (pdev)
1752 SET_NETDEV_DEV(dev, &pdev->dev);
1753
1754 if (pcnet32_debug & NETIF_MSG_PROBE)
1755 pr_info("%s at %#3lx,", chipname, ioaddr);
1756
1757
1758
1759
1760
1761
1762
1763
1764 for (i = 0; i < 3; i++) {
1765 unsigned int val;
1766 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1767
1768 addr[2 * i] = val & 0x0ff;
1769 addr[2 * i + 1] = (val >> 8) & 0x0ff;
1770 }
1771 eth_hw_addr_set(dev, addr);
1772
1773
1774 for (i = 0; i < ETH_ALEN; i++)
1775 promaddr[i] = inb(ioaddr + i);
1776
1777 if (!ether_addr_equal(promaddr, dev->dev_addr) ||
1778 !is_valid_ether_addr(dev->dev_addr)) {
1779 if (is_valid_ether_addr(promaddr)) {
1780 if (pcnet32_debug & NETIF_MSG_PROBE) {
1781 pr_cont(" warning: CSR address invalid,\n");
1782 pr_info(" using instead PROM address of");
1783 }
1784 eth_hw_addr_set(dev, promaddr);
1785 }
1786 }
1787
1788
1789 if (!is_valid_ether_addr(dev->dev_addr)) {
1790 static const u8 zero_addr[ETH_ALEN] = {};
1791
1792 eth_hw_addr_set(dev, zero_addr);
1793 }
1794
1795 if (pcnet32_debug & NETIF_MSG_PROBE) {
1796 pr_cont(" %pM", dev->dev_addr);
1797
1798
1799 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1800 i = a->read_csr(ioaddr, 80) & 0x0C00;
1801 pr_info(" tx_start_pt(0x%04x):", i);
1802 switch (i >> 10) {
1803 case 0:
1804 pr_cont(" 20 bytes,");
1805 break;
1806 case 1:
1807 pr_cont(" 64 bytes,");
1808 break;
1809 case 2:
1810 pr_cont(" 128 bytes,");
1811 break;
1812 case 3:
1813 pr_cont("~220 bytes,");
1814 break;
1815 }
1816 i = a->read_bcr(ioaddr, 18);
1817 pr_cont(" BCR18(%x):", i & 0xffff);
1818 if (i & (1 << 5))
1819 pr_cont("BurstWrEn ");
1820 if (i & (1 << 6))
1821 pr_cont("BurstRdEn ");
1822 if (i & (1 << 7))
1823 pr_cont("DWordIO ");
1824 if (i & (1 << 11))
1825 pr_cont("NoUFlow ");
1826 i = a->read_bcr(ioaddr, 25);
1827 pr_info(" SRAMSIZE=0x%04x,", i << 8);
1828 i = a->read_bcr(ioaddr, 26);
1829 pr_cont(" SRAM_BND=0x%04x,", i << 8);
1830 i = a->read_bcr(ioaddr, 27);
1831 if (i & (1 << 14))
1832 pr_cont("LowLatRx");
1833 }
1834 }
1835
1836 dev->base_addr = ioaddr;
1837 lp = netdev_priv(dev);
1838
1839 lp->init_block = dma_alloc_coherent(&pdev->dev,
1840 sizeof(*lp->init_block),
1841 &lp->init_dma_addr, GFP_KERNEL);
1842 if (!lp->init_block) {
1843 if (pcnet32_debug & NETIF_MSG_PROBE)
1844 pr_err("Coherent memory allocation failed\n");
1845 ret = -ENOMEM;
1846 goto err_free_netdev;
1847 }
1848 lp->pci_dev = pdev;
1849
1850 lp->dev = dev;
1851
1852 spin_lock_init(&lp->lock);
1853
1854 lp->name = chipname;
1855 lp->shared_irq = shared;
1856 lp->tx_ring_size = TX_RING_SIZE;
1857 lp->rx_ring_size = RX_RING_SIZE;
1858 lp->tx_mod_mask = lp->tx_ring_size - 1;
1859 lp->rx_mod_mask = lp->rx_ring_size - 1;
1860 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1861 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1862 lp->mii_if.full_duplex = fdx;
1863 lp->mii_if.phy_id_mask = 0x1f;
1864 lp->mii_if.reg_num_mask = 0x1f;
1865 lp->dxsuflo = dxsuflo;
1866 lp->mii = mii;
1867 lp->chip_version = chip_version;
1868 lp->msg_enable = pcnet32_debug;
1869 if ((cards_found >= MAX_UNITS) ||
1870 (options[cards_found] >= sizeof(options_mapping)))
1871 lp->options = PCNET32_PORT_ASEL;
1872 else
1873 lp->options = options_mapping[options[cards_found]];
1874
1875 if (lp->chip_version == PCNET32_79C970A)
1876 lp->options = PCNET32_PORT_10BT;
1877 lp->mii_if.dev = dev;
1878 lp->mii_if.mdio_read = mdio_read;
1879 lp->mii_if.mdio_write = mdio_write;
1880
1881
1882 lp->napi.weight = lp->rx_ring_size / 2;
1883
1884 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1885
1886 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1887 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1888 lp->options |= PCNET32_PORT_FD;
1889
1890 lp->a = a;
1891
1892
1893 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1894 ret = -ENOMEM;
1895 goto err_free_ring;
1896 }
1897
1898 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&
1899 dev->dev_addr[2] == 0x75)
1900 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1901
1902 lp->init_block->mode = cpu_to_le16(0x0003);
1903 lp->init_block->tlen_rlen =
1904 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1905 for (i = 0; i < 6; i++)
1906 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1907 lp->init_block->filter[0] = 0x00000000;
1908 lp->init_block->filter[1] = 0x00000000;
1909 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1910 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1911
1912
1913 a->write_bcr(ioaddr, 20, 2);
1914
1915 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1916 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1917
1918 if (pdev) {
1919 dev->irq = pdev->irq;
1920 if (pcnet32_debug & NETIF_MSG_PROBE)
1921 pr_cont(" assigned IRQ %d\n", dev->irq);
1922 } else {
1923 unsigned long irq_mask = probe_irq_on();
1924
1925
1926
1927
1928
1929
1930
1931 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1932 mdelay(1);
1933
1934 dev->irq = probe_irq_off(irq_mask);
1935 if (!dev->irq) {
1936 if (pcnet32_debug & NETIF_MSG_PROBE)
1937 pr_cont(", failed to detect IRQ line\n");
1938 ret = -ENODEV;
1939 goto err_free_ring;
1940 }
1941 if (pcnet32_debug & NETIF_MSG_PROBE)
1942 pr_cont(", probed IRQ %d\n", dev->irq);
1943 }
1944
1945
1946 if (lp->mii) {
1947
1948
1949 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1950
1951 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1952 unsigned short id1, id2;
1953
1954 id1 = mdio_read(dev, i, MII_PHYSID1);
1955 if (id1 == 0xffff)
1956 continue;
1957 id2 = mdio_read(dev, i, MII_PHYSID2);
1958 if (id2 == 0xffff)
1959 continue;
1960 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1961 continue;
1962 lp->phycount++;
1963 lp->phymask |= (1 << i);
1964 lp->mii_if.phy_id = i;
1965 if (pcnet32_debug & NETIF_MSG_PROBE)
1966 pr_info("Found PHY %04x:%04x at address %d\n",
1967 id1, id2, i);
1968 }
1969 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1970 if (lp->phycount > 1)
1971 lp->options |= PCNET32_PORT_MII;
1972 }
1973
1974 timer_setup(&lp->watchdog_timer, pcnet32_watchdog, 0);
1975
1976
1977 dev->netdev_ops = &pcnet32_netdev_ops;
1978 dev->ethtool_ops = &pcnet32_ethtool_ops;
1979 dev->watchdog_timeo = (5 * HZ);
1980
1981
1982 if (register_netdev(dev))
1983 goto err_free_ring;
1984
1985 if (pdev) {
1986 pci_set_drvdata(pdev, dev);
1987 } else {
1988 lp->next = pcnet32_dev;
1989 pcnet32_dev = dev;
1990 }
1991
1992 if (pcnet32_debug & NETIF_MSG_PROBE)
1993 pr_info("%s: registered as %s\n", dev->name, lp->name);
1994 cards_found++;
1995
1996
1997 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1998
1999 return 0;
2000
2001err_free_ring:
2002 pcnet32_free_ring(dev);
2003 dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block),
2004 lp->init_block, lp->init_dma_addr);
2005err_free_netdev:
2006 free_netdev(dev);
2007err_release_region:
2008 release_region(ioaddr, PCNET32_TOTAL_SIZE);
2009 return ret;
2010}
2011
2012
2013static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
2014{
2015 struct pcnet32_private *lp = netdev_priv(dev);
2016
2017 lp->tx_ring = dma_alloc_coherent(&lp->pci_dev->dev,
2018 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
2019 &lp->tx_ring_dma_addr, GFP_KERNEL);
2020 if (lp->tx_ring == NULL) {
2021 netif_err(lp, drv, dev, "Coherent memory allocation failed\n");
2022 return -ENOMEM;
2023 }
2024
2025 lp->rx_ring = dma_alloc_coherent(&lp->pci_dev->dev,
2026 sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
2027 &lp->rx_ring_dma_addr, GFP_KERNEL);
2028 if (lp->rx_ring == NULL) {
2029 netif_err(lp, drv, dev, "Coherent memory allocation failed\n");
2030 return -ENOMEM;
2031 }
2032
2033 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
2034 GFP_KERNEL);
2035 if (!lp->tx_dma_addr)
2036 return -ENOMEM;
2037
2038 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
2039 GFP_KERNEL);
2040 if (!lp->rx_dma_addr)
2041 return -ENOMEM;
2042
2043 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
2044 GFP_KERNEL);
2045 if (!lp->tx_skbuff)
2046 return -ENOMEM;
2047
2048 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2049 GFP_KERNEL);
2050 if (!lp->rx_skbuff)
2051 return -ENOMEM;
2052
2053 return 0;
2054}
2055
2056static void pcnet32_free_ring(struct net_device *dev)
2057{
2058 struct pcnet32_private *lp = netdev_priv(dev);
2059
2060 kfree(lp->tx_skbuff);
2061 lp->tx_skbuff = NULL;
2062
2063 kfree(lp->rx_skbuff);
2064 lp->rx_skbuff = NULL;
2065
2066 kfree(lp->tx_dma_addr);
2067 lp->tx_dma_addr = NULL;
2068
2069 kfree(lp->rx_dma_addr);
2070 lp->rx_dma_addr = NULL;
2071
2072 if (lp->tx_ring) {
2073 dma_free_coherent(&lp->pci_dev->dev,
2074 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
2075 lp->tx_ring, lp->tx_ring_dma_addr);
2076 lp->tx_ring = NULL;
2077 }
2078
2079 if (lp->rx_ring) {
2080 dma_free_coherent(&lp->pci_dev->dev,
2081 sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
2082 lp->rx_ring, lp->rx_ring_dma_addr);
2083 lp->rx_ring = NULL;
2084 }
2085}
2086
2087static int pcnet32_open(struct net_device *dev)
2088{
2089 struct pcnet32_private *lp = netdev_priv(dev);
2090 struct pci_dev *pdev = lp->pci_dev;
2091 unsigned long ioaddr = dev->base_addr;
2092 u16 val;
2093 int i;
2094 int rc;
2095 unsigned long flags;
2096
2097 if (request_irq(dev->irq, pcnet32_interrupt,
2098 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2099 (void *)dev)) {
2100 return -EAGAIN;
2101 }
2102
2103 spin_lock_irqsave(&lp->lock, flags);
2104
2105 if (!is_valid_ether_addr(dev->dev_addr)) {
2106 rc = -EINVAL;
2107 goto err_free_irq;
2108 }
2109
2110
2111 lp->a->reset(ioaddr);
2112
2113
2114 lp->a->write_bcr(ioaddr, 20, 2);
2115
2116 netif_printk(lp, ifup, KERN_DEBUG, dev,
2117 "%s() irq %d tx/rx rings %#x/%#x init %#x\n",
2118 __func__, dev->irq, (u32) (lp->tx_ring_dma_addr),
2119 (u32) (lp->rx_ring_dma_addr),
2120 (u32) (lp->init_dma_addr));
2121
2122 lp->autoneg = !!(lp->options & PCNET32_PORT_ASEL);
2123 lp->port_tp = !!(lp->options & PCNET32_PORT_10BT);
2124 lp->fdx = !!(lp->options & PCNET32_PORT_FD);
2125
2126
2127 val = lp->a->read_bcr(ioaddr, 2) & ~2;
2128 if (lp->options & PCNET32_PORT_ASEL)
2129 val |= 2;
2130 lp->a->write_bcr(ioaddr, 2, val);
2131
2132
2133 if (lp->mii_if.full_duplex) {
2134 val = lp->a->read_bcr(ioaddr, 9) & ~3;
2135 if (lp->options & PCNET32_PORT_FD) {
2136 val |= 1;
2137 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2138 val |= 2;
2139 } else if (lp->options & PCNET32_PORT_ASEL) {
2140
2141 if (lp->chip_version == 0x2627)
2142 val |= 3;
2143 }
2144 lp->a->write_bcr(ioaddr, 9, val);
2145 }
2146
2147
2148 val = lp->a->read_csr(ioaddr, 124) & ~0x10;
2149 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2150 val |= 0x10;
2151 lp->a->write_csr(ioaddr, 124, val);
2152
2153
2154 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2155 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2156 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2157 if (lp->options & PCNET32_PORT_ASEL) {
2158 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2159 netif_printk(lp, link, KERN_DEBUG, dev,
2160 "Setting 100Mb-Full Duplex\n");
2161 }
2162 }
2163 if (lp->phycount < 2) {
2164
2165
2166
2167
2168
2169 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2170 lp->a->write_bcr(ioaddr, 32,
2171 lp->a->read_bcr(ioaddr, 32) | 0x0080);
2172
2173 val = lp->a->read_bcr(ioaddr, 32) & ~0xb8;
2174 if (lp->options & PCNET32_PORT_FD)
2175 val |= 0x10;
2176 if (lp->options & PCNET32_PORT_100)
2177 val |= 0x08;
2178 lp->a->write_bcr(ioaddr, 32, val);
2179 } else {
2180 if (lp->options & PCNET32_PORT_ASEL) {
2181 lp->a->write_bcr(ioaddr, 32,
2182 lp->a->read_bcr(ioaddr,
2183 32) | 0x0080);
2184
2185 val = lp->a->read_bcr(ioaddr, 32) & ~0x98;
2186 val |= 0x20;
2187 lp->a->write_bcr(ioaddr, 32, val);
2188 }
2189 }
2190 } else {
2191 int first_phy = -1;
2192 u16 bmcr;
2193 u32 bcr9;
2194 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
2195
2196
2197
2198
2199
2200 val = lp->a->read_bcr(ioaddr, 2);
2201 lp->a->write_bcr(ioaddr, 2, val & ~2);
2202 val = lp->a->read_bcr(ioaddr, 32);
2203 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7));
2204
2205 if (!(lp->options & PCNET32_PORT_ASEL)) {
2206
2207 ecmd.port = PORT_MII;
2208 ecmd.transceiver = XCVR_INTERNAL;
2209 ecmd.autoneg = AUTONEG_DISABLE;
2210 ethtool_cmd_speed_set(&ecmd,
2211 (lp->options & PCNET32_PORT_100) ?
2212 SPEED_100 : SPEED_10);
2213 bcr9 = lp->a->read_bcr(ioaddr, 9);
2214
2215 if (lp->options & PCNET32_PORT_FD) {
2216 ecmd.duplex = DUPLEX_FULL;
2217 bcr9 |= (1 << 0);
2218 } else {
2219 ecmd.duplex = DUPLEX_HALF;
2220 bcr9 |= ~(1 << 0);
2221 }
2222 lp->a->write_bcr(ioaddr, 9, bcr9);
2223 }
2224
2225 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2226 if (lp->phymask & (1 << i)) {
2227
2228 bmcr = mdio_read(dev, i, MII_BMCR);
2229 if (first_phy == -1) {
2230 first_phy = i;
2231 mdio_write(dev, i, MII_BMCR,
2232 bmcr & ~BMCR_ISOLATE);
2233 } else {
2234 mdio_write(dev, i, MII_BMCR,
2235 bmcr | BMCR_ISOLATE);
2236 }
2237
2238 lp->mii_if.phy_id = i;
2239 ecmd.phy_address = i;
2240 if (lp->options & PCNET32_PORT_ASEL) {
2241 mii_ethtool_gset(&lp->mii_if, &ecmd);
2242 ecmd.autoneg = AUTONEG_ENABLE;
2243 }
2244 mii_ethtool_sset(&lp->mii_if, &ecmd);
2245 }
2246 }
2247 lp->mii_if.phy_id = first_phy;
2248 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy);
2249 }
2250
2251#ifdef DO_DXSUFLO
2252 if (lp->dxsuflo) {
2253 val = lp->a->read_csr(ioaddr, CSR3);
2254 val |= 0x40;
2255 lp->a->write_csr(ioaddr, CSR3, val);
2256 }
2257#endif
2258
2259 lp->init_block->mode =
2260 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2261 pcnet32_load_multicast(dev);
2262
2263 if (pcnet32_init_ring(dev)) {
2264 rc = -ENOMEM;
2265 goto err_free_ring;
2266 }
2267
2268 napi_enable(&lp->napi);
2269
2270
2271 lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2272 lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2273
2274 lp->a->write_csr(ioaddr, CSR4, 0x0915);
2275 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2276
2277 netif_start_queue(dev);
2278
2279 if (lp->chip_version >= PCNET32_79C970A) {
2280
2281 pcnet32_check_media(dev, 1);
2282 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
2283 }
2284
2285 i = 0;
2286 while (i++ < 100)
2287 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2288 break;
2289
2290
2291
2292
2293 lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL);
2294
2295 netif_printk(lp, ifup, KERN_DEBUG, dev,
2296 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n",
2297 i,
2298 (u32) (lp->init_dma_addr),
2299 lp->a->read_csr(ioaddr, CSR0));
2300
2301 spin_unlock_irqrestore(&lp->lock, flags);
2302
2303 return 0;
2304
2305err_free_ring:
2306
2307 pcnet32_purge_rx_ring(dev);
2308
2309
2310
2311
2312
2313 lp->a->write_bcr(ioaddr, 20, 4);
2314
2315err_free_irq:
2316 spin_unlock_irqrestore(&lp->lock, flags);
2317 free_irq(dev->irq, dev);
2318 return rc;
2319}
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334static void pcnet32_purge_tx_ring(struct net_device *dev)
2335{
2336 struct pcnet32_private *lp = netdev_priv(dev);
2337 int i;
2338
2339 for (i = 0; i < lp->tx_ring_size; i++) {
2340 lp->tx_ring[i].status = 0;
2341 wmb();
2342 if (lp->tx_skbuff[i]) {
2343 if (!dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[i]))
2344 dma_unmap_single(&lp->pci_dev->dev,
2345 lp->tx_dma_addr[i],
2346 lp->tx_skbuff[i]->len,
2347 DMA_TO_DEVICE);
2348 dev_kfree_skb_any(lp->tx_skbuff[i]);
2349 }
2350 lp->tx_skbuff[i] = NULL;
2351 lp->tx_dma_addr[i] = 0;
2352 }
2353}
2354
2355
2356static int pcnet32_init_ring(struct net_device *dev)
2357{
2358 struct pcnet32_private *lp = netdev_priv(dev);
2359 int i;
2360
2361 lp->tx_full = 0;
2362 lp->cur_rx = lp->cur_tx = 0;
2363 lp->dirty_rx = lp->dirty_tx = 0;
2364
2365 for (i = 0; i < lp->rx_ring_size; i++) {
2366 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2367 if (rx_skbuff == NULL) {
2368 lp->rx_skbuff[i] = netdev_alloc_skb(dev, PKT_BUF_SKB);
2369 rx_skbuff = lp->rx_skbuff[i];
2370 if (!rx_skbuff) {
2371
2372 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
2373 __func__);
2374 return -1;
2375 }
2376 skb_reserve(rx_skbuff, NET_IP_ALIGN);
2377 }
2378
2379 rmb();
2380 if (lp->rx_dma_addr[i] == 0) {
2381 lp->rx_dma_addr[i] =
2382 dma_map_single(&lp->pci_dev->dev, rx_skbuff->data,
2383 PKT_BUF_SIZE, DMA_FROM_DEVICE);
2384 if (dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[i])) {
2385
2386 netif_err(lp, drv, dev,
2387 "%s pci dma mapping error\n",
2388 __func__);
2389 return -1;
2390 }
2391 }
2392 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2393 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
2394 wmb();
2395 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2396 }
2397
2398
2399 for (i = 0; i < lp->tx_ring_size; i++) {
2400 lp->tx_ring[i].status = 0;
2401 wmb();
2402 lp->tx_ring[i].base = 0;
2403 lp->tx_dma_addr[i] = 0;
2404 }
2405
2406 lp->init_block->tlen_rlen =
2407 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2408 for (i = 0; i < 6; i++)
2409 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2410 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2411 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2412 wmb();
2413 return 0;
2414}
2415
2416
2417
2418
2419
2420static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2421{
2422 struct pcnet32_private *lp = netdev_priv(dev);
2423 unsigned long ioaddr = dev->base_addr;
2424 int i;
2425
2426
2427 for (i = 0; i < 100; i++)
2428 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP)
2429 break;
2430
2431 if (i >= 100)
2432 netif_err(lp, drv, dev, "%s timed out waiting for stop\n",
2433 __func__);
2434
2435 pcnet32_purge_tx_ring(dev);
2436 if (pcnet32_init_ring(dev))
2437 return;
2438
2439
2440 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2441 i = 0;
2442 while (i++ < 1000)
2443 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2444 break;
2445
2446 lp->a->write_csr(ioaddr, CSR0, csr0_bits);
2447}
2448
2449static void pcnet32_tx_timeout(struct net_device *dev, unsigned int txqueue)
2450{
2451 struct pcnet32_private *lp = netdev_priv(dev);
2452 unsigned long ioaddr = dev->base_addr, flags;
2453
2454 spin_lock_irqsave(&lp->lock, flags);
2455
2456 if (pcnet32_debug & NETIF_MSG_DRV)
2457 pr_err("%s: transmit timed out, status %4.4x, resetting\n",
2458 dev->name, lp->a->read_csr(ioaddr, CSR0));
2459 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2460 dev->stats.tx_errors++;
2461 if (netif_msg_tx_err(lp)) {
2462 int i;
2463 printk(KERN_DEBUG
2464 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2465 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2466 lp->cur_rx);
2467 for (i = 0; i < lp->rx_ring_size; i++)
2468 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2469 le32_to_cpu(lp->rx_ring[i].base),
2470 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2471 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2472 le16_to_cpu(lp->rx_ring[i].status));
2473 for (i = 0; i < lp->tx_ring_size; i++)
2474 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2475 le32_to_cpu(lp->tx_ring[i].base),
2476 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2477 le32_to_cpu(lp->tx_ring[i].misc),
2478 le16_to_cpu(lp->tx_ring[i].status));
2479 printk("\n");
2480 }
2481 pcnet32_restart(dev, CSR0_NORMAL);
2482
2483 netif_trans_update(dev);
2484 netif_wake_queue(dev);
2485
2486 spin_unlock_irqrestore(&lp->lock, flags);
2487}
2488
2489static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2490 struct net_device *dev)
2491{
2492 struct pcnet32_private *lp = netdev_priv(dev);
2493 unsigned long ioaddr = dev->base_addr;
2494 u16 status;
2495 int entry;
2496 unsigned long flags;
2497
2498 spin_lock_irqsave(&lp->lock, flags);
2499
2500 netif_printk(lp, tx_queued, KERN_DEBUG, dev,
2501 "%s() called, csr0 %4.4x\n",
2502 __func__, lp->a->read_csr(ioaddr, CSR0));
2503
2504
2505
2506
2507 status = 0x8300;
2508
2509
2510
2511
2512 entry = lp->cur_tx & lp->tx_mod_mask;
2513
2514
2515
2516
2517 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2518
2519 lp->tx_ring[entry].misc = 0x00000000;
2520
2521 lp->tx_dma_addr[entry] =
2522 dma_map_single(&lp->pci_dev->dev, skb->data, skb->len,
2523 DMA_TO_DEVICE);
2524 if (dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[entry])) {
2525 dev_kfree_skb_any(skb);
2526 dev->stats.tx_dropped++;
2527 goto drop_packet;
2528 }
2529 lp->tx_skbuff[entry] = skb;
2530 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2531 wmb();
2532 lp->tx_ring[entry].status = cpu_to_le16(status);
2533
2534 lp->cur_tx++;
2535 dev->stats.tx_bytes += skb->len;
2536
2537
2538 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2539
2540 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2541 lp->tx_full = 1;
2542 netif_stop_queue(dev);
2543 }
2544drop_packet:
2545 spin_unlock_irqrestore(&lp->lock, flags);
2546 return NETDEV_TX_OK;
2547}
2548
2549
2550static irqreturn_t
2551pcnet32_interrupt(int irq, void *dev_id)
2552{
2553 struct net_device *dev = dev_id;
2554 struct pcnet32_private *lp;
2555 unsigned long ioaddr;
2556 u16 csr0;
2557 int boguscnt = max_interrupt_work;
2558
2559 ioaddr = dev->base_addr;
2560 lp = netdev_priv(dev);
2561
2562 spin_lock(&lp->lock);
2563
2564 csr0 = lp->a->read_csr(ioaddr, CSR0);
2565 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2566 if (csr0 == 0xffff)
2567 break;
2568
2569 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2570
2571 netif_printk(lp, intr, KERN_DEBUG, dev,
2572 "interrupt csr0=%#2.2x new csr=%#2.2x\n",
2573 csr0, lp->a->read_csr(ioaddr, CSR0));
2574
2575
2576 if (csr0 & 0x4000)
2577 dev->stats.tx_errors++;
2578 if (csr0 & 0x1000) {
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590 dev->stats.rx_errors++;
2591 }
2592 if (csr0 & 0x0800) {
2593 netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n",
2594 csr0);
2595
2596 }
2597 if (napi_schedule_prep(&lp->napi)) {
2598 u16 val;
2599
2600 val = lp->a->read_csr(ioaddr, CSR3);
2601 val |= 0x5f00;
2602 lp->a->write_csr(ioaddr, CSR3, val);
2603
2604 __napi_schedule(&lp->napi);
2605 break;
2606 }
2607 csr0 = lp->a->read_csr(ioaddr, CSR0);
2608 }
2609
2610 netif_printk(lp, intr, KERN_DEBUG, dev,
2611 "exiting interrupt, csr0=%#4.4x\n",
2612 lp->a->read_csr(ioaddr, CSR0));
2613
2614 spin_unlock(&lp->lock);
2615
2616 return IRQ_HANDLED;
2617}
2618
2619static int pcnet32_close(struct net_device *dev)
2620{
2621 unsigned long ioaddr = dev->base_addr;
2622 struct pcnet32_private *lp = netdev_priv(dev);
2623 unsigned long flags;
2624
2625 del_timer_sync(&lp->watchdog_timer);
2626
2627 netif_stop_queue(dev);
2628 napi_disable(&lp->napi);
2629
2630 spin_lock_irqsave(&lp->lock, flags);
2631
2632 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2633
2634 netif_printk(lp, ifdown, KERN_DEBUG, dev,
2635 "Shutting down ethercard, status was %2.2x\n",
2636 lp->a->read_csr(ioaddr, CSR0));
2637
2638
2639 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2640
2641
2642
2643
2644
2645 lp->a->write_bcr(ioaddr, 20, 4);
2646
2647 spin_unlock_irqrestore(&lp->lock, flags);
2648
2649 free_irq(dev->irq, dev);
2650
2651 spin_lock_irqsave(&lp->lock, flags);
2652
2653 pcnet32_purge_rx_ring(dev);
2654 pcnet32_purge_tx_ring(dev);
2655
2656 spin_unlock_irqrestore(&lp->lock, flags);
2657
2658 return 0;
2659}
2660
2661static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2662{
2663 struct pcnet32_private *lp = netdev_priv(dev);
2664 unsigned long ioaddr = dev->base_addr;
2665 unsigned long flags;
2666
2667 spin_lock_irqsave(&lp->lock, flags);
2668 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2669 spin_unlock_irqrestore(&lp->lock, flags);
2670
2671 return &dev->stats;
2672}
2673
2674
2675static void pcnet32_load_multicast(struct net_device *dev)
2676{
2677 struct pcnet32_private *lp = netdev_priv(dev);
2678 volatile struct pcnet32_init_block *ib = lp->init_block;
2679 volatile __le16 *mcast_table = (__le16 *)ib->filter;
2680 struct netdev_hw_addr *ha;
2681 unsigned long ioaddr = dev->base_addr;
2682 int i;
2683 u32 crc;
2684
2685
2686 if (dev->flags & IFF_ALLMULTI) {
2687 ib->filter[0] = cpu_to_le32(~0U);
2688 ib->filter[1] = cpu_to_le32(~0U);
2689 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2690 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2691 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2692 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2693 return;
2694 }
2695
2696 ib->filter[0] = 0;
2697 ib->filter[1] = 0;
2698
2699
2700 netdev_for_each_mc_addr(ha, dev) {
2701 crc = ether_crc_le(6, ha->addr);
2702 crc = crc >> 26;
2703 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2704 }
2705 for (i = 0; i < 4; i++)
2706 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i,
2707 le16_to_cpu(mcast_table[i]));
2708}
2709
2710
2711
2712
2713static void pcnet32_set_multicast_list(struct net_device *dev)
2714{
2715 unsigned long ioaddr = dev->base_addr, flags;
2716 struct pcnet32_private *lp = netdev_priv(dev);
2717 int csr15, suspended;
2718
2719 spin_lock_irqsave(&lp->lock, flags);
2720 suspended = pcnet32_suspend(dev, &flags, 0);
2721 csr15 = lp->a->read_csr(ioaddr, CSR15);
2722 if (dev->flags & IFF_PROMISC) {
2723
2724 netif_info(lp, hw, dev, "Promiscuous mode enabled\n");
2725 lp->init_block->mode =
2726 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2727 7);
2728 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000);
2729 } else {
2730 lp->init_block->mode =
2731 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2732 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2733 pcnet32_load_multicast(dev);
2734 }
2735
2736 if (suspended) {
2737 pcnet32_clr_suspend(lp, ioaddr);
2738 } else {
2739 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2740 pcnet32_restart(dev, CSR0_NORMAL);
2741 netif_wake_queue(dev);
2742 }
2743
2744 spin_unlock_irqrestore(&lp->lock, flags);
2745}
2746
2747
2748static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2749{
2750 struct pcnet32_private *lp = netdev_priv(dev);
2751 unsigned long ioaddr = dev->base_addr;
2752 u16 val_out;
2753
2754 if (!lp->mii)
2755 return 0;
2756
2757 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2758 val_out = lp->a->read_bcr(ioaddr, 34);
2759
2760 return val_out;
2761}
2762
2763
2764static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2765{
2766 struct pcnet32_private *lp = netdev_priv(dev);
2767 unsigned long ioaddr = dev->base_addr;
2768
2769 if (!lp->mii)
2770 return;
2771
2772 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2773 lp->a->write_bcr(ioaddr, 34, val);
2774}
2775
2776static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2777{
2778 struct pcnet32_private *lp = netdev_priv(dev);
2779 int rc;
2780 unsigned long flags;
2781
2782
2783 if (lp->mii) {
2784 spin_lock_irqsave(&lp->lock, flags);
2785 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2786 spin_unlock_irqrestore(&lp->lock, flags);
2787 } else {
2788 rc = -EOPNOTSUPP;
2789 }
2790
2791 return rc;
2792}
2793
2794static int pcnet32_check_otherphy(struct net_device *dev)
2795{
2796 struct pcnet32_private *lp = netdev_priv(dev);
2797 struct mii_if_info mii = lp->mii_if;
2798 u16 bmcr;
2799 int i;
2800
2801 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2802 if (i == lp->mii_if.phy_id)
2803 continue;
2804 if (lp->phymask & (1 << i)) {
2805 mii.phy_id = i;
2806 if (mii_link_ok(&mii)) {
2807
2808 netif_info(lp, link, dev, "Using PHY number %d\n",
2809 i);
2810
2811
2812 bmcr =
2813 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2814 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2815 bmcr | BMCR_ISOLATE);
2816
2817
2818 bmcr = mdio_read(dev, i, MII_BMCR);
2819 mdio_write(dev, i, MII_BMCR,
2820 bmcr & ~BMCR_ISOLATE);
2821
2822
2823 lp->mii_if.phy_id = i;
2824 return 1;
2825 }
2826 }
2827 }
2828 return 0;
2829}
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839static void pcnet32_check_media(struct net_device *dev, int verbose)
2840{
2841 struct pcnet32_private *lp = netdev_priv(dev);
2842 int curr_link;
2843 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2844 u32 bcr9;
2845
2846 if (lp->mii) {
2847 curr_link = mii_link_ok(&lp->mii_if);
2848 } else if (lp->chip_version == PCNET32_79C970A) {
2849 ulong ioaddr = dev->base_addr;
2850
2851 if (!lp->autoneg && lp->port_tp)
2852 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
2853 else
2854 curr_link = 1;
2855 } else {
2856 ulong ioaddr = dev->base_addr;
2857 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
2858 }
2859 if (!curr_link) {
2860 if (prev_link || verbose) {
2861 netif_carrier_off(dev);
2862 netif_info(lp, link, dev, "link down\n");
2863 }
2864 if (lp->phycount > 1) {
2865 pcnet32_check_otherphy(dev);
2866 }
2867 } else if (verbose || !prev_link) {
2868 netif_carrier_on(dev);
2869 if (lp->mii) {
2870 if (netif_msg_link(lp)) {
2871 struct ethtool_cmd ecmd = {
2872 .cmd = ETHTOOL_GSET };
2873 mii_ethtool_gset(&lp->mii_if, &ecmd);
2874 netdev_info(dev, "link up, %uMbps, %s-duplex\n",
2875 ethtool_cmd_speed(&ecmd),
2876 (ecmd.duplex == DUPLEX_FULL)
2877 ? "full" : "half");
2878 }
2879 bcr9 = lp->a->read_bcr(dev->base_addr, 9);
2880 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2881 if (lp->mii_if.full_duplex)
2882 bcr9 |= (1 << 0);
2883 else
2884 bcr9 &= ~(1 << 0);
2885 lp->a->write_bcr(dev->base_addr, 9, bcr9);
2886 }
2887 } else {
2888 netif_info(lp, link, dev, "link up\n");
2889 }
2890 }
2891}
2892
2893
2894
2895
2896
2897
2898static void pcnet32_watchdog(struct timer_list *t)
2899{
2900 struct pcnet32_private *lp = from_timer(lp, t, watchdog_timer);
2901 struct net_device *dev = lp->dev;
2902 unsigned long flags;
2903
2904
2905 spin_lock_irqsave(&lp->lock, flags);
2906 pcnet32_check_media(dev, 0);
2907 spin_unlock_irqrestore(&lp->lock, flags);
2908
2909 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
2910}
2911
2912static int __maybe_unused pcnet32_pm_suspend(struct device *device_d)
2913{
2914 struct net_device *dev = dev_get_drvdata(device_d);
2915
2916 if (netif_running(dev)) {
2917 netif_device_detach(dev);
2918 pcnet32_close(dev);
2919 }
2920
2921 return 0;
2922}
2923
2924static int __maybe_unused pcnet32_pm_resume(struct device *device_d)
2925{
2926 struct net_device *dev = dev_get_drvdata(device_d);
2927
2928 if (netif_running(dev)) {
2929 pcnet32_open(dev);
2930 netif_device_attach(dev);
2931 }
2932
2933 return 0;
2934}
2935
2936static void pcnet32_remove_one(struct pci_dev *pdev)
2937{
2938 struct net_device *dev = pci_get_drvdata(pdev);
2939
2940 if (dev) {
2941 struct pcnet32_private *lp = netdev_priv(dev);
2942
2943 unregister_netdev(dev);
2944 pcnet32_free_ring(dev);
2945 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2946 dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block),
2947 lp->init_block, lp->init_dma_addr);
2948 free_netdev(dev);
2949 pci_disable_device(pdev);
2950 }
2951}
2952
2953static SIMPLE_DEV_PM_OPS(pcnet32_pm_ops, pcnet32_pm_suspend, pcnet32_pm_resume);
2954
2955static struct pci_driver pcnet32_driver = {
2956 .name = DRV_NAME,
2957 .probe = pcnet32_probe_pci,
2958 .remove = pcnet32_remove_one,
2959 .id_table = pcnet32_pci_tbl,
2960 .driver = {
2961 .pm = &pcnet32_pm_ops,
2962 },
2963};
2964
2965
2966static int debug = -1;
2967static int tx_start_pt = -1;
2968static int pcnet32_have_pci;
2969
2970module_param(debug, int, 0);
2971MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2972module_param(max_interrupt_work, int, 0);
2973MODULE_PARM_DESC(max_interrupt_work,
2974 DRV_NAME " maximum events handled per interrupt");
2975module_param(rx_copybreak, int, 0);
2976MODULE_PARM_DESC(rx_copybreak,
2977 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2978module_param(tx_start_pt, int, 0);
2979MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2980module_param(pcnet32vlb, int, 0);
2981MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2982module_param_array(options, int, NULL, 0);
2983MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2984module_param_array(full_duplex, int, NULL, 0);
2985MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2986
2987module_param_array(homepna, int, NULL, 0);
2988MODULE_PARM_DESC(homepna,
2989 DRV_NAME
2990 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2991
2992MODULE_AUTHOR("Thomas Bogendoerfer");
2993MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2994MODULE_LICENSE("GPL");
2995
2996#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2997
2998static int __init pcnet32_init_module(void)
2999{
3000 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
3001
3002 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3003 tx_start = tx_start_pt;
3004
3005
3006 if (!pci_register_driver(&pcnet32_driver))
3007 pcnet32_have_pci = 1;
3008
3009
3010 if (pcnet32vlb)
3011 pcnet32_probe_vlbus(pcnet32_portlist);
3012
3013 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3014 pr_info("%d cards_found\n", cards_found);
3015
3016 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
3017}
3018
3019static void __exit pcnet32_cleanup_module(void)
3020{
3021 struct net_device *next_dev;
3022
3023 while (pcnet32_dev) {
3024 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
3025 next_dev = lp->next;
3026 unregister_netdev(pcnet32_dev);
3027 pcnet32_free_ring(pcnet32_dev);
3028 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3029 dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block),
3030 lp->init_block, lp->init_dma_addr);
3031 free_netdev(pcnet32_dev);
3032 pcnet32_dev = next_dev;
3033 }
3034
3035 if (pcnet32_have_pci)
3036 pci_unregister_driver(&pcnet32_driver);
3037}
3038
3039module_init(pcnet32_init_module);
3040module_exit(pcnet32_cleanup_module);
3041