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4#ifndef _ICE_ADMINQ_CMD_H_
5#define _ICE_ADMINQ_CMD_H_
6
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8
9
10
11#define ICE_MAX_VSI 768
12#define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
13#define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
14
15struct ice_aqc_generic {
16 __le32 param0;
17 __le32 param1;
18 __le32 addr_high;
19 __le32 addr_low;
20};
21
22
23struct ice_aqc_get_ver {
24 __le32 rom_ver;
25 __le32 fw_build;
26 u8 fw_branch;
27 u8 fw_major;
28 u8 fw_minor;
29 u8 fw_patch;
30 u8 api_branch;
31 u8 api_major;
32 u8 api_minor;
33 u8 api_patch;
34};
35
36
37struct ice_aqc_driver_ver {
38 u8 major_ver;
39 u8 minor_ver;
40 u8 build_ver;
41 u8 subbuild_ver;
42 u8 reserved[4];
43 __le32 addr_high;
44 __le32 addr_low;
45};
46
47
48struct ice_aqc_q_shutdown {
49 u8 driver_unloading;
50#define ICE_AQC_DRIVER_UNLOADING BIT(0)
51 u8 reserved[15];
52};
53
54
55
56
57struct ice_aqc_req_res {
58 __le16 res_id;
59#define ICE_AQC_RES_ID_NVM 1
60#define ICE_AQC_RES_ID_SDP 2
61#define ICE_AQC_RES_ID_CHNG_LOCK 3
62#define ICE_AQC_RES_ID_GLBL_LOCK 4
63 __le16 access_type;
64#define ICE_AQC_RES_ACCESS_READ 1
65#define ICE_AQC_RES_ACCESS_WRITE 2
66
67
68
69
70
71 __le32 timeout;
72#define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
73#define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
74#define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
75#define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
76
77 __le32 res_number;
78
79 __le16 status;
80#define ICE_AQ_RES_GLBL_SUCCESS 0
81#define ICE_AQ_RES_GLBL_IN_PROG 1
82#define ICE_AQ_RES_GLBL_DONE 2
83 u8 reserved[2];
84};
85
86
87
88
89struct ice_aqc_list_caps {
90 u8 cmd_flags;
91 u8 pf_index;
92 u8 reserved[2];
93 __le32 count;
94 __le32 addr_high;
95 __le32 addr_low;
96};
97
98
99struct ice_aqc_list_caps_elem {
100 __le16 cap;
101#define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
102#define ICE_AQC_CAPS_SRIOV 0x0012
103#define ICE_AQC_CAPS_VF 0x0013
104#define ICE_AQC_CAPS_VSI 0x0017
105#define ICE_AQC_CAPS_DCB 0x0018
106#define ICE_AQC_CAPS_RSS 0x0040
107#define ICE_AQC_CAPS_RXQS 0x0041
108#define ICE_AQC_CAPS_TXQS 0x0042
109#define ICE_AQC_CAPS_MSIX 0x0043
110#define ICE_AQC_CAPS_FD 0x0045
111#define ICE_AQC_CAPS_1588 0x0046
112#define ICE_AQC_CAPS_MAX_MTU 0x0047
113#define ICE_AQC_CAPS_NVM_VER 0x0048
114#define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049
115#define ICE_AQC_CAPS_OROM_VER 0x004A
116#define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B
117#define ICE_AQC_CAPS_NET_VER 0x004C
118#define ICE_AQC_CAPS_PENDING_NET_VER 0x004D
119#define ICE_AQC_CAPS_RDMA 0x0051
120#define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
121#define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077
122#define ICE_AQC_CAPS_NVM_MGMT 0x0080
123
124 u8 major_ver;
125 u8 minor_ver;
126
127 __le32 number;
128
129 __le32 logical_id;
130
131 __le32 phys_id;
132 __le64 rsvd1;
133 __le64 rsvd2;
134};
135
136
137
138
139struct ice_aqc_manage_mac_read {
140 __le16 flags;
141#define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
142#define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
143#define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
144#define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
145#define ICE_AQC_MAN_MAC_READ_S 4
146#define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
147 u8 rsvd[2];
148 u8 num_addr;
149 u8 rsvd1[3];
150 __le32 addr_high;
151 __le32 addr_low;
152};
153
154
155struct ice_aqc_manage_mac_read_resp {
156 u8 lport_num;
157 u8 addr_type;
158#define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
159#define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
160 u8 mac_addr[ETH_ALEN];
161};
162
163
164struct ice_aqc_manage_mac_write {
165 u8 rsvd;
166 u8 flags;
167#define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
168#define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
169#define ICE_AQC_MAN_MAC_WR_S 6
170#define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S)
171#define ICE_AQC_MAN_MAC_UPDATE_LAA 0
172#define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
173
174 u8 mac_addr[ETH_ALEN];
175 __le32 addr_high;
176 __le32 addr_low;
177};
178
179
180struct ice_aqc_clear_pxe {
181 u8 rx_cnt;
182#define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
183 u8 reserved[15];
184};
185
186
187struct ice_aqc_get_sw_cfg {
188
189 __le16 flags;
190
191
192
193
194
195 __le16 element;
196
197 __le16 num_elems;
198 __le16 rsvd;
199 __le32 addr_high;
200 __le32 addr_low;
201};
202
203
204struct ice_aqc_get_sw_cfg_resp_elem {
205
206 __le16 vsi_port_num;
207#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
208#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
209 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
210#define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
211#define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
212#define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
213#define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
214#define ICE_AQC_GET_SW_CONF_RESP_VSI 2
215
216
217 __le16 swid;
218
219
220
221
222 __le16 pf_vf_num;
223#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
224#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
225 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
226#define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
227};
228
229
230struct ice_aqc_set_port_params {
231 __le16 cmd_flags;
232#define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2)
233 __le16 bad_frame_vsi;
234 __le16 swid;
235 u8 reserved[10];
236};
237
238
239
240
241
242
243
244
245#define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
246#define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
247#define ICE_AQC_RES_TYPE_RECIPE 0x05
248#define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
249#define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
250#define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
251#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
252#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
253#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
254#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
255
256#define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
257#define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
258#define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
259
260#define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
261
262#define ICE_AQC_RES_TYPE_S 0
263#define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
264
265
266
267
268struct ice_aqc_alloc_free_res_cmd {
269 __le16 num_entries;
270 u8 reserved[6];
271 __le32 addr_high;
272 __le32 addr_low;
273};
274
275
276struct ice_aqc_res_elem {
277 union {
278 __le16 sw_resp;
279 __le16 flu_resp;
280 } e;
281};
282
283
284struct ice_aqc_alloc_free_res_elem {
285 __le16 res_type;
286#define ICE_AQC_RES_TYPE_SHARED_S 7
287#define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S)
288#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
289#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
290 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
291 __le16 num_elems;
292 struct ice_aqc_res_elem elem[];
293};
294
295
296struct ice_aqc_set_vlan_mode {
297 u8 reserved;
298 u8 l2tag_prio_tagging;
299#define ICE_AQ_VLAN_PRIO_TAG_S 0
300#define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S)
301#define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0
302#define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1
303#define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2
304#define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3
305#define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4
306#define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4
307#define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7
308 u8 l2tag_reserved[64];
309 u8 rdma_packet;
310#define ICE_AQ_VLAN_RDMA_TAG_S 0
311#define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S)
312#define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10
313#define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A
314 u8 rdma_reserved[2];
315 u8 mng_vlan_prot_id;
316#define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10
317#define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11
318 u8 prot_id_reserved[30];
319};
320
321
322struct ice_aqc_get_vlan_mode {
323 u8 vlan_mode;
324#define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0)
325 u8 l2tag_prio_tagging;
326 u8 reserved[98];
327};
328
329
330
331
332
333
334struct ice_aqc_add_get_update_free_vsi {
335 __le16 vsi_num;
336#define ICE_AQ_VSI_NUM_S 0
337#define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
338#define ICE_AQ_VSI_IS_VALID BIT(15)
339 __le16 cmd_flags;
340#define ICE_AQ_VSI_KEEP_ALLOC 0x1
341 u8 vf_id;
342 u8 reserved;
343 __le16 vsi_flags;
344#define ICE_AQ_VSI_TYPE_S 0
345#define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
346#define ICE_AQ_VSI_TYPE_VF 0x0
347#define ICE_AQ_VSI_TYPE_VMDQ2 0x1
348#define ICE_AQ_VSI_TYPE_PF 0x2
349#define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
350 __le32 addr_high;
351 __le32 addr_low;
352};
353
354
355
356
357
358
359struct ice_aqc_add_update_free_vsi_resp {
360 __le16 vsi_num;
361 __le16 ext_status;
362 __le16 vsi_used;
363 __le16 vsi_free;
364 __le32 addr_high;
365 __le32 addr_low;
366};
367
368struct ice_aqc_vsi_props {
369 __le16 valid_sections;
370#define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
371#define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
372#define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
373#define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
374#define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
375#define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
376#define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
377#define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
378#define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
379#define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
380#define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
381
382 u8 sw_id;
383 u8 sw_flags;
384#define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
385#define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
386#define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
387 u8 sw_flags2;
388#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
389#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
390#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
391#define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
392 u8 veb_stat_id;
393#define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
394#define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
395#define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
396
397 u8 sec_flags;
398#define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
399#define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
400#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
401#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
402#define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
403 u8 sec_reserved;
404
405 __le16 port_based_inner_vlan;
406 u8 inner_vlan_reserved[2];
407 u8 inner_vlan_flags;
408#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0
409#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)
410#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
411#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
412#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3
413#define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2)
414#define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3
415#define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
416#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
417#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
418#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
419#define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
420 u8 inner_vlan_reserved2[3];
421
422 __le32 ingress_table;
423#define ICE_AQ_VSI_UP_TABLE_UP0_S 0
424#define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
425#define ICE_AQ_VSI_UP_TABLE_UP1_S 3
426#define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
427#define ICE_AQ_VSI_UP_TABLE_UP2_S 6
428#define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
429#define ICE_AQ_VSI_UP_TABLE_UP3_S 9
430#define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
431#define ICE_AQ_VSI_UP_TABLE_UP4_S 12
432#define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
433#define ICE_AQ_VSI_UP_TABLE_UP5_S 15
434#define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
435#define ICE_AQ_VSI_UP_TABLE_UP6_S 18
436#define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
437#define ICE_AQ_VSI_UP_TABLE_UP7_S 21
438#define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
439 __le32 egress_table;
440
441 __le16 port_based_outer_vlan;
442 u8 outer_vlan_flags;
443#define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0
444#define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)
445#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0
446#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1
447#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2
448#define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3
449#define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
450#define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
451#define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
452#define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
453#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
454#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
455#define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4)
456#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5
457#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)
458#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
459#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
460#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3
461#define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7)
462 u8 outer_vlan_reserved;
463
464 __le16 mapping_flags;
465#define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
466#define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
467 __le16 q_mapping[16];
468#define ICE_AQ_VSI_Q_S 0
469#define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
470 __le16 tc_mapping[8];
471#define ICE_AQ_VSI_TC_Q_OFFSET_S 0
472#define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
473#define ICE_AQ_VSI_TC_Q_NUM_S 11
474#define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
475
476 u8 q_opt_rss;
477#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
478#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
479#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
480#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
481#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
482#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
483#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
484#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
485#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
486#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
487#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
488#define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
489#define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
490 u8 q_opt_tc;
491#define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
492#define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
493#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
494 u8 q_opt_flags;
495#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
496 u8 q_opt_reserved[3];
497
498 __le32 outer_up_table;
499
500 __le16 sect_10_reserved;
501
502 __le16 fd_options;
503#define ICE_AQ_VSI_FD_ENABLE BIT(0)
504#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
505#define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
506 __le16 max_fd_fltr_dedicated;
507 __le16 max_fd_fltr_shared;
508 __le16 fd_def_q;
509#define ICE_AQ_VSI_FD_DEF_Q_S 0
510#define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
511#define ICE_AQ_VSI_FD_DEF_GRP_S 12
512#define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
513 __le16 fd_report_opt;
514#define ICE_AQ_VSI_FD_REPORT_Q_S 0
515#define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
516#define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
517#define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
518#define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
519
520 __le32 pasid_id;
521#define ICE_AQ_VSI_PASID_ID_S 0
522#define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
523#define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
524 u8 reserved[24];
525};
526
527#define ICE_MAX_NUM_RECIPES 64
528
529
530struct ice_aqc_add_get_recipe {
531 __le16 num_sub_recipes;
532 __le16 return_index;
533 u8 reserved[4];
534 __le32 addr_high;
535 __le32 addr_low;
536};
537
538struct ice_aqc_recipe_content {
539 u8 rid;
540#define ICE_AQ_RECIPE_ID_S 0
541#define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S)
542#define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7)
543#define ICE_AQ_SW_ID_LKUP_IDX 0
544 u8 lkup_indx[5];
545#define ICE_AQ_RECIPE_LKUP_DATA_S 0
546#define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)
547#define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7)
548#define ICE_AQ_SW_ID_LKUP_MASK 0x00FF
549 __le16 mask[5];
550 u8 result_indx;
551#define ICE_AQ_RECIPE_RESULT_DATA_S 0
552#define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S)
553#define ICE_AQ_RECIPE_RESULT_EN BIT(7)
554 u8 rsvd0[3];
555 u8 act_ctrl_join_priority;
556 u8 act_ctrl_fwd_priority;
557#define ICE_AQ_RECIPE_FWD_PRIORITY_S 0
558#define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S)
559 u8 act_ctrl;
560#define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0)
561#define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1)
562#define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2)
563#define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4
564#define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S)
565 u8 rsvd1;
566 __le32 dflt_act;
567#define ICE_AQ_RECIPE_DFLT_ACT_S 0
568#define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S)
569#define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31)
570};
571
572struct ice_aqc_recipe_data_elem {
573 u8 recipe_indx;
574 u8 resp_bits;
575#define ICE_AQ_RECIPE_WAS_UPDATED BIT(0)
576 u8 rsvd0[2];
577 u8 recipe_bitmap[8];
578 u8 rsvd1[4];
579 struct ice_aqc_recipe_content content;
580 u8 rsvd2[20];
581};
582
583
584struct ice_aqc_recipe_to_profile {
585 __le16 profile_id;
586 u8 rsvd[6];
587 DECLARE_BITMAP(recipe_assoc, ICE_MAX_NUM_RECIPES);
588};
589
590
591
592struct ice_aqc_sw_rules {
593
594
595
596
597
598 __le16 num_rules_fltr_entry_index;
599 u8 reserved[6];
600 __le32 addr_high;
601 __le32 addr_low;
602};
603
604
605
606
607
608
609struct ice_sw_rule_lkup_rx_tx {
610 __le16 recipe_id;
611#define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
612
613 __le16 src;
614 __le32 act;
615
616
617#define ICE_SINGLE_ACT_TYPE_S 0x00
618#define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
619
620
621
622
623#define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
624#define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
625
626
627#define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
628
629#define ICE_SINGLE_ACT_VSI_ID_S 4
630#define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
631#define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
632#define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
633
634#define ICE_SINGLE_ACT_VSI_LIST BIT(14)
635#define ICE_SINGLE_ACT_VALID_BIT BIT(17)
636#define ICE_SINGLE_ACT_DROP BIT(18)
637
638
639#define ICE_SINGLE_ACT_TO_Q 0x1
640#define ICE_SINGLE_ACT_Q_INDEX_S 4
641#define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
642#define ICE_SINGLE_ACT_Q_REGION_S 15
643#define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
644#define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
645
646
647#define ICE_SINGLE_ACT_PRUNE 0x2
648#define ICE_SINGLE_ACT_EGRESS BIT(15)
649#define ICE_SINGLE_ACT_INGRESS BIT(16)
650#define ICE_SINGLE_ACT_PRUNET BIT(17)
651
652
653
654#define ICE_SINGLE_ACT_PTR 0x2
655#define ICE_SINGLE_ACT_PTR_VAL_S 4
656#define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
657
658#define ICE_SINGLE_ACT_PTR_BIT BIT(18)
659
660
661
662
663#define ICE_SINGLE_ACT_OTHER_ACTS 0x3
664#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
665#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
666 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
667
668
669
670#define ICE_SINGLE_OTHER_ACT_MIRROR 0
671#define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
672#define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
673 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
674
675
676#define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
677#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
678#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
679 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
680
681 __le16 index;
682
683
684
685 __le16 hdr_len;
686 u8 hdr[];
687};
688
689
690
691
692
693struct ice_sw_rule_lg_act {
694 __le16 index;
695 __le16 size;
696
697#define ICE_MAX_LG_ACT 4
698
699#define ICE_LG_ACT_TYPE_S 0
700#define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
701
702
703#define ICE_LG_ACT_VSI_FORWARDING 0
704#define ICE_LG_ACT_VSI_ID_S 3
705#define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
706#define ICE_LG_ACT_VSI_LIST_ID_S 3
707#define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
708
709#define ICE_LG_ACT_VSI_LIST BIT(13)
710
711#define ICE_LG_ACT_VALID_BIT BIT(16)
712
713
714#define ICE_LG_ACT_TO_Q 0x1
715#define ICE_LG_ACT_Q_INDEX_S 3
716#define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
717#define ICE_LG_ACT_Q_REGION_S 14
718#define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
719#define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
720
721
722#define ICE_LG_ACT_PRUNE 0x2
723#define ICE_LG_ACT_EGRESS BIT(14)
724#define ICE_LG_ACT_INGRESS BIT(15)
725#define ICE_LG_ACT_PRUNET BIT(16)
726
727
728#define ICE_LG_OTHER_ACT_MIRROR 0x3
729#define ICE_LG_ACT_MIRROR_VSI_ID_S 3
730#define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
731
732
733#define ICE_LG_ACT_GENERIC 0x5
734#define ICE_LG_ACT_GENERIC_VALUE_S 3
735#define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
736#define ICE_LG_ACT_GENERIC_OFFSET_S 19
737#define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
738#define ICE_LG_ACT_GENERIC_PRIORITY_S 22
739#define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
740#define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
741
742
743#define ICE_LG_ACT_STAT_COUNT 0x7
744#define ICE_LG_ACT_STAT_COUNT_S 3
745#define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
746 __le32 act[];
747};
748
749
750
751
752
753struct ice_sw_rule_vsi_list {
754 __le16 index;
755 __le16 number_vsi;
756 __le16 vsi[];
757};
758
759
760struct ice_sw_rule_vsi_list_query {
761 __le16 index;
762 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI);
763} __packed;
764
765
766
767
768
769struct ice_aqc_sw_rules_elem {
770 __le16 type;
771#define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
772#define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
773#define ICE_AQC_SW_RULES_T_LG_ACT 0x2
774#define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
775#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
776#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
777#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
778 __le16 status;
779 union {
780 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
781 struct ice_sw_rule_lg_act lg_act;
782 struct ice_sw_rule_vsi_list vsi_list;
783 struct ice_sw_rule_vsi_list_query vsi_list_query;
784 } __packed pdata;
785};
786
787
788
789
790struct ice_aqc_set_query_pfc_mode {
791 u8 pfc_mode;
792
793#define ICE_AQC_PFC_VLAN_BASED_PFC 1
794#define ICE_AQC_PFC_DSCP_BASED_PFC 2
795 u8 rsvd[15];
796};
797
798struct ice_aqc_get_topo {
799 u8 port_num;
800 u8 num_branches;
801 __le16 reserved1;
802 __le32 reserved2;
803 __le32 addr_high;
804 __le32 addr_low;
805};
806
807
808
809
810
811
812
813
814
815struct ice_aqc_sched_elem_cmd {
816 __le16 num_elem_req;
817 __le16 num_elem_resp;
818 __le32 reserved;
819 __le32 addr_high;
820 __le32 addr_low;
821};
822
823struct ice_aqc_txsched_move_grp_info_hdr {
824 __le32 src_parent_teid;
825 __le32 dest_parent_teid;
826 __le16 num_elems;
827 __le16 reserved;
828};
829
830struct ice_aqc_move_elem {
831 struct ice_aqc_txsched_move_grp_info_hdr hdr;
832 __le32 teid[];
833};
834
835struct ice_aqc_elem_info_bw {
836 __le16 bw_profile_idx;
837 __le16 bw_alloc;
838};
839
840struct ice_aqc_txsched_elem {
841 u8 elem_type;
842#define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
843#define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
844#define ICE_AQC_ELEM_TYPE_TC 0x2
845#define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
846#define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
847#define ICE_AQC_ELEM_TYPE_LEAF 0x5
848#define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
849 u8 valid_sections;
850#define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
851#define ICE_AQC_ELEM_VALID_CIR BIT(1)
852#define ICE_AQC_ELEM_VALID_EIR BIT(2)
853#define ICE_AQC_ELEM_VALID_SHARED BIT(3)
854 u8 generic;
855#define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
856#define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
857#define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
858#define ICE_AQC_ELEM_GENERIC_SP_S 0x4
859#define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
860#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
861#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
862 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
863 u8 flags;
864#define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
865 struct ice_aqc_elem_info_bw cir_bw;
866 struct ice_aqc_elem_info_bw eir_bw;
867 __le16 srl_id;
868 __le16 reserved2;
869};
870
871struct ice_aqc_txsched_elem_data {
872 __le32 parent_teid;
873 __le32 node_teid;
874 struct ice_aqc_txsched_elem data;
875};
876
877struct ice_aqc_txsched_topo_grp_info_hdr {
878 __le32 parent_teid;
879 __le16 num_elems;
880 __le16 reserved2;
881};
882
883struct ice_aqc_add_elem {
884 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
885 struct ice_aqc_txsched_elem_data generic[];
886};
887
888struct ice_aqc_get_topo_elem {
889 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
890 struct ice_aqc_txsched_elem_data
891 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
892};
893
894struct ice_aqc_delete_elem {
895 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
896 __le32 teid[];
897};
898
899
900
901
902
903struct ice_aqc_query_port_ets {
904 __le32 port_teid;
905 __le32 reserved;
906 __le32 addr_high;
907 __le32 addr_low;
908};
909
910struct ice_aqc_port_ets_elem {
911 u8 tc_valid_bits;
912 u8 reserved[3];
913
914 __le32 up2tc;
915 u8 tc_bw_share[8];
916 __le32 port_eir_prof_id;
917 __le32 port_cir_prof_id;
918
919 __le32 tc_node_prio;
920#define ICE_TC_NODE_PRIO_S 0x4
921 u8 reserved1[4];
922 __le32 tc_node_teid[8];
923};
924
925
926
927
928
929
930
931
932struct ice_aqc_rl_profile {
933 __le16 num_profiles;
934 __le16 num_processed;
935 u8 reserved[4];
936 __le32 addr_high;
937 __le32 addr_low;
938};
939
940struct ice_aqc_rl_profile_elem {
941 u8 level;
942 u8 flags;
943#define ICE_AQC_RL_PROFILE_TYPE_S 0x0
944#define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
945#define ICE_AQC_RL_PROFILE_TYPE_CIR 0
946#define ICE_AQC_RL_PROFILE_TYPE_EIR 1
947#define ICE_AQC_RL_PROFILE_TYPE_SRL 2
948
949#define ICE_AQC_RL_PROFILE_INVAL_S 0x7
950#define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
951
952 __le16 profile_id;
953 __le16 max_burst_size;
954 __le16 rl_multiply;
955 __le16 wake_up_calc;
956 __le16 rl_encode;
957};
958
959
960
961
962
963struct ice_aqc_query_txsched_res {
964 u8 reserved[8];
965 __le32 addr_high;
966 __le32 addr_low;
967};
968
969struct ice_aqc_generic_sched_props {
970 __le16 phys_levels;
971 __le16 logical_levels;
972 u8 flattening_bitmap;
973 u8 max_device_cgds;
974 u8 max_pf_cgds;
975 u8 rsvd0;
976 __le16 rdma_qsets;
977 u8 rsvd1[22];
978};
979
980struct ice_aqc_layer_props {
981 u8 logical_layer;
982 u8 chunk_size;
983 __le16 max_device_nodes;
984 __le16 max_pf_nodes;
985 u8 rsvd0[4];
986 __le16 max_sibl_grp_sz;
987 __le16 max_cir_rl_profiles;
988 __le16 max_eir_rl_profiles;
989 __le16 max_srl_profiles;
990 u8 rsvd1[14];
991};
992
993struct ice_aqc_query_txsched_res_resp {
994 struct ice_aqc_generic_sched_props sched_props;
995 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
996};
997
998
999struct ice_aqc_get_phy_caps {
1000 u8 lport_num;
1001 u8 reserved;
1002 __le16 param0;
1003
1004#define ICE_AQC_GET_PHY_RQM BIT(0)
1005
1006
1007
1008
1009
1010
1011#define ICE_AQC_REPORT_MODE_S 1
1012#define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S)
1013#define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0
1014#define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)
1015#define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)
1016#define ICE_AQC_REPORT_DFLT_CFG BIT(3)
1017 __le32 reserved1;
1018 __le32 addr_high;
1019 __le32 addr_low;
1020};
1021
1022
1023
1024
1025#define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1026#define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1027#define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1028#define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
1029#define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
1030#define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
1031#define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1032#define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1033#define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1034#define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
1035#define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1036#define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1037#define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1038#define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
1039#define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
1040#define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
1041#define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
1042#define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
1043#define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
1044#define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
1045#define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
1046#define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
1047#define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1048#define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1049#define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1050#define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1051#define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1052#define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1053#define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1054#define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1055#define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1056#define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1057#define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1058#define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1059#define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1060#define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1061#define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1062#define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1063#define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1064#define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1065#define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1066#define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1067#define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1068#define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1069#define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1070#define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1071#define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1072#define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1073#define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1074#define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1075#define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1076#define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1077#define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1078#define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1079#define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1080#define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1081#define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1082#define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1083#define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1084#define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1085#define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1086#define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1087#define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1088#define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1089#define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1090
1091#define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1092#define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1093#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1094#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1095#define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1096#define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
1097
1098struct ice_aqc_get_phy_caps_data {
1099 __le64 phy_type_low;
1100 __le64 phy_type_high;
1101 u8 caps;
1102#define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1103#define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1104#define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1105#define ICE_AQC_PHY_EN_LINK BIT(3)
1106#define ICE_AQC_PHY_AN_MODE BIT(4)
1107#define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5)
1108#define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1109#define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0)
1110 u8 low_power_ctrl_an;
1111#define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1112#define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
1113#define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
1114#define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
1115 __le16 eee_cap;
1116#define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1117#define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1118#define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1119#define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1120#define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1121#define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1122#define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1123 __le16 eeer_value;
1124 u8 phy_id_oui[4];
1125 u8 phy_fw_ver[8];
1126 u8 link_fec_options;
1127#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1128#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1129#define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1130#define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1131#define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1132#define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1133#define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1134#define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0)
1135 u8 module_compliance_enforcement;
1136#define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
1137 u8 extended_compliance_code;
1138#define ICE_MODULE_TYPE_TOTAL_BYTE 3
1139 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1140#define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1141#define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1142#define ICE_AQC_MOD_TYPE_IDENT 1
1143#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1144#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1145#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1146#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1147#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1148#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1149#define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1150#define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1151 u8 qualified_module_count;
1152 u8 rsvd2[7];
1153#define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1154 struct {
1155 u8 v_oui[3];
1156 u8 rsvd3;
1157 u8 v_part[16];
1158 __le32 v_rev;
1159 __le64 rsvd4;
1160 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1161};
1162
1163
1164
1165
1166struct ice_aqc_set_phy_cfg {
1167 u8 lport_num;
1168 u8 reserved[7];
1169 __le32 addr_high;
1170 __le32 addr_low;
1171};
1172
1173
1174struct ice_aqc_set_phy_cfg_data {
1175 __le64 phy_type_low;
1176 __le64 phy_type_high;
1177 u8 caps;
1178#define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0)
1179#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1180#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1181#define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1182#define ICE_AQ_PHY_ENA_LINK BIT(3)
1183#define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1184#define ICE_AQ_PHY_ENA_LESM BIT(6)
1185#define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1186 u8 low_power_ctrl_an;
1187 __le16 eee_cap;
1188 __le16 eeer_value;
1189 u8 link_fec_opt;
1190 u8 module_compliance_enforcement;
1191};
1192
1193
1194struct ice_aqc_set_mac_cfg {
1195 __le16 max_frame_size;
1196 u8 params;
1197#define ICE_AQ_SET_MAC_PACE_S 3
1198#define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1199#define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1200#define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1201#define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1202 u8 tx_tmr_priority;
1203 __le16 tx_tmr_value;
1204 __le16 fc_refresh_threshold;
1205 u8 drop_opts;
1206#define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1207#define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1208#define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1209 u8 reserved[7];
1210};
1211
1212
1213
1214
1215struct ice_aqc_restart_an {
1216 u8 lport_num;
1217 u8 reserved;
1218 u8 cmd_flags;
1219#define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1220#define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1221 u8 reserved2[13];
1222};
1223
1224
1225struct ice_aqc_get_link_status {
1226 u8 lport_num;
1227 u8 reserved;
1228 __le16 cmd_flags;
1229#define ICE_AQ_LSE_M 0x3
1230#define ICE_AQ_LSE_NOP 0x0
1231#define ICE_AQ_LSE_DIS 0x2
1232#define ICE_AQ_LSE_ENA 0x3
1233
1234#define ICE_AQ_LSE_IS_ENABLED 0x1
1235 __le32 reserved2;
1236 __le32 addr_high;
1237 __le32 addr_low;
1238};
1239
1240
1241struct ice_aqc_get_link_status_data {
1242 u8 topo_media_conflict;
1243#define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1244#define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1245#define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1246#define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1247#define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1248#define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1249#define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1250 u8 link_cfg_err;
1251#define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5)
1252#define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6)
1253#define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7)
1254 u8 link_info;
1255#define ICE_AQ_LINK_UP BIT(0)
1256#define ICE_AQ_LINK_FAULT BIT(1)
1257#define ICE_AQ_LINK_FAULT_TX BIT(2)
1258#define ICE_AQ_LINK_FAULT_RX BIT(3)
1259#define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1260#define ICE_AQ_LINK_UP_PORT BIT(5)
1261#define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1262#define ICE_AQ_SIGNAL_DETECT BIT(7)
1263 u8 an_info;
1264#define ICE_AQ_AN_COMPLETED BIT(0)
1265#define ICE_AQ_LP_AN_ABILITY BIT(1)
1266#define ICE_AQ_PD_FAULT BIT(2)
1267#define ICE_AQ_FEC_EN BIT(3)
1268#define ICE_AQ_PHY_LOW_POWER BIT(4)
1269#define ICE_AQ_LINK_PAUSE_TX BIT(5)
1270#define ICE_AQ_LINK_PAUSE_RX BIT(6)
1271#define ICE_AQ_QUALIFIED_MODULE BIT(7)
1272 u8 ext_info;
1273#define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1274#define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1)
1275
1276#define ICE_AQ_LINK_TX_S 2
1277#define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1278#define ICE_AQ_LINK_TX_ACTIVE 0
1279#define ICE_AQ_LINK_TX_DRAINED 1
1280#define ICE_AQ_LINK_TX_FLUSHED 3
1281 u8 reserved2;
1282 __le16 max_frame_size;
1283 u8 cfg;
1284#define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1285#define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1286#define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1287#define ICE_AQ_FEC_MASK ICE_M(0x7, 0)
1288
1289#define ICE_AQ_CFG_PACING_S 3
1290#define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1291#define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1292#define ICE_AQ_CFG_PACING_TYPE_AVG 0
1293#define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1294
1295 u8 power_desc;
1296#define ICE_AQ_PWR_CLASS_M 0x3F
1297#define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1298#define ICE_AQ_LINK_PWR_BASET_HIGH 1
1299#define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1300#define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1301#define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1302#define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1303 __le16 link_speed;
1304#define ICE_AQ_LINK_SPEED_M 0x7FF
1305#define ICE_AQ_LINK_SPEED_10MB BIT(0)
1306#define ICE_AQ_LINK_SPEED_100MB BIT(1)
1307#define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1308#define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1309#define ICE_AQ_LINK_SPEED_5GB BIT(4)
1310#define ICE_AQ_LINK_SPEED_10GB BIT(5)
1311#define ICE_AQ_LINK_SPEED_20GB BIT(6)
1312#define ICE_AQ_LINK_SPEED_25GB BIT(7)
1313#define ICE_AQ_LINK_SPEED_40GB BIT(8)
1314#define ICE_AQ_LINK_SPEED_50GB BIT(9)
1315#define ICE_AQ_LINK_SPEED_100GB BIT(10)
1316#define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1317 __le32 reserved3;
1318 __le64 phy_type_low;
1319 __le64 phy_type_high;
1320};
1321
1322
1323struct ice_aqc_set_event_mask {
1324 u8 lport_num;
1325 u8 reserved[7];
1326 __le16 event_mask;
1327#define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1328#define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1329#define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1330#define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1331#define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1332#define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1333#define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1334#define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1335#define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1336#define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12)
1337 u8 reserved1[6];
1338};
1339
1340
1341struct ice_aqc_set_mac_lb {
1342 u8 lb_mode;
1343#define ICE_AQ_MAC_LB_EN BIT(0)
1344#define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1345 u8 reserved[15];
1346};
1347
1348struct ice_aqc_link_topo_params {
1349 u8 lport_num;
1350 u8 lport_num_valid;
1351#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1352 u8 node_type_ctx;
1353#define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1354#define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1355#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1356#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
1357#define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1358#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
1359#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
1360#define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
1361#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
1362#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
1363#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
1364#define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
1365#define ICE_AQC_LINK_TOPO_NODE_CTX_M \
1366 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1367#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1368#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
1369#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1370#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
1371#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
1372#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
1373 u8 index;
1374};
1375
1376struct ice_aqc_link_topo_addr {
1377 struct ice_aqc_link_topo_params topo_params;
1378 __le16 handle;
1379#define ICE_AQC_LINK_TOPO_HANDLE_S 0
1380#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1381
1382#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1383#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
1384#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
1385#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1386
1387#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
1388 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1389#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
1390#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1391
1392#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
1393 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1394};
1395
1396
1397struct ice_aqc_get_link_topo {
1398 struct ice_aqc_link_topo_addr addr;
1399 u8 node_part_num;
1400#define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
1401 u8 rsvd[9];
1402};
1403
1404
1405struct ice_aqc_i2c {
1406 struct ice_aqc_link_topo_addr topo_addr;
1407 __le16 i2c_addr;
1408 u8 i2c_params;
1409#define ICE_AQC_I2C_DATA_SIZE_M GENMASK(3, 0)
1410#define ICE_AQC_I2C_USE_REPEATED_START BIT(7)
1411
1412 u8 rsvd;
1413 __le16 i2c_bus_addr;
1414 u8 rsvd2[4];
1415};
1416
1417
1418struct ice_aqc_read_i2c_resp {
1419 u8 i2c_data[16];
1420};
1421
1422
1423struct ice_aqc_set_port_id_led {
1424 u8 lport_num;
1425 u8 lport_num_valid;
1426 u8 ident_mode;
1427#define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1428#define ICE_AQC_PORT_IDENT_LED_ORIG 0
1429 u8 rsvd[13];
1430};
1431
1432
1433struct ice_aqc_gpio {
1434 __le16 gpio_ctrl_handle;
1435#define ICE_AQC_GPIO_HANDLE_S 0
1436#define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S)
1437 u8 gpio_num;
1438 u8 gpio_val;
1439 u8 rsvd[12];
1440};
1441
1442
1443struct ice_aqc_sff_eeprom {
1444 u8 lport_num;
1445 u8 lport_num_valid;
1446#define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1447 __le16 i2c_bus_addr;
1448#define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1449#define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1450#define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1451#define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1452#define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1453#define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1454#define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1455#define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1456#define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1457#define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1458#define ICE_AQC_SFF_IS_WRITE BIT(15)
1459 __le16 i2c_mem_addr;
1460 __le16 eeprom_page;
1461#define ICE_AQC_SFF_EEPROM_BANK_S 0
1462#define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1463#define ICE_AQC_SFF_EEPROM_PAGE_S 8
1464#define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1465 __le32 addr_high;
1466 __le32 addr_low;
1467};
1468
1469
1470
1471
1472
1473struct ice_aqc_nvm {
1474#define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
1475 __le16 offset_low;
1476 u8 offset_high;
1477 u8 cmd_flags;
1478#define ICE_AQC_NVM_LAST_CMD BIT(0)
1479#define ICE_AQC_NVM_PCIR_REQ BIT(0)
1480#define ICE_AQC_NVM_PRESERVATION_S 1
1481#define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1482#define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1483#define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1484#define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1485#define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1486#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3)
1487#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
1488#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
1489#define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
1490#define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6)
1491#define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3)
1492#define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1493#define ICE_AQC_NVM_RESET_LVL_M ICE_M(0x3, 0)
1494#define ICE_AQC_NVM_POR_FLAG 0
1495#define ICE_AQC_NVM_PERST_FLAG 1
1496#define ICE_AQC_NVM_EMPR_FLAG 2
1497#define ICE_AQC_NVM_EMPR_ENA BIT(0)
1498 __le16 module_typeid;
1499 __le16 length;
1500#define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1501 __le32 addr_high;
1502 __le32 addr_low;
1503};
1504
1505#define ICE_AQC_NVM_START_POINT 0
1506
1507
1508struct ice_aqc_nvm_checksum {
1509 u8 flags;
1510#define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1511#define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1512 u8 rsvd;
1513 __le16 checksum;
1514#define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1515 u8 rsvd2[12];
1516};
1517
1518
1519struct ice_aqc_nvm_pkg_data {
1520 u8 reserved[3];
1521 u8 cmd_flags;
1522#define ICE_AQC_NVM_PKG_DELETE BIT(0)
1523#define ICE_AQC_NVM_PKG_SKIPPED BIT(0)
1524
1525 u32 reserved1;
1526 __le32 addr_high;
1527 __le32 addr_low;
1528};
1529
1530
1531struct ice_aqc_nvm_pass_comp_tbl {
1532 u8 component_response;
1533#define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0
1534#define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1
1535#define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2
1536 u8 component_response_code;
1537#define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0
1538#define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1
1539#define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2
1540#define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3
1541#define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4
1542#define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5
1543#define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6
1544#define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7
1545#define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8
1546#define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA
1547#define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB
1548 u8 reserved;
1549 u8 transfer_flag;
1550#define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1
1551#define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2
1552#define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4
1553#define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5
1554 __le32 reserved1;
1555 __le32 addr_high;
1556 __le32 addr_low;
1557};
1558
1559struct ice_aqc_nvm_comp_tbl {
1560 __le16 comp_class;
1561#define NVM_COMP_CLASS_ALL_FW 0x000A
1562
1563 __le16 comp_id;
1564#define NVM_COMP_ID_OROM 0x5
1565#define NVM_COMP_ID_NVM 0x6
1566#define NVM_COMP_ID_NETLIST 0x8
1567
1568 u8 comp_class_idx;
1569#define FWU_COMP_CLASS_IDX_NOT_USE 0x0
1570
1571 __le32 comp_cmp_stamp;
1572 u8 cvs_type;
1573#define NVM_CVS_TYPE_ASCII 0x1
1574
1575 u8 cvs_len;
1576 u8 cvs[];
1577} __packed;
1578
1579
1580
1581
1582
1583
1584struct ice_aqc_pf_vf_msg {
1585 __le32 id;
1586 u32 reserved;
1587 __le32 addr_high;
1588 __le32 addr_low;
1589};
1590
1591
1592
1593
1594
1595struct ice_aqc_lldp_get_mib {
1596 u8 type;
1597#define ICE_AQ_LLDP_MIB_TYPE_S 0
1598#define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1599#define ICE_AQ_LLDP_MIB_LOCAL 0
1600#define ICE_AQ_LLDP_MIB_REMOTE 1
1601#define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1602#define ICE_AQ_LLDP_BRID_TYPE_S 2
1603#define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1604#define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1605#define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1606
1607#define ICE_AQ_LLDP_TX_S 0x4
1608#define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1609#define ICE_AQ_LLDP_TX_ACTIVE 0
1610#define ICE_AQ_LLDP_TX_SUSPENDED 1
1611#define ICE_AQ_LLDP_TX_FLUSHED 3
1612
1613
1614
1615
1616 u8 reserved1;
1617 __le16 local_len;
1618 __le16 remote_len;
1619 u8 reserved2[2];
1620 __le32 addr_high;
1621 __le32 addr_low;
1622};
1623
1624
1625
1626struct ice_aqc_lldp_set_mib_change {
1627 u8 command;
1628#define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1629#define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1630 u8 reserved[15];
1631};
1632
1633
1634struct ice_aqc_lldp_stop {
1635 u8 command;
1636#define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1637#define ICE_AQ_LLDP_AGENT_STOP 0x0
1638#define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1639#define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1640 u8 reserved[15];
1641};
1642
1643
1644struct ice_aqc_lldp_start {
1645 u8 command;
1646#define ICE_AQ_LLDP_AGENT_START BIT(0)
1647#define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1648 u8 reserved[15];
1649};
1650
1651
1652
1653
1654
1655struct ice_aqc_get_cee_dcb_cfg_resp {
1656 u8 oper_num_tc;
1657 u8 oper_prio_tc[4];
1658 u8 oper_tc_bw[8];
1659 u8 oper_pfc_en;
1660 __le16 oper_app_prio;
1661#define ICE_AQC_CEE_APP_FCOE_S 0
1662#define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1663#define ICE_AQC_CEE_APP_ISCSI_S 3
1664#define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1665#define ICE_AQC_CEE_APP_FIP_S 8
1666#define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1667 __le32 tlv_status;
1668#define ICE_AQC_CEE_PG_STATUS_S 0
1669#define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1670#define ICE_AQC_CEE_PFC_STATUS_S 3
1671#define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1672#define ICE_AQC_CEE_FCOE_STATUS_S 8
1673#define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1674#define ICE_AQC_CEE_ISCSI_STATUS_S 11
1675#define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1676#define ICE_AQC_CEE_FIP_STATUS_S 16
1677#define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1678 u8 reserved[12];
1679};
1680
1681
1682
1683
1684struct ice_aqc_lldp_set_local_mib {
1685 u8 type;
1686#define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1687#define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1688#define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1689#define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1690#define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1691 u8 reserved0;
1692 __le16 length;
1693 u8 reserved1[4];
1694 __le32 addr_high;
1695 __le32 addr_low;
1696};
1697
1698
1699
1700
1701
1702
1703struct ice_aqc_lldp_stop_start_specific_agent {
1704 u8 command;
1705#define ICE_AQC_START_STOP_AGENT_M BIT(0)
1706#define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1707#define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1708 u8 reserved[15];
1709};
1710
1711
1712struct ice_aqc_lldp_filter_ctrl {
1713 u8 cmd_flags;
1714#define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0
1715#define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1
1716 u8 reserved1;
1717 __le16 vsi_num;
1718 u8 reserved2[12];
1719};
1720
1721
1722struct ice_aqc_get_set_rss_key {
1723#define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1724#define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1725#define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1726 __le16 vsi_id;
1727 u8 reserved[6];
1728 __le32 addr_high;
1729 __le32 addr_low;
1730};
1731
1732#define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1733#define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1734#define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1735 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1736 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1737
1738struct ice_aqc_get_set_rss_keys {
1739 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1740 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1741};
1742
1743
1744struct ice_aqc_get_set_rss_lut {
1745#define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1746#define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1747#define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1748 __le16 vsi_id;
1749#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1750#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1751 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1752
1753#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1754#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1755#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1756
1757#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1758#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1759 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1760
1761#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1762#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1763#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1764#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1765#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1766#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1767
1768#define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1769#define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1770 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1771
1772 __le16 flags;
1773 __le32 reserved;
1774 __le32 addr_high;
1775 __le32 addr_low;
1776};
1777
1778
1779
1780struct ice_aqc_neigh_dev_req {
1781 __le16 sb_data_len;
1782 u8 reserved[6];
1783 __le32 addr_high;
1784 __le32 addr_low;
1785};
1786
1787
1788struct ice_aqc_add_txqs {
1789 u8 num_qgrps;
1790 u8 reserved[3];
1791 __le32 reserved1;
1792 __le32 addr_high;
1793 __le32 addr_low;
1794};
1795
1796
1797
1798
1799struct ice_aqc_add_txqs_perq {
1800 __le16 txq_id;
1801 u8 rsvd[2];
1802 __le32 q_teid;
1803 u8 txq_ctx[22];
1804 u8 rsvd2[2];
1805 struct ice_aqc_txsched_elem info;
1806};
1807
1808
1809
1810
1811
1812
1813struct ice_aqc_add_tx_qgrp {
1814 __le32 parent_teid;
1815 u8 num_txqs;
1816 u8 rsvd[3];
1817 struct ice_aqc_add_txqs_perq txqs[];
1818};
1819
1820
1821struct ice_aqc_dis_txqs {
1822 u8 cmd_type;
1823#define ICE_AQC_Q_DIS_CMD_S 0
1824#define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1825#define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1826#define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1827#define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1828#define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1829#define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
1830#define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
1831 u8 num_entries;
1832 __le16 vmvf_and_timeout;
1833#define ICE_AQC_Q_DIS_VMVF_NUM_S 0
1834#define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1835#define ICE_AQC_Q_DIS_TIMEOUT_S 10
1836#define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1837 __le32 blocked_cgds;
1838 __le32 addr_high;
1839 __le32 addr_low;
1840};
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850struct ice_aqc_dis_txq_item {
1851 __le32 parent_teid;
1852 u8 num_qs;
1853 u8 rsvd;
1854
1855#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1856#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1857 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1858#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1859 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1860 __le16 q_id[];
1861} __packed;
1862
1863
1864struct ice_aqc_add_rdma_qset {
1865 u8 num_qset_grps;
1866 u8 reserved[7];
1867 __le32 addr_high;
1868 __le32 addr_low;
1869};
1870
1871
1872
1873
1874struct ice_aqc_add_tx_rdma_qset_entry {
1875 __le16 tx_qset_id;
1876 u8 rsvd[2];
1877 __le32 qset_teid;
1878 struct ice_aqc_txsched_elem info;
1879};
1880
1881
1882
1883
1884
1885
1886struct ice_aqc_add_rdma_qset_data {
1887 __le32 parent_teid;
1888 __le16 num_qsets;
1889 u8 rsvd[2];
1890 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[];
1891};
1892
1893
1894
1895
1896
1897struct ice_aqc_fw_logging {
1898 u8 log_ctrl;
1899#define ICE_AQC_FW_LOG_AQ_EN BIT(0)
1900#define ICE_AQC_FW_LOG_UART_EN BIT(1)
1901 u8 rsvd0;
1902 u8 log_ctrl_valid;
1903#define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
1904#define ICE_AQC_FW_LOG_UART_VALID BIT(1)
1905 u8 rsvd1[5];
1906 __le32 addr_high;
1907 __le32 addr_low;
1908};
1909
1910enum ice_aqc_fw_logging_mod {
1911 ICE_AQC_FW_LOG_ID_GENERAL = 0,
1912 ICE_AQC_FW_LOG_ID_CTRL,
1913 ICE_AQC_FW_LOG_ID_LINK,
1914 ICE_AQC_FW_LOG_ID_LINK_TOPO,
1915 ICE_AQC_FW_LOG_ID_DNL,
1916 ICE_AQC_FW_LOG_ID_I2C,
1917 ICE_AQC_FW_LOG_ID_SDP,
1918 ICE_AQC_FW_LOG_ID_MDIO,
1919 ICE_AQC_FW_LOG_ID_ADMINQ,
1920 ICE_AQC_FW_LOG_ID_HDMA,
1921 ICE_AQC_FW_LOG_ID_LLDP,
1922 ICE_AQC_FW_LOG_ID_DCBX,
1923 ICE_AQC_FW_LOG_ID_DCB,
1924 ICE_AQC_FW_LOG_ID_NETPROXY,
1925 ICE_AQC_FW_LOG_ID_NVM,
1926 ICE_AQC_FW_LOG_ID_AUTH,
1927 ICE_AQC_FW_LOG_ID_VPD,
1928 ICE_AQC_FW_LOG_ID_IOSF,
1929 ICE_AQC_FW_LOG_ID_PARSER,
1930 ICE_AQC_FW_LOG_ID_SW,
1931 ICE_AQC_FW_LOG_ID_SCHEDULER,
1932 ICE_AQC_FW_LOG_ID_TXQ,
1933 ICE_AQC_FW_LOG_ID_RSVD,
1934 ICE_AQC_FW_LOG_ID_POST,
1935 ICE_AQC_FW_LOG_ID_WATCHDOG,
1936 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
1937 ICE_AQC_FW_LOG_ID_MNG,
1938 ICE_AQC_FW_LOG_ID_MAX,
1939};
1940
1941
1942#define ICE_AQC_FW_LOG_ID_S 0
1943#define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
1944
1945#define ICE_AQC_FW_LOG_CONF_SUCCESS 0
1946#define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12)
1947
1948#define ICE_AQC_FW_LOG_EN_S 12
1949#define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
1950#define ICE_AQC_FW_LOG_INFO_EN BIT(12)
1951#define ICE_AQC_FW_LOG_INIT_EN BIT(13)
1952#define ICE_AQC_FW_LOG_FLOW_EN BIT(14)
1953#define ICE_AQC_FW_LOG_ERR_EN BIT(15)
1954
1955
1956struct ice_aqc_get_clear_fw_log {
1957 u8 flags;
1958#define ICE_AQC_FW_LOG_CLEAR BIT(0)
1959#define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
1960 u8 rsvd1[7];
1961 __le32 addr_high;
1962 __le32 addr_low;
1963};
1964
1965
1966
1967struct ice_aqc_download_pkg {
1968 u8 flags;
1969#define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
1970 u8 reserved[3];
1971 __le32 reserved1;
1972 __le32 addr_high;
1973 __le32 addr_low;
1974};
1975
1976struct ice_aqc_download_pkg_resp {
1977 __le32 error_offset;
1978 __le32 error_info;
1979 __le32 addr_high;
1980 __le32 addr_low;
1981};
1982
1983
1984struct ice_aqc_get_pkg_info_list {
1985 __le32 reserved1;
1986 __le32 reserved2;
1987 __le32 addr_high;
1988 __le32 addr_low;
1989};
1990
1991
1992struct ice_pkg_ver {
1993 u8 major;
1994 u8 minor;
1995 u8 update;
1996 u8 draft;
1997};
1998
1999#define ICE_PKG_NAME_SIZE 32
2000#define ICE_SEG_ID_SIZE 28
2001#define ICE_SEG_NAME_SIZE 28
2002
2003struct ice_aqc_get_pkg_info {
2004 struct ice_pkg_ver ver;
2005 char name[ICE_SEG_NAME_SIZE];
2006 __le32 track_id;
2007 u8 is_in_nvm;
2008 u8 is_active;
2009 u8 is_active_at_boot;
2010 u8 is_modified;
2011};
2012
2013
2014struct ice_aqc_get_pkg_info_resp {
2015 __le32 count;
2016 struct ice_aqc_get_pkg_info pkg_info[];
2017};
2018
2019
2020struct ice_aqc_driver_shared_params {
2021 u8 set_or_get_op;
2022#define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)
2023#define ICE_AQC_DRIVER_PARAM_SET 0
2024#define ICE_AQC_DRIVER_PARAM_GET 1
2025 u8 param_indx;
2026#define ICE_AQC_DRIVER_PARAM_MAX_IDX 15
2027 u8 rsvd[2];
2028 __le32 param_val;
2029 __le32 addr_high;
2030 __le32 addr_low;
2031};
2032
2033enum ice_aqc_driver_params {
2034
2035 ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0 = 0,
2036
2037 ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1,
2038
2039
2040 ICE_AQC_DRIVER_PARAM_MAX = 16,
2041};
2042
2043
2044struct ice_aqc_event_lan_overflow {
2045 __le32 prtdcb_ruptq;
2046 __le32 qtx_ctl;
2047 u8 reserved[8];
2048};
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067struct ice_aq_desc {
2068 __le16 flags;
2069 __le16 opcode;
2070 __le16 datalen;
2071 __le16 retval;
2072 __le32 cookie_high;
2073 __le32 cookie_low;
2074 union {
2075 u8 raw[16];
2076 struct ice_aqc_generic generic;
2077 struct ice_aqc_get_ver get_ver;
2078 struct ice_aqc_driver_ver driver_ver;
2079 struct ice_aqc_q_shutdown q_shutdown;
2080 struct ice_aqc_req_res res_owner;
2081 struct ice_aqc_manage_mac_read mac_read;
2082 struct ice_aqc_manage_mac_write mac_write;
2083 struct ice_aqc_clear_pxe clear_pxe;
2084 struct ice_aqc_list_caps get_cap;
2085 struct ice_aqc_get_phy_caps get_phy;
2086 struct ice_aqc_set_phy_cfg set_phy;
2087 struct ice_aqc_restart_an restart_an;
2088 struct ice_aqc_gpio read_write_gpio;
2089 struct ice_aqc_sff_eeprom read_write_sff_param;
2090 struct ice_aqc_set_port_id_led set_port_id_led;
2091 struct ice_aqc_get_sw_cfg get_sw_conf;
2092 struct ice_aqc_set_port_params set_port_params;
2093 struct ice_aqc_sw_rules sw_rules;
2094 struct ice_aqc_add_get_recipe add_get_recipe;
2095 struct ice_aqc_recipe_to_profile recipe_to_profile;
2096 struct ice_aqc_get_topo get_topo;
2097 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2098 struct ice_aqc_query_txsched_res query_sched_res;
2099 struct ice_aqc_query_port_ets port_ets;
2100 struct ice_aqc_rl_profile rl_profile;
2101 struct ice_aqc_nvm nvm;
2102 struct ice_aqc_nvm_checksum nvm_checksum;
2103 struct ice_aqc_nvm_pkg_data pkg_data;
2104 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl;
2105 struct ice_aqc_pf_vf_msg virt;
2106 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2107 struct ice_aqc_lldp_get_mib lldp_get_mib;
2108 struct ice_aqc_lldp_set_mib_change lldp_set_event;
2109 struct ice_aqc_lldp_stop lldp_stop;
2110 struct ice_aqc_lldp_start lldp_start;
2111 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2112 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2113 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
2114 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2115 struct ice_aqc_get_set_rss_key get_set_rss_key;
2116 struct ice_aqc_neigh_dev_req neigh_dev;
2117 struct ice_aqc_add_txqs add_txqs;
2118 struct ice_aqc_dis_txqs dis_txqs;
2119 struct ice_aqc_add_rdma_qset add_rdma_qset;
2120 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2121 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2122 struct ice_aqc_fw_logging fw_logging;
2123 struct ice_aqc_get_clear_fw_log get_clear_fw_log;
2124 struct ice_aqc_download_pkg download_pkg;
2125 struct ice_aqc_driver_shared_params drv_shared_params;
2126 struct ice_aqc_set_mac_lb set_mac_lb;
2127 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2128 struct ice_aqc_set_mac_cfg set_mac_cfg;
2129 struct ice_aqc_set_event_mask set_event_mask;
2130 struct ice_aqc_get_link_status get_link_status;
2131 struct ice_aqc_event_lan_overflow lan_overflow;
2132 struct ice_aqc_get_link_topo get_link_topo;
2133 struct ice_aqc_i2c read_i2c;
2134 struct ice_aqc_read_i2c_resp read_i2c_resp;
2135 } params;
2136};
2137
2138
2139#define ICE_AQ_LG_BUF 512
2140
2141#define ICE_AQ_FLAG_ERR_S 2
2142#define ICE_AQ_FLAG_LB_S 9
2143#define ICE_AQ_FLAG_RD_S 10
2144#define ICE_AQ_FLAG_BUF_S 12
2145#define ICE_AQ_FLAG_SI_S 13
2146
2147#define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S)
2148#define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S)
2149#define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S)
2150#define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S)
2151#define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S)
2152
2153
2154enum ice_aq_err {
2155 ICE_AQ_RC_OK = 0,
2156 ICE_AQ_RC_EPERM = 1,
2157 ICE_AQ_RC_ENOENT = 2,
2158 ICE_AQ_RC_ENOMEM = 9,
2159 ICE_AQ_RC_EBUSY = 12,
2160 ICE_AQ_RC_EEXIST = 13,
2161 ICE_AQ_RC_EINVAL = 14,
2162 ICE_AQ_RC_ENOSPC = 16,
2163 ICE_AQ_RC_ENOSYS = 17,
2164 ICE_AQ_RC_EMODE = 21,
2165 ICE_AQ_RC_ENOSEC = 24,
2166 ICE_AQ_RC_EBADSIG = 25,
2167 ICE_AQ_RC_ESVN = 26,
2168 ICE_AQ_RC_EBADMAN = 27,
2169 ICE_AQ_RC_EBADBUF = 28,
2170};
2171
2172
2173enum ice_adminq_opc {
2174
2175 ice_aqc_opc_get_ver = 0x0001,
2176 ice_aqc_opc_driver_ver = 0x0002,
2177 ice_aqc_opc_q_shutdown = 0x0003,
2178
2179
2180 ice_aqc_opc_req_res = 0x0008,
2181 ice_aqc_opc_release_res = 0x0009,
2182
2183
2184 ice_aqc_opc_list_func_caps = 0x000A,
2185 ice_aqc_opc_list_dev_caps = 0x000B,
2186
2187
2188 ice_aqc_opc_manage_mac_read = 0x0107,
2189 ice_aqc_opc_manage_mac_write = 0x0108,
2190
2191
2192 ice_aqc_opc_clear_pxe_mode = 0x0110,
2193
2194
2195 ice_aqc_opc_get_sw_cfg = 0x0200,
2196 ice_aqc_opc_set_port_params = 0x0203,
2197
2198
2199 ice_aqc_opc_alloc_res = 0x0208,
2200 ice_aqc_opc_free_res = 0x0209,
2201 ice_aqc_opc_set_vlan_mode_parameters = 0x020C,
2202 ice_aqc_opc_get_vlan_mode_parameters = 0x020D,
2203
2204
2205 ice_aqc_opc_add_vsi = 0x0210,
2206 ice_aqc_opc_update_vsi = 0x0211,
2207 ice_aqc_opc_free_vsi = 0x0213,
2208
2209
2210 ice_aqc_opc_add_recipe = 0x0290,
2211 ice_aqc_opc_recipe_to_profile = 0x0291,
2212 ice_aqc_opc_get_recipe = 0x0292,
2213 ice_aqc_opc_get_recipe_to_profile = 0x0293,
2214
2215
2216 ice_aqc_opc_add_sw_rules = 0x02A0,
2217 ice_aqc_opc_update_sw_rules = 0x02A1,
2218 ice_aqc_opc_remove_sw_rules = 0x02A2,
2219
2220 ice_aqc_opc_clear_pf_cfg = 0x02A4,
2221
2222
2223 ice_aqc_opc_query_pfc_mode = 0x0302,
2224 ice_aqc_opc_set_pfc_mode = 0x0303,
2225
2226
2227 ice_aqc_opc_get_dflt_topo = 0x0400,
2228 ice_aqc_opc_add_sched_elems = 0x0401,
2229 ice_aqc_opc_cfg_sched_elems = 0x0403,
2230 ice_aqc_opc_get_sched_elems = 0x0404,
2231 ice_aqc_opc_move_sched_elems = 0x0408,
2232 ice_aqc_opc_suspend_sched_elems = 0x0409,
2233 ice_aqc_opc_resume_sched_elems = 0x040A,
2234 ice_aqc_opc_query_port_ets = 0x040E,
2235 ice_aqc_opc_delete_sched_elems = 0x040F,
2236 ice_aqc_opc_add_rl_profiles = 0x0410,
2237 ice_aqc_opc_query_sched_res = 0x0412,
2238 ice_aqc_opc_remove_rl_profiles = 0x0415,
2239
2240
2241 ice_aqc_opc_get_phy_caps = 0x0600,
2242 ice_aqc_opc_set_phy_cfg = 0x0601,
2243 ice_aqc_opc_set_mac_cfg = 0x0603,
2244 ice_aqc_opc_restart_an = 0x0605,
2245 ice_aqc_opc_get_link_status = 0x0607,
2246 ice_aqc_opc_set_event_mask = 0x0613,
2247 ice_aqc_opc_set_mac_lb = 0x0620,
2248 ice_aqc_opc_get_link_topo = 0x06E0,
2249 ice_aqc_opc_read_i2c = 0x06E2,
2250 ice_aqc_opc_set_port_id_led = 0x06E9,
2251 ice_aqc_opc_set_gpio = 0x06EC,
2252 ice_aqc_opc_get_gpio = 0x06ED,
2253 ice_aqc_opc_sff_eeprom = 0x06EE,
2254
2255
2256 ice_aqc_opc_nvm_read = 0x0701,
2257 ice_aqc_opc_nvm_erase = 0x0702,
2258 ice_aqc_opc_nvm_write = 0x0703,
2259 ice_aqc_opc_nvm_checksum = 0x0706,
2260 ice_aqc_opc_nvm_write_activate = 0x0707,
2261 ice_aqc_opc_nvm_update_empr = 0x0709,
2262 ice_aqc_opc_nvm_pkg_data = 0x070A,
2263 ice_aqc_opc_nvm_pass_component_tbl = 0x070B,
2264
2265
2266 ice_mbx_opc_send_msg_to_pf = 0x0801,
2267 ice_mbx_opc_send_msg_to_vf = 0x0802,
2268
2269 ice_aqc_opc_lldp_get_mib = 0x0A00,
2270 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
2271 ice_aqc_opc_lldp_stop = 0x0A05,
2272 ice_aqc_opc_lldp_start = 0x0A06,
2273 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
2274 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
2275 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
2276 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A,
2277
2278
2279 ice_aqc_opc_set_rss_key = 0x0B02,
2280 ice_aqc_opc_set_rss_lut = 0x0B03,
2281 ice_aqc_opc_get_rss_key = 0x0B04,
2282 ice_aqc_opc_get_rss_lut = 0x0B05,
2283
2284
2285 ice_aqc_opc_neighbour_device_request = 0x0C00,
2286
2287
2288 ice_aqc_opc_add_txqs = 0x0C30,
2289 ice_aqc_opc_dis_txqs = 0x0C31,
2290 ice_aqc_opc_add_rdma_qset = 0x0C33,
2291
2292
2293 ice_aqc_opc_download_pkg = 0x0C40,
2294 ice_aqc_opc_upload_section = 0x0C41,
2295 ice_aqc_opc_update_pkg = 0x0C42,
2296 ice_aqc_opc_get_pkg_info_list = 0x0C43,
2297
2298 ice_aqc_opc_driver_shared_params = 0x0C90,
2299
2300
2301 ice_aqc_opc_event_lan_overflow = 0x1001,
2302
2303
2304 ice_aqc_opc_fw_logging = 0xFF09,
2305 ice_aqc_opc_fw_logging_info = 0xFF10,
2306};
2307
2308#endif
2309