1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33#include <linux/highmem.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/interrupt.h>
42#include <linux/delay.h>
43#include <linux/mlx5/driver.h>
44#include <linux/mlx5/cq.h>
45#include <linux/mlx5/qp.h>
46#include <linux/debugfs.h>
47#include <linux/kmod.h>
48#include <linux/mlx5/mlx5_ifc.h>
49#include <linux/mlx5/vport.h>
50#ifdef CONFIG_RFS_ACCEL
51#include <linux/cpu_rmap.h>
52#endif
53#include <linux/version.h>
54#include <net/devlink.h>
55#include "mlx5_core.h"
56#include "lib/eq.h"
57#include "fs_core.h"
58#include "lib/mpfs.h"
59#include "eswitch.h"
60#include "devlink.h"
61#include "fw_reset.h"
62#include "lib/mlx5.h"
63#include "lib/tout.h"
64#include "fpga/core.h"
65#include "fpga/ipsec.h"
66#include "accel/ipsec.h"
67#include "accel/tls.h"
68#include "lib/clock.h"
69#include "lib/vxlan.h"
70#include "lib/geneve.h"
71#include "lib/devcom.h"
72#include "lib/pci_vsc.h"
73#include "diag/fw_tracer.h"
74#include "ecpf.h"
75#include "lib/hv_vhca.h"
76#include "diag/rsc_dump.h"
77#include "sf/vhca_event.h"
78#include "sf/dev/dev.h"
79#include "sf/sf.h"
80#include "mlx5_irq.h"
81
82MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
83MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
84MODULE_LICENSE("Dual BSD/GPL");
85
86unsigned int mlx5_core_debug_mask;
87module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
88MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
89
90static unsigned int prof_sel = MLX5_DEFAULT_PROF;
91module_param_named(prof_sel, prof_sel, uint, 0444);
92MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
93
94static u32 sw_owner_id[4];
95
96enum {
97 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
98 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
99};
100
101#define LOG_MAX_SUPPORTED_QPS 0xff
102
103static struct mlx5_profile profile[] = {
104 [0] = {
105 .mask = 0,
106 },
107 [1] = {
108 .mask = MLX5_PROF_MASK_QP_SIZE,
109 .log_max_qp = 12,
110 },
111 [2] = {
112 .mask = MLX5_PROF_MASK_QP_SIZE |
113 MLX5_PROF_MASK_MR_CACHE,
114 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
115 .mr_cache[0] = {
116 .size = 500,
117 .limit = 250
118 },
119 .mr_cache[1] = {
120 .size = 500,
121 .limit = 250
122 },
123 .mr_cache[2] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[3] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[4] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[5] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[6] = {
140 .size = 500,
141 .limit = 250
142 },
143 .mr_cache[7] = {
144 .size = 500,
145 .limit = 250
146 },
147 .mr_cache[8] = {
148 .size = 500,
149 .limit = 250
150 },
151 .mr_cache[9] = {
152 .size = 500,
153 .limit = 250
154 },
155 .mr_cache[10] = {
156 .size = 500,
157 .limit = 250
158 },
159 .mr_cache[11] = {
160 .size = 500,
161 .limit = 250
162 },
163 .mr_cache[12] = {
164 .size = 64,
165 .limit = 32
166 },
167 .mr_cache[13] = {
168 .size = 32,
169 .limit = 16
170 },
171 .mr_cache[14] = {
172 .size = 16,
173 .limit = 8
174 },
175 .mr_cache[15] = {
176 .size = 8,
177 .limit = 4
178 },
179 },
180};
181
182static int fw_initializing(struct mlx5_core_dev *dev)
183{
184 return ioread32be(&dev->iseg->initializing) >> 31;
185}
186
187static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
188 u32 warn_time_mili)
189{
190 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
191 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
192 int err = 0;
193
194 while (fw_initializing(dev)) {
195 if (time_after(jiffies, end)) {
196 err = -EBUSY;
197 break;
198 }
199 if (warn_time_mili && time_after(jiffies, warn)) {
200 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
201 jiffies_to_msecs(end - warn) / 1000);
202 warn = jiffies + msecs_to_jiffies(warn_time_mili);
203 }
204 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
205 }
206
207 return err;
208}
209
210static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
211{
212 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
213 driver_version);
214 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
215 int remaining_size = driver_ver_sz;
216 char *string;
217
218 if (!MLX5_CAP_GEN(dev, driver_version))
219 return;
220
221 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
222
223 strncpy(string, "Linux", remaining_size);
224
225 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
226 strncat(string, ",", remaining_size);
227
228 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
229 strncat(string, KBUILD_MODNAME, remaining_size);
230
231 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
232 strncat(string, ",", remaining_size);
233
234 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
235
236 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
237 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
238 LINUX_VERSION_SUBLEVEL);
239
240
241 MLX5_SET(set_driver_version_in, in, opcode,
242 MLX5_CMD_OP_SET_DRIVER_VERSION);
243
244 mlx5_cmd_exec_in(dev, set_driver_version, in);
245}
246
247static int set_dma_caps(struct pci_dev *pdev)
248{
249 int err;
250
251 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
252 if (err) {
253 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
254 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
255 if (err) {
256 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
257 return err;
258 }
259 }
260
261 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
262 return err;
263}
264
265static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
266{
267 struct pci_dev *pdev = dev->pdev;
268 int err = 0;
269
270 mutex_lock(&dev->pci_status_mutex);
271 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
272 err = pci_enable_device(pdev);
273 if (!err)
274 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
275 }
276 mutex_unlock(&dev->pci_status_mutex);
277
278 return err;
279}
280
281static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
282{
283 struct pci_dev *pdev = dev->pdev;
284
285 mutex_lock(&dev->pci_status_mutex);
286 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
287 pci_disable_device(pdev);
288 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
289 }
290 mutex_unlock(&dev->pci_status_mutex);
291}
292
293static int request_bar(struct pci_dev *pdev)
294{
295 int err = 0;
296
297 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
298 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
299 return -ENODEV;
300 }
301
302 err = pci_request_regions(pdev, KBUILD_MODNAME);
303 if (err)
304 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
305
306 return err;
307}
308
309static void release_bar(struct pci_dev *pdev)
310{
311 pci_release_regions(pdev);
312}
313
314struct mlx5_reg_host_endianness {
315 u8 he;
316 u8 rsvd[15];
317};
318
319#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
320
321enum {
322 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
323 MLX5_DEV_CAP_FLAG_DCT,
324};
325
326static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
327{
328 switch (size) {
329 case 128:
330 return 0;
331 case 256:
332 return 1;
333 case 512:
334 return 2;
335 case 1024:
336 return 3;
337 case 2048:
338 return 4;
339 case 4096:
340 return 5;
341 default:
342 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
343 return 0;
344 }
345}
346
347static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
348 enum mlx5_cap_type cap_type,
349 enum mlx5_cap_mode cap_mode)
350{
351 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
352 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
353 void *out, *hca_caps;
354 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
355 int err;
356
357 memset(in, 0, sizeof(in));
358 out = kzalloc(out_sz, GFP_KERNEL);
359 if (!out)
360 return -ENOMEM;
361
362 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
363 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
364 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
365 if (err) {
366 mlx5_core_warn(dev,
367 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
368 cap_type, cap_mode, err);
369 goto query_ex;
370 }
371
372 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
373
374 switch (cap_mode) {
375 case HCA_CAP_OPMOD_GET_MAX:
376 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
377 MLX5_UN_SZ_BYTES(hca_cap_union));
378 break;
379 case HCA_CAP_OPMOD_GET_CUR:
380 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
381 MLX5_UN_SZ_BYTES(hca_cap_union));
382 break;
383 default:
384 mlx5_core_warn(dev,
385 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
386 cap_type, cap_mode);
387 err = -EINVAL;
388 break;
389 }
390query_ex:
391 kfree(out);
392 return err;
393}
394
395int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
396{
397 int ret;
398
399 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
400 if (ret)
401 return ret;
402 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
403}
404
405static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
406{
407 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
408 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
409 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
410}
411
412static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
413{
414 void *set_hca_cap;
415 int req_endianness;
416 int err;
417
418 if (!MLX5_CAP_GEN(dev, atomic))
419 return 0;
420
421 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
422 if (err)
423 return err;
424
425 req_endianness =
426 MLX5_CAP_ATOMIC(dev,
427 supported_atomic_req_8B_endianness_mode_1);
428
429 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
430 return 0;
431
432 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
433
434
435 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
436 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
437
438 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
439}
440
441static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
442{
443 void *set_hca_cap;
444 bool do_set = false;
445 int err;
446
447 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
448 !MLX5_CAP_GEN(dev, pg))
449 return 0;
450
451 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
452 if (err)
453 return err;
454
455 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
456 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
457 MLX5_ST_SZ_BYTES(odp_cap));
458
459#define ODP_CAP_SET_MAX(dev, field) \
460 do { \
461 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
462 if (_res) { \
463 do_set = true; \
464 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
465 } \
466 } while (0)
467
468 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
469 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
470 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
471 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
472 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
473 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
474 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
475 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
476 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
477 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
478 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
479 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
480 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
481 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
482
483 if (!do_set)
484 return 0;
485
486 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
487}
488
489static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
490{
491 struct devlink *devlink = priv_to_devlink(dev);
492 union devlink_param_value val;
493 int err;
494
495 err = devlink_param_driverinit_value_get(devlink,
496 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
497 &val);
498 if (!err)
499 return val.vu32;
500 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
501 return err;
502}
503
504static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
505{
506 struct mlx5_profile *prof = &dev->profile;
507 void *set_hca_cap;
508 int max_uc_list;
509 int err;
510
511 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
512 if (err)
513 return err;
514
515 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
516 capability);
517 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
518 MLX5_ST_SZ_BYTES(cmd_hca_cap));
519
520 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
521 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
522 128);
523
524 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
525 to_fw_pkey_sz(dev, 128));
526
527
528 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
529 prof->log_max_qp = min_t(u8, 17, MLX5_CAP_GEN_MAX(dev, log_max_qp));
530 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
531 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
532 prof->log_max_qp,
533 MLX5_CAP_GEN_MAX(dev, log_max_qp));
534 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
535 }
536 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
537 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
538 prof->log_max_qp);
539
540
541 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
542
543
544
545
546 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
547 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
548
549 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
550
551 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
552 MLX5_SET(cmd_hca_cap,
553 set_hca_cap,
554 cache_line_128byte,
555 cache_line_size() >= 128 ? 1 : 0);
556
557 if (MLX5_CAP_GEN_MAX(dev, dct))
558 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
559
560 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
561 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
562
563 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
564 MLX5_SET(cmd_hca_cap,
565 set_hca_cap,
566 num_vhca_ports,
567 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
568
569 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
570 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
571
572 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
573 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
574
575 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
576
577 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
578 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
579 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
580
581 if (MLX5_CAP_GEN(dev, roce_rw_supported))
582 MLX5_SET(cmd_hca_cap, set_hca_cap, roce, mlx5_is_roce_init_enabled(dev));
583
584 max_uc_list = max_uc_list_get_devlink_param(dev);
585 if (max_uc_list > 0)
586 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
587 ilog2(max_uc_list));
588
589 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
590}
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
607{
608 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_init_enabled(dev)) ||
609 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
610}
611
612static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
613{
614 void *set_hca_cap;
615 int err;
616
617 if (is_roce_fw_disabled(dev))
618 return 0;
619
620 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
621 if (err)
622 return err;
623
624 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
625 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
626 return 0;
627
628 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
629 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
630 MLX5_ST_SZ_BYTES(roce_cap));
631 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
632
633 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
634 return err;
635}
636
637static int set_hca_cap(struct mlx5_core_dev *dev)
638{
639 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
640 void *set_ctx;
641 int err;
642
643 set_ctx = kzalloc(set_sz, GFP_KERNEL);
644 if (!set_ctx)
645 return -ENOMEM;
646
647 err = handle_hca_cap(dev, set_ctx);
648 if (err) {
649 mlx5_core_err(dev, "handle_hca_cap failed\n");
650 goto out;
651 }
652
653 memset(set_ctx, 0, set_sz);
654 err = handle_hca_cap_atomic(dev, set_ctx);
655 if (err) {
656 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
657 goto out;
658 }
659
660 memset(set_ctx, 0, set_sz);
661 err = handle_hca_cap_odp(dev, set_ctx);
662 if (err) {
663 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
664 goto out;
665 }
666
667 memset(set_ctx, 0, set_sz);
668 err = handle_hca_cap_roce(dev, set_ctx);
669 if (err) {
670 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
671 goto out;
672 }
673
674out:
675 kfree(set_ctx);
676 return err;
677}
678
679static int set_hca_ctrl(struct mlx5_core_dev *dev)
680{
681 struct mlx5_reg_host_endianness he_in;
682 struct mlx5_reg_host_endianness he_out;
683 int err;
684
685 if (!mlx5_core_is_pf(dev))
686 return 0;
687
688 memset(&he_in, 0, sizeof(he_in));
689 he_in.he = MLX5_SET_HOST_ENDIANNESS;
690 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
691 &he_out, sizeof(he_out),
692 MLX5_REG_HOST_ENDIANNESS, 0, 1);
693 return err;
694}
695
696static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
697{
698 int ret = 0;
699
700
701 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
702 ret = mlx5_nic_vport_update_local_lb(dev, false);
703
704 return ret;
705}
706
707int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
708{
709 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
710
711 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
712 MLX5_SET(enable_hca_in, in, function_id, func_id);
713 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
714 dev->caps.embedded_cpu);
715 return mlx5_cmd_exec_in(dev, enable_hca, in);
716}
717
718int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
719{
720 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
721
722 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
723 MLX5_SET(disable_hca_in, in, function_id, func_id);
724 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
725 dev->caps.embedded_cpu);
726 return mlx5_cmd_exec_in(dev, disable_hca, in);
727}
728
729static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
730{
731 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
732 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
733 u32 sup_issi;
734 int err;
735
736 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
737 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
738 if (err) {
739 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome);
740 u8 status = MLX5_GET(query_issi_out, query_out, status);
741
742 if (!status || syndrome == MLX5_DRIVER_SYND) {
743 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
744 err, status, syndrome);
745 return err;
746 }
747
748 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
749 dev->issi = 0;
750 return 0;
751 }
752
753 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
754
755 if (sup_issi & (1 << 1)) {
756 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
757
758 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
759 MLX5_SET(set_issi_in, set_in, current_issi, 1);
760 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
761 if (err) {
762 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
763 err);
764 return err;
765 }
766
767 dev->issi = 1;
768
769 return 0;
770 } else if (sup_issi & (1 << 0) || !sup_issi) {
771 return 0;
772 }
773
774 return -EOPNOTSUPP;
775}
776
777static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
778 const struct pci_device_id *id)
779{
780 int err = 0;
781
782 mutex_init(&dev->pci_status_mutex);
783 pci_set_drvdata(dev->pdev, dev);
784
785 dev->bar_addr = pci_resource_start(pdev, 0);
786
787 err = mlx5_pci_enable_device(dev);
788 if (err) {
789 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
790 return err;
791 }
792
793 err = request_bar(pdev);
794 if (err) {
795 mlx5_core_err(dev, "error requesting BARs, aborting\n");
796 goto err_disable;
797 }
798
799 pci_set_master(pdev);
800
801 err = set_dma_caps(pdev);
802 if (err) {
803 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
804 goto err_clr_master;
805 }
806
807 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
808 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
809 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
810 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
811
812 dev->iseg_base = dev->bar_addr;
813 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
814 if (!dev->iseg) {
815 err = -ENOMEM;
816 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
817 goto err_clr_master;
818 }
819
820 mlx5_pci_vsc_init(dev);
821 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
822 return 0;
823
824err_clr_master:
825 pci_clear_master(dev->pdev);
826 release_bar(dev->pdev);
827err_disable:
828 mlx5_pci_disable_device(dev);
829 return err;
830}
831
832static void mlx5_pci_close(struct mlx5_core_dev *dev)
833{
834
835
836
837
838 mlx5_drain_health_wq(dev);
839 iounmap(dev->iseg);
840 pci_clear_master(dev->pdev);
841 release_bar(dev->pdev);
842 mlx5_pci_disable_device(dev);
843}
844
845static int mlx5_init_once(struct mlx5_core_dev *dev)
846{
847 int err;
848
849 dev->priv.devcom = mlx5_devcom_register_device(dev);
850 if (IS_ERR(dev->priv.devcom))
851 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
852 dev->priv.devcom);
853
854 err = mlx5_query_board_id(dev);
855 if (err) {
856 mlx5_core_err(dev, "query board id failed\n");
857 goto err_devcom;
858 }
859
860 err = mlx5_irq_table_init(dev);
861 if (err) {
862 mlx5_core_err(dev, "failed to initialize irq table\n");
863 goto err_devcom;
864 }
865
866 err = mlx5_eq_table_init(dev);
867 if (err) {
868 mlx5_core_err(dev, "failed to initialize eq\n");
869 goto err_irq_cleanup;
870 }
871
872 err = mlx5_events_init(dev);
873 if (err) {
874 mlx5_core_err(dev, "failed to initialize events\n");
875 goto err_eq_cleanup;
876 }
877
878 err = mlx5_fw_reset_init(dev);
879 if (err) {
880 mlx5_core_err(dev, "failed to initialize fw reset events\n");
881 goto err_events_cleanup;
882 }
883
884 mlx5_cq_debugfs_init(dev);
885
886 mlx5_init_reserved_gids(dev);
887
888 mlx5_init_clock(dev);
889
890 dev->vxlan = mlx5_vxlan_create(dev);
891 dev->geneve = mlx5_geneve_create(dev);
892
893 err = mlx5_init_rl_table(dev);
894 if (err) {
895 mlx5_core_err(dev, "Failed to init rate limiting\n");
896 goto err_tables_cleanup;
897 }
898
899 err = mlx5_mpfs_init(dev);
900 if (err) {
901 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
902 goto err_rl_cleanup;
903 }
904
905 err = mlx5_sriov_init(dev);
906 if (err) {
907 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
908 goto err_mpfs_cleanup;
909 }
910
911 err = mlx5_eswitch_init(dev);
912 if (err) {
913 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
914 goto err_sriov_cleanup;
915 }
916
917 err = mlx5_fpga_init(dev);
918 if (err) {
919 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
920 goto err_eswitch_cleanup;
921 }
922
923 err = mlx5_vhca_event_init(dev);
924 if (err) {
925 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
926 goto err_fpga_cleanup;
927 }
928
929 err = mlx5_sf_hw_table_init(dev);
930 if (err) {
931 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
932 goto err_sf_hw_table_cleanup;
933 }
934
935 err = mlx5_sf_table_init(dev);
936 if (err) {
937 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
938 goto err_sf_table_cleanup;
939 }
940
941 err = mlx5_fs_core_alloc(dev);
942 if (err) {
943 mlx5_core_err(dev, "Failed to alloc flow steering\n");
944 goto err_fs;
945 }
946
947 dev->dm = mlx5_dm_create(dev);
948 if (IS_ERR(dev->dm))
949 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
950
951 dev->tracer = mlx5_fw_tracer_create(dev);
952 dev->hv_vhca = mlx5_hv_vhca_create(dev);
953 dev->rsc_dump = mlx5_rsc_dump_create(dev);
954
955 return 0;
956
957err_fs:
958 mlx5_sf_table_cleanup(dev);
959err_sf_table_cleanup:
960 mlx5_sf_hw_table_cleanup(dev);
961err_sf_hw_table_cleanup:
962 mlx5_vhca_event_cleanup(dev);
963err_fpga_cleanup:
964 mlx5_fpga_cleanup(dev);
965err_eswitch_cleanup:
966 mlx5_eswitch_cleanup(dev->priv.eswitch);
967err_sriov_cleanup:
968 mlx5_sriov_cleanup(dev);
969err_mpfs_cleanup:
970 mlx5_mpfs_cleanup(dev);
971err_rl_cleanup:
972 mlx5_cleanup_rl_table(dev);
973err_tables_cleanup:
974 mlx5_geneve_destroy(dev->geneve);
975 mlx5_vxlan_destroy(dev->vxlan);
976 mlx5_cq_debugfs_cleanup(dev);
977 mlx5_fw_reset_cleanup(dev);
978err_events_cleanup:
979 mlx5_events_cleanup(dev);
980err_eq_cleanup:
981 mlx5_eq_table_cleanup(dev);
982err_irq_cleanup:
983 mlx5_irq_table_cleanup(dev);
984err_devcom:
985 mlx5_devcom_unregister_device(dev->priv.devcom);
986
987 return err;
988}
989
990static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
991{
992 mlx5_rsc_dump_destroy(dev);
993 mlx5_hv_vhca_destroy(dev->hv_vhca);
994 mlx5_fw_tracer_destroy(dev->tracer);
995 mlx5_dm_cleanup(dev);
996 mlx5_fs_core_free(dev);
997 mlx5_sf_table_cleanup(dev);
998 mlx5_sf_hw_table_cleanup(dev);
999 mlx5_vhca_event_cleanup(dev);
1000 mlx5_fpga_cleanup(dev);
1001 mlx5_eswitch_cleanup(dev->priv.eswitch);
1002 mlx5_sriov_cleanup(dev);
1003 mlx5_mpfs_cleanup(dev);
1004 mlx5_cleanup_rl_table(dev);
1005 mlx5_geneve_destroy(dev->geneve);
1006 mlx5_vxlan_destroy(dev->vxlan);
1007 mlx5_cleanup_clock(dev);
1008 mlx5_cleanup_reserved_gids(dev);
1009 mlx5_cq_debugfs_cleanup(dev);
1010 mlx5_fw_reset_cleanup(dev);
1011 mlx5_events_cleanup(dev);
1012 mlx5_eq_table_cleanup(dev);
1013 mlx5_irq_table_cleanup(dev);
1014 mlx5_devcom_unregister_device(dev->priv.devcom);
1015}
1016
1017static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
1018{
1019 int err;
1020
1021 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1022 fw_rev_min(dev), fw_rev_sub(dev));
1023
1024
1025 if (mlx5_core_is_pf(dev))
1026 pcie_print_link_status(dev->pdev);
1027
1028 mlx5_tout_set_def_val(dev);
1029
1030
1031
1032 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT),
1033 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL));
1034 if (err) {
1035 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n",
1036 mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1037 return err;
1038 }
1039
1040 err = mlx5_cmd_init(dev);
1041 if (err) {
1042 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1043 return err;
1044 }
1045
1046 mlx5_tout_query_iseg(dev);
1047
1048 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0);
1049 if (err) {
1050 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n",
1051 mlx5_tout_ms(dev, FW_INIT));
1052 goto err_cmd_cleanup;
1053 }
1054
1055 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1056
1057 err = mlx5_core_enable_hca(dev, 0);
1058 if (err) {
1059 mlx5_core_err(dev, "enable hca failed\n");
1060 goto err_cmd_cleanup;
1061 }
1062
1063 err = mlx5_core_set_issi(dev);
1064 if (err) {
1065 mlx5_core_err(dev, "failed to set issi\n");
1066 goto err_disable_hca;
1067 }
1068
1069 err = mlx5_satisfy_startup_pages(dev, 1);
1070 if (err) {
1071 mlx5_core_err(dev, "failed to allocate boot pages\n");
1072 goto err_disable_hca;
1073 }
1074
1075 err = mlx5_tout_query_dtor(dev);
1076 if (err) {
1077 mlx5_core_err(dev, "failed to read dtor\n");
1078 goto reclaim_boot_pages;
1079 }
1080
1081 err = set_hca_ctrl(dev);
1082 if (err) {
1083 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1084 goto reclaim_boot_pages;
1085 }
1086
1087 err = set_hca_cap(dev);
1088 if (err) {
1089 mlx5_core_err(dev, "set_hca_cap failed\n");
1090 goto reclaim_boot_pages;
1091 }
1092
1093 err = mlx5_satisfy_startup_pages(dev, 0);
1094 if (err) {
1095 mlx5_core_err(dev, "failed to allocate init pages\n");
1096 goto reclaim_boot_pages;
1097 }
1098
1099 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1100 if (err) {
1101 mlx5_core_err(dev, "init hca failed\n");
1102 goto reclaim_boot_pages;
1103 }
1104
1105 mlx5_set_driver_version(dev);
1106
1107 err = mlx5_query_hca_caps(dev);
1108 if (err) {
1109 mlx5_core_err(dev, "query hca failed\n");
1110 goto reclaim_boot_pages;
1111 }
1112
1113 mlx5_start_health_poll(dev);
1114
1115 return 0;
1116
1117reclaim_boot_pages:
1118 mlx5_reclaim_startup_pages(dev);
1119err_disable_hca:
1120 mlx5_core_disable_hca(dev, 0);
1121err_cmd_cleanup:
1122 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1123 mlx5_cmd_cleanup(dev);
1124
1125 return err;
1126}
1127
1128static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1129{
1130 int err;
1131
1132 mlx5_stop_health_poll(dev, boot);
1133 err = mlx5_cmd_teardown_hca(dev);
1134 if (err) {
1135 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1136 return err;
1137 }
1138 mlx5_reclaim_startup_pages(dev);
1139 mlx5_core_disable_hca(dev, 0);
1140 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1141 mlx5_cmd_cleanup(dev);
1142
1143 return 0;
1144}
1145
1146static int mlx5_load(struct mlx5_core_dev *dev)
1147{
1148 int err;
1149
1150 dev->priv.uar = mlx5_get_uars_page(dev);
1151 if (IS_ERR(dev->priv.uar)) {
1152 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1153 err = PTR_ERR(dev->priv.uar);
1154 return err;
1155 }
1156
1157 mlx5_events_start(dev);
1158 mlx5_pagealloc_start(dev);
1159
1160 err = mlx5_irq_table_create(dev);
1161 if (err) {
1162 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1163 goto err_irq_table;
1164 }
1165
1166 err = mlx5_eq_table_create(dev);
1167 if (err) {
1168 mlx5_core_err(dev, "Failed to create EQs\n");
1169 goto err_eq_table;
1170 }
1171
1172 err = mlx5_fw_tracer_init(dev->tracer);
1173 if (err) {
1174 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1175 mlx5_fw_tracer_destroy(dev->tracer);
1176 dev->tracer = NULL;
1177 }
1178
1179 mlx5_fw_reset_events_start(dev);
1180 mlx5_hv_vhca_init(dev->hv_vhca);
1181
1182 err = mlx5_rsc_dump_init(dev);
1183 if (err) {
1184 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1185 mlx5_rsc_dump_destroy(dev);
1186 dev->rsc_dump = NULL;
1187 }
1188
1189 err = mlx5_fpga_device_start(dev);
1190 if (err) {
1191 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1192 goto err_fpga_start;
1193 }
1194
1195 mlx5_accel_ipsec_init(dev);
1196
1197 err = mlx5_accel_tls_init(dev);
1198 if (err) {
1199 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1200 goto err_tls_start;
1201 }
1202
1203 err = mlx5_fs_core_init(dev);
1204 if (err) {
1205 mlx5_core_err(dev, "Failed to init flow steering\n");
1206 goto err_fs;
1207 }
1208
1209 err = mlx5_core_set_hca_defaults(dev);
1210 if (err) {
1211 mlx5_core_err(dev, "Failed to set hca defaults\n");
1212 goto err_set_hca;
1213 }
1214
1215 mlx5_vhca_event_start(dev);
1216
1217 err = mlx5_sf_hw_table_create(dev);
1218 if (err) {
1219 mlx5_core_err(dev, "sf table create failed %d\n", err);
1220 goto err_vhca;
1221 }
1222
1223 err = mlx5_ec_init(dev);
1224 if (err) {
1225 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1226 goto err_ec;
1227 }
1228
1229 mlx5_lag_add_mdev(dev);
1230 err = mlx5_sriov_attach(dev);
1231 if (err) {
1232 mlx5_core_err(dev, "sriov init failed %d\n", err);
1233 goto err_sriov;
1234 }
1235
1236 mlx5_sf_dev_table_create(dev);
1237
1238 return 0;
1239
1240err_sriov:
1241 mlx5_lag_remove_mdev(dev);
1242 mlx5_ec_cleanup(dev);
1243err_ec:
1244 mlx5_sf_hw_table_destroy(dev);
1245err_vhca:
1246 mlx5_vhca_event_stop(dev);
1247err_set_hca:
1248 mlx5_fs_core_cleanup(dev);
1249err_fs:
1250 mlx5_accel_tls_cleanup(dev);
1251err_tls_start:
1252 mlx5_accel_ipsec_cleanup(dev);
1253 mlx5_fpga_device_stop(dev);
1254err_fpga_start:
1255 mlx5_rsc_dump_cleanup(dev);
1256 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1257 mlx5_fw_reset_events_stop(dev);
1258 mlx5_fw_tracer_cleanup(dev->tracer);
1259 mlx5_eq_table_destroy(dev);
1260err_eq_table:
1261 mlx5_irq_table_destroy(dev);
1262err_irq_table:
1263 mlx5_pagealloc_stop(dev);
1264 mlx5_events_stop(dev);
1265 mlx5_put_uars_page(dev, dev->priv.uar);
1266 return err;
1267}
1268
1269static void mlx5_unload(struct mlx5_core_dev *dev)
1270{
1271 mlx5_sf_dev_table_destroy(dev);
1272 mlx5_sriov_detach(dev);
1273 mlx5_lag_remove_mdev(dev);
1274 mlx5_ec_cleanup(dev);
1275 mlx5_sf_hw_table_destroy(dev);
1276 mlx5_vhca_event_stop(dev);
1277 mlx5_fs_core_cleanup(dev);
1278 mlx5_accel_ipsec_cleanup(dev);
1279 mlx5_accel_tls_cleanup(dev);
1280 mlx5_fpga_device_stop(dev);
1281 mlx5_rsc_dump_cleanup(dev);
1282 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1283 mlx5_fw_reset_events_stop(dev);
1284 mlx5_fw_tracer_cleanup(dev->tracer);
1285 mlx5_eq_table_destroy(dev);
1286 mlx5_irq_table_destroy(dev);
1287 mlx5_pagealloc_stop(dev);
1288 mlx5_events_stop(dev);
1289 mlx5_put_uars_page(dev, dev->priv.uar);
1290}
1291
1292int mlx5_init_one(struct mlx5_core_dev *dev)
1293{
1294 int err = 0;
1295
1296 mutex_lock(&dev->intf_state_mutex);
1297 dev->state = MLX5_DEVICE_STATE_UP;
1298
1299 err = mlx5_function_setup(dev, true);
1300 if (err)
1301 goto err_function;
1302
1303 err = mlx5_init_once(dev);
1304 if (err) {
1305 mlx5_core_err(dev, "sw objs init failed\n");
1306 goto function_teardown;
1307 }
1308
1309 err = mlx5_load(dev);
1310 if (err)
1311 goto err_load;
1312
1313 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1314
1315 err = mlx5_devlink_register(priv_to_devlink(dev));
1316 if (err)
1317 goto err_devlink_reg;
1318
1319 err = mlx5_register_device(dev);
1320 if (err)
1321 goto err_register;
1322
1323 mutex_unlock(&dev->intf_state_mutex);
1324 return 0;
1325
1326err_register:
1327 mlx5_devlink_unregister(priv_to_devlink(dev));
1328err_devlink_reg:
1329 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1330 mlx5_unload(dev);
1331err_load:
1332 mlx5_cleanup_once(dev);
1333function_teardown:
1334 mlx5_function_teardown(dev, true);
1335err_function:
1336 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1337 mutex_unlock(&dev->intf_state_mutex);
1338 return err;
1339}
1340
1341void mlx5_uninit_one(struct mlx5_core_dev *dev)
1342{
1343 mutex_lock(&dev->intf_state_mutex);
1344
1345 mlx5_unregister_device(dev);
1346 mlx5_devlink_unregister(priv_to_devlink(dev));
1347
1348 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1349 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1350 __func__);
1351 mlx5_cleanup_once(dev);
1352 goto out;
1353 }
1354
1355 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1356 mlx5_unload(dev);
1357 mlx5_cleanup_once(dev);
1358 mlx5_function_teardown(dev, true);
1359out:
1360 mutex_unlock(&dev->intf_state_mutex);
1361}
1362
1363int mlx5_load_one(struct mlx5_core_dev *dev)
1364{
1365 int err = 0;
1366
1367 mutex_lock(&dev->intf_state_mutex);
1368 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1369 mlx5_core_warn(dev, "interface is up, NOP\n");
1370 goto out;
1371 }
1372
1373 dev->state = MLX5_DEVICE_STATE_UP;
1374
1375 err = mlx5_function_setup(dev, false);
1376 if (err)
1377 goto err_function;
1378
1379 err = mlx5_load(dev);
1380 if (err)
1381 goto err_load;
1382
1383 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1384
1385 err = mlx5_attach_device(dev);
1386 if (err)
1387 goto err_attach;
1388
1389 mutex_unlock(&dev->intf_state_mutex);
1390 return 0;
1391
1392err_attach:
1393 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1394 mlx5_unload(dev);
1395err_load:
1396 mlx5_function_teardown(dev, false);
1397err_function:
1398 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1399out:
1400 mutex_unlock(&dev->intf_state_mutex);
1401 return err;
1402}
1403
1404void mlx5_unload_one(struct mlx5_core_dev *dev)
1405{
1406 mutex_lock(&dev->intf_state_mutex);
1407
1408 mlx5_detach_device(dev);
1409
1410 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1411 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1412 __func__);
1413 goto out;
1414 }
1415
1416 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1417 mlx5_unload(dev);
1418 mlx5_function_teardown(dev, false);
1419out:
1420 mutex_unlock(&dev->intf_state_mutex);
1421}
1422
1423static const int types[] = {
1424 MLX5_CAP_GENERAL,
1425 MLX5_CAP_GENERAL_2,
1426 MLX5_CAP_ETHERNET_OFFLOADS,
1427 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1428 MLX5_CAP_ODP,
1429 MLX5_CAP_ATOMIC,
1430 MLX5_CAP_ROCE,
1431 MLX5_CAP_IPOIB_OFFLOADS,
1432 MLX5_CAP_FLOW_TABLE,
1433 MLX5_CAP_ESWITCH_FLOW_TABLE,
1434 MLX5_CAP_ESWITCH,
1435 MLX5_CAP_VECTOR_CALC,
1436 MLX5_CAP_QOS,
1437 MLX5_CAP_DEBUG,
1438 MLX5_CAP_DEV_MEM,
1439 MLX5_CAP_DEV_EVENT,
1440 MLX5_CAP_TLS,
1441 MLX5_CAP_VDPA_EMULATION,
1442 MLX5_CAP_IPSEC,
1443 MLX5_CAP_PORT_SELECTION,
1444 MLX5_CAP_DEV_SHAMPO,
1445};
1446
1447static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1448{
1449 int type;
1450 int i;
1451
1452 for (i = 0; i < ARRAY_SIZE(types); i++) {
1453 type = types[i];
1454 kfree(dev->caps.hca[type]);
1455 }
1456}
1457
1458static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1459{
1460 struct mlx5_hca_cap *cap;
1461 int type;
1462 int i;
1463
1464 for (i = 0; i < ARRAY_SIZE(types); i++) {
1465 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1466 if (!cap)
1467 goto err;
1468 type = types[i];
1469 dev->caps.hca[type] = cap;
1470 }
1471
1472 return 0;
1473
1474err:
1475 mlx5_hca_caps_free(dev);
1476 return -ENOMEM;
1477}
1478
1479int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1480{
1481 struct mlx5_priv *priv = &dev->priv;
1482 int err;
1483
1484 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1485 INIT_LIST_HEAD(&priv->ctx_list);
1486 spin_lock_init(&priv->ctx_lock);
1487 mutex_init(&dev->intf_state_mutex);
1488
1489 mutex_init(&priv->bfregs.reg_head.lock);
1490 mutex_init(&priv->bfregs.wc_head.lock);
1491 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1492 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1493
1494 mutex_init(&priv->alloc_mutex);
1495 mutex_init(&priv->pgdir_mutex);
1496 INIT_LIST_HEAD(&priv->pgdir_list);
1497
1498 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1499 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device),
1500 mlx5_debugfs_root);
1501 INIT_LIST_HEAD(&priv->traps);
1502
1503 err = mlx5_tout_init(dev);
1504 if (err) {
1505 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1506 goto err_timeout_init;
1507 }
1508
1509 err = mlx5_health_init(dev);
1510 if (err)
1511 goto err_health_init;
1512
1513 err = mlx5_pagealloc_init(dev);
1514 if (err)
1515 goto err_pagealloc_init;
1516
1517 err = mlx5_adev_init(dev);
1518 if (err)
1519 goto err_adev_init;
1520
1521 err = mlx5_hca_caps_alloc(dev);
1522 if (err)
1523 goto err_hca_caps;
1524
1525 return 0;
1526
1527err_hca_caps:
1528 mlx5_adev_cleanup(dev);
1529err_adev_init:
1530 mlx5_pagealloc_cleanup(dev);
1531err_pagealloc_init:
1532 mlx5_health_cleanup(dev);
1533err_health_init:
1534 mlx5_tout_cleanup(dev);
1535err_timeout_init:
1536 debugfs_remove(dev->priv.dbg.dbg_root);
1537 mutex_destroy(&priv->pgdir_mutex);
1538 mutex_destroy(&priv->alloc_mutex);
1539 mutex_destroy(&priv->bfregs.wc_head.lock);
1540 mutex_destroy(&priv->bfregs.reg_head.lock);
1541 mutex_destroy(&dev->intf_state_mutex);
1542 return err;
1543}
1544
1545void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1546{
1547 struct mlx5_priv *priv = &dev->priv;
1548
1549 mlx5_hca_caps_free(dev);
1550 mlx5_adev_cleanup(dev);
1551 mlx5_pagealloc_cleanup(dev);
1552 mlx5_health_cleanup(dev);
1553 mlx5_tout_cleanup(dev);
1554 debugfs_remove_recursive(dev->priv.dbg.dbg_root);
1555 mutex_destroy(&priv->pgdir_mutex);
1556 mutex_destroy(&priv->alloc_mutex);
1557 mutex_destroy(&priv->bfregs.wc_head.lock);
1558 mutex_destroy(&priv->bfregs.reg_head.lock);
1559 mutex_destroy(&dev->intf_state_mutex);
1560}
1561
1562static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1563{
1564 struct mlx5_core_dev *dev;
1565 struct devlink *devlink;
1566 int err;
1567
1568 devlink = mlx5_devlink_alloc(&pdev->dev);
1569 if (!devlink) {
1570 dev_err(&pdev->dev, "devlink alloc failed\n");
1571 return -ENOMEM;
1572 }
1573
1574 dev = devlink_priv(devlink);
1575 dev->device = &pdev->dev;
1576 dev->pdev = pdev;
1577
1578 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1579 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1580
1581 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1582 if (dev->priv.adev_idx < 0) {
1583 err = dev->priv.adev_idx;
1584 goto adev_init_err;
1585 }
1586
1587 err = mlx5_mdev_init(dev, prof_sel);
1588 if (err)
1589 goto mdev_init_err;
1590
1591 err = mlx5_pci_init(dev, pdev, id);
1592 if (err) {
1593 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1594 err);
1595 goto pci_init_err;
1596 }
1597
1598 err = mlx5_init_one(dev);
1599 if (err) {
1600 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1601 err);
1602 goto err_init_one;
1603 }
1604
1605 err = mlx5_crdump_enable(dev);
1606 if (err)
1607 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1608
1609 pci_save_state(pdev);
1610 devlink_register(devlink);
1611 return 0;
1612
1613err_init_one:
1614 mlx5_pci_close(dev);
1615pci_init_err:
1616 mlx5_mdev_uninit(dev);
1617mdev_init_err:
1618 mlx5_adev_idx_free(dev->priv.adev_idx);
1619adev_init_err:
1620 mlx5_devlink_free(devlink);
1621
1622 return err;
1623}
1624
1625static void remove_one(struct pci_dev *pdev)
1626{
1627 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1628 struct devlink *devlink = priv_to_devlink(dev);
1629
1630
1631
1632
1633 mlx5_drain_fw_reset(dev);
1634 devlink_unregister(devlink);
1635 mlx5_sriov_disable(pdev);
1636 mlx5_crdump_disable(dev);
1637 mlx5_drain_health_wq(dev);
1638 mlx5_uninit_one(dev);
1639 mlx5_pci_close(dev);
1640 mlx5_mdev_uninit(dev);
1641 mlx5_adev_idx_free(dev->priv.adev_idx);
1642 mlx5_devlink_free(devlink);
1643}
1644
1645#define mlx5_pci_trace(dev, fmt, ...) ({ \
1646 struct mlx5_core_dev *__dev = (dev); \
1647 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
1648 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
1649 __dev->pci_status, ##__VA_ARGS__); \
1650})
1651
1652static const char *result2str(enum pci_ers_result result)
1653{
1654 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
1655 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
1656 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
1657 "unknown";
1658}
1659
1660static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1661 pci_channel_state_t state)
1662{
1663 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1664 enum pci_ers_result res;
1665
1666 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
1667
1668 mlx5_enter_error_state(dev, false);
1669 mlx5_error_sw_reset(dev);
1670 mlx5_unload_one(dev);
1671 mlx5_drain_health_wq(dev);
1672 mlx5_pci_disable_device(dev);
1673
1674 res = state == pci_channel_io_perm_failure ?
1675 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1676
1677 mlx5_pci_trace(dev, "Exit, result = %d, %s\n", res, result2str(res));
1678 return res;
1679}
1680
1681
1682
1683
1684static int wait_vital(struct pci_dev *pdev)
1685{
1686 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1687 struct mlx5_core_health *health = &dev->priv.health;
1688 const int niter = 100;
1689 u32 last_count = 0;
1690 u32 count;
1691 int i;
1692
1693 for (i = 0; i < niter; i++) {
1694 count = ioread32be(health->health_counter);
1695 if (count && count != 0xffffffff) {
1696 if (last_count && last_count != count) {
1697 mlx5_core_info(dev,
1698 "wait vital counter value 0x%x after %d iterations\n",
1699 count, i);
1700 return 0;
1701 }
1702 last_count = count;
1703 }
1704 msleep(50);
1705 }
1706
1707 return -ETIMEDOUT;
1708}
1709
1710static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1711{
1712 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
1713 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1714 int err;
1715
1716 mlx5_pci_trace(dev, "Enter\n");
1717
1718 err = mlx5_pci_enable_device(dev);
1719 if (err) {
1720 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1721 __func__, err);
1722 goto out;
1723 }
1724
1725 pci_set_master(pdev);
1726 pci_restore_state(pdev);
1727 pci_save_state(pdev);
1728
1729 err = wait_vital(pdev);
1730 if (err) {
1731 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
1732 __func__, err);
1733 goto out;
1734 }
1735
1736 res = PCI_ERS_RESULT_RECOVERED;
1737out:
1738 mlx5_pci_trace(dev, "Exit, err = %d, result = %d, %s\n", err, res, result2str(res));
1739 return res;
1740}
1741
1742static void mlx5_pci_resume(struct pci_dev *pdev)
1743{
1744 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1745 int err;
1746
1747 mlx5_pci_trace(dev, "Enter, loading driver..\n");
1748
1749 err = mlx5_load_one(dev);
1750
1751 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
1752 !err ? "recovered" : "Failed");
1753}
1754
1755static const struct pci_error_handlers mlx5_err_handler = {
1756 .error_detected = mlx5_pci_err_detected,
1757 .slot_reset = mlx5_pci_slot_reset,
1758 .resume = mlx5_pci_resume
1759};
1760
1761static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1762{
1763 bool fast_teardown = false, force_teardown = false;
1764 int ret = 1;
1765
1766 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1767 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1768
1769 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1770 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1771
1772 if (!fast_teardown && !force_teardown)
1773 return -EOPNOTSUPP;
1774
1775 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1776 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1777 return -EAGAIN;
1778 }
1779
1780
1781
1782
1783 mlx5_drain_health_wq(dev);
1784 mlx5_stop_health_poll(dev, false);
1785
1786 ret = mlx5_cmd_fast_teardown_hca(dev);
1787 if (!ret)
1788 goto succeed;
1789
1790 ret = mlx5_cmd_force_teardown_hca(dev);
1791 if (!ret)
1792 goto succeed;
1793
1794 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1795 mlx5_start_health_poll(dev);
1796 return ret;
1797
1798succeed:
1799 mlx5_enter_error_state(dev, true);
1800
1801
1802
1803
1804
1805
1806 mlx5_core_eq_free_irqs(dev);
1807
1808 return 0;
1809}
1810
1811static void shutdown(struct pci_dev *pdev)
1812{
1813 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1814 int err;
1815
1816 mlx5_core_info(dev, "Shutdown was called\n");
1817 err = mlx5_try_fast_unload(dev);
1818 if (err)
1819 mlx5_unload_one(dev);
1820 mlx5_pci_disable_device(dev);
1821}
1822
1823static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1824{
1825 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1826
1827 mlx5_unload_one(dev);
1828
1829 return 0;
1830}
1831
1832static int mlx5_resume(struct pci_dev *pdev)
1833{
1834 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1835
1836 return mlx5_load_one(dev);
1837}
1838
1839static const struct pci_device_id mlx5_core_pci_table[] = {
1840 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1841 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF},
1842 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1843 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF},
1844 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1845 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF},
1846 { PCI_VDEVICE(MELLANOX, 0x1017) },
1847 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF},
1848 { PCI_VDEVICE(MELLANOX, 0x1019) },
1849 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF},
1850 { PCI_VDEVICE(MELLANOX, 0x101b) },
1851 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF},
1852 { PCI_VDEVICE(MELLANOX, 0x101d) },
1853 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF},
1854 { PCI_VDEVICE(MELLANOX, 0x101f) },
1855 { PCI_VDEVICE(MELLANOX, 0x1021) },
1856 { PCI_VDEVICE(MELLANOX, 0x1023) },
1857 { PCI_VDEVICE(MELLANOX, 0xa2d2) },
1858 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF},
1859 { PCI_VDEVICE(MELLANOX, 0xa2d6) },
1860 { PCI_VDEVICE(MELLANOX, 0xa2dc) },
1861 { PCI_VDEVICE(MELLANOX, 0xa2df) },
1862 { 0, }
1863};
1864
1865MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1866
1867void mlx5_disable_device(struct mlx5_core_dev *dev)
1868{
1869 mlx5_error_sw_reset(dev);
1870 mlx5_unload_one(dev);
1871}
1872
1873int mlx5_recover_device(struct mlx5_core_dev *dev)
1874{
1875 if (!mlx5_core_is_sf(dev)) {
1876 mlx5_pci_disable_device(dev);
1877 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
1878 return -EIO;
1879 }
1880
1881 return mlx5_load_one(dev);
1882}
1883
1884static struct pci_driver mlx5_core_driver = {
1885 .name = KBUILD_MODNAME,
1886 .id_table = mlx5_core_pci_table,
1887 .probe = probe_one,
1888 .remove = remove_one,
1889 .suspend = mlx5_suspend,
1890 .resume = mlx5_resume,
1891 .shutdown = shutdown,
1892 .err_handler = &mlx5_err_handler,
1893 .sriov_configure = mlx5_core_sriov_configure,
1894 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
1895 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
1896};
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev)
1910 __acquires(&mdev->intf_state_mutex)
1911{
1912 struct mlx5_core_dev *mdev;
1913
1914 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver);
1915 if (IS_ERR(mdev))
1916 return NULL;
1917
1918 mutex_lock(&mdev->intf_state_mutex);
1919 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) {
1920 mutex_unlock(&mdev->intf_state_mutex);
1921 return NULL;
1922 }
1923
1924 return mdev;
1925}
1926EXPORT_SYMBOL(mlx5_vf_get_core_dev);
1927
1928
1929
1930
1931
1932
1933
1934
1935void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev)
1936 __releases(&mdev->intf_state_mutex)
1937{
1938 mutex_unlock(&mdev->intf_state_mutex);
1939}
1940EXPORT_SYMBOL(mlx5_vf_put_core_dev);
1941
1942static void mlx5_core_verify_params(void)
1943{
1944 if (prof_sel >= ARRAY_SIZE(profile)) {
1945 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1946 prof_sel,
1947 ARRAY_SIZE(profile) - 1,
1948 MLX5_DEFAULT_PROF);
1949 prof_sel = MLX5_DEFAULT_PROF;
1950 }
1951}
1952
1953static int __init init(void)
1954{
1955 int err;
1956
1957 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
1958 "mlx5_core name not in sync with kernel module name");
1959
1960 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1961
1962 mlx5_core_verify_params();
1963 mlx5_fpga_ipsec_build_fs_cmds();
1964 mlx5_register_debugfs();
1965
1966 err = pci_register_driver(&mlx5_core_driver);
1967 if (err)
1968 goto err_debug;
1969
1970 err = mlx5_sf_driver_register();
1971 if (err)
1972 goto err_sf;
1973
1974 err = mlx5e_init();
1975 if (err)
1976 goto err_en;
1977
1978 return 0;
1979
1980err_en:
1981 mlx5_sf_driver_unregister();
1982err_sf:
1983 pci_unregister_driver(&mlx5_core_driver);
1984err_debug:
1985 mlx5_unregister_debugfs();
1986 return err;
1987}
1988
1989static void __exit cleanup(void)
1990{
1991 mlx5e_cleanup();
1992 mlx5_sf_driver_unregister();
1993 pci_unregister_driver(&mlx5_core_driver);
1994 mlx5_unregister_debugfs();
1995}
1996
1997module_init(init);
1998module_exit(cleanup);
1999
