1/* SPDX-License-Identifier: GPL-2.0-only */ 2/**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2018 Solarflare Communications Inc. 5 * Copyright 2019-2020 Xilinx Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation, incorporated herein by reference. 10 */ 11 12#ifndef EFX_EF100_REGS_H 13#define EFX_EF100_REGS_H 14 15/* EF100 hardware architecture definitions have a name prefix following 16 * the format: 17 * 18 * E<type>_<min-rev><max-rev>_ 19 * 20 * The following <type> strings are used: 21 * 22 * MMIO register Host memory structure 23 * ------------------------------------------------------------- 24 * Address R 25 * Bitfield RF SF 26 * Enumerator FE SE 27 * 28 * <min-rev> is the first revision to which the definition applies: 29 * 30 * G: Riverhead 31 * 32 * If the definition has been changed or removed in later revisions 33 * then <max-rev> is the last revision to which the definition applies; 34 * otherwise it is "Z". 35 */ 36 37/************************************************************************** 38 * 39 * EF100 registers and descriptors 40 * 41 ************************************************************************** 42 */ 43 44/* HW_REV_ID_REG: Hardware revision info register */ 45#define ER_GZ_HW_REV_ID 0x00000000 46 47/* NIC_REV_ID: SoftNIC revision info register */ 48#define ER_GZ_NIC_REV_ID 0x00000004 49 50/* NIC_MAGIC: Signature register that should contain a well-known value */ 51#define ER_GZ_NIC_MAGIC 0x00000008 52#define ERF_GZ_NIC_MAGIC_LBN 0 53#define ERF_GZ_NIC_MAGIC_WIDTH 32 54#define EFE_GZ_NIC_MAGIC_EXPECTED 0xEF100FCB 55 56/* MC_SFT_STATUS: MC soft status */ 57#define ER_GZ_MC_SFT_STATUS 0x00000010 58#define ER_GZ_MC_SFT_STATUS_STEP 4 59#define ER_GZ_MC_SFT_STATUS_ROWS 2 60 61/* MC_DB_LWRD_REG: MC doorbell register, low word */ 62#define ER_GZ_MC_DB_LWRD 0x00000020 63 64/* MC_DB_HWRD_REG: MC doorbell register, high word */ 65#define ER_GZ_MC_DB_HWRD 0x00000024 66 67/* EVQ_INT_PRIME: Prime EVQ */ 68#define ER_GZ_EVQ_INT_PRIME 0x00000040 69#define ERF_GZ_IDX_LBN 16 70#define ERF_GZ_IDX_WIDTH 16 71#define ERF_GZ_EVQ_ID_LBN 0 72#define ERF_GZ_EVQ_ID_WIDTH 16 73 74/* INT_AGG_RING_PRIME: Prime interrupt aggregation ring. */ 75#define ER_GZ_INT_AGG_RING_PRIME 0x00000048 76/* defined as ERF_GZ_IDX_LBN 16; access=WO reset=0x0 */ 77/* defined as ERF_GZ_IDX_WIDTH 16 */ 78#define ERF_GZ_RING_ID_LBN 0 79#define ERF_GZ_RING_ID_WIDTH 16 80 81/* EVQ_TMR: EVQ timer control */ 82#define ER_GZ_EVQ_TMR 0x00000104 83#define ER_GZ_EVQ_TMR_STEP 65536 84#define ER_GZ_EVQ_TMR_ROWS 1024 85 86/* EVQ_UNSOL_CREDIT_GRANT_SEQ: Grant credits for unsolicited events. */ 87#define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ 0x00000108 88#define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_STEP 65536 89#define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_ROWS 1024 90 91/* EVQ_DESC_CREDIT_GRANT_SEQ: Grant credits for descriptor proxy events. */ 92#define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ 0x00000110 93#define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_STEP 65536 94#define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_ROWS 1024 95 96/* RX_RING_DOORBELL: Ring Rx doorbell. */ 97#define ER_GZ_RX_RING_DOORBELL 0x00000180 98#define ER_GZ_RX_RING_DOORBELL_STEP 65536 99#define ER_GZ_RX_RING_DOORBELL_ROWS 1024 100#define ERF_GZ_RX_RING_PIDX_LBN 16 101#define ERF_GZ_RX_RING_PIDX_WIDTH 16 102 103/* TX_RING_DOORBELL: Ring Tx doorbell. */ 104#define ER_GZ_TX_RING_DOORBELL 0x00000200 105#define ER_GZ_TX_RING_DOORBELL_STEP 65536 106#define ER_GZ_TX_RING_DOORBELL_ROWS 1024 107#define ERF_GZ_TX_RING_PIDX_LBN 16 108#define ERF_GZ_TX_RING_PIDX_WIDTH 16 109 110/* TX_DESC_PUSH: Tx ring descriptor push. Reserved for future use. */ 111#define ER_GZ_TX_DESC_PUSH 0x00000210 112#define ER_GZ_TX_DESC_PUSH_STEP 65536 113#define ER_GZ_TX_DESC_PUSH_ROWS 1024 114 115/* THE_TIME: NIC hardware time */ 116#define ER_GZ_THE_TIME 0x00000280 117#define ER_GZ_THE_TIME_STEP 65536 118#define ER_GZ_THE_TIME_ROWS 1024 119#define ERF_GZ_THE_TIME_SECS_LBN 32 120#define ERF_GZ_THE_TIME_SECS_WIDTH 32 121#define ERF_GZ_THE_TIME_NANOS_LBN 2 122#define ERF_GZ_THE_TIME_NANOS_WIDTH 30 123#define ERF_GZ_THE_TIME_CLOCK_IN_SYNC_LBN 1 124#define ERF_GZ_THE_TIME_CLOCK_IN_SYNC_WIDTH 1 125#define ERF_GZ_THE_TIME_CLOCK_IS_SET_LBN 0 126#define ERF_GZ_THE_TIME_CLOCK_IS_SET_WIDTH 1 127 128/* PARAMS_TLV_LEN: Size of design parameters area in bytes */ 129#define ER_GZ_PARAMS_TLV_LEN 0x00000c00 130#define ER_GZ_PARAMS_TLV_LEN_STEP 65536 131#define ER_GZ_PARAMS_TLV_LEN_ROWS 1024 132 133/* PARAMS_TLV: Design parameters */ 134#define ER_GZ_PARAMS_TLV 0x00000c04 135#define ER_GZ_PARAMS_TLV_STEP 65536 136#define ER_GZ_PARAMS_TLV_ROWS 1024 137 138/* EW_EMBEDDED_EVENT */ 139#define ESF_GZ_EV_256_EVENT_LBN 0 140#define ESF_GZ_EV_256_EVENT_WIDTH 64 141#define ESE_GZ_EW_EMBEDDED_EVENT_STRUCT_SIZE 64 142 143/* NMMU_PAGESZ_2M_ADDR */ 144#define ESF_GZ_NMMU_2M_PAGE_SIZE_ID_LBN 59 145#define ESF_GZ_NMMU_2M_PAGE_SIZE_ID_WIDTH 5 146#define ESE_GZ_NMMU_PAGE_SIZE_2M 9 147#define ESF_GZ_NMMU_2M_PAGE_ID_LBN 21 148#define ESF_GZ_NMMU_2M_PAGE_ID_WIDTH 38 149#define ESF_GZ_NMMU_2M_PAGE_OFFSET_LBN 0 150#define ESF_GZ_NMMU_2M_PAGE_OFFSET_WIDTH 21 151#define ESE_GZ_NMMU_PAGESZ_2M_ADDR_STRUCT_SIZE 64 152 153/* PARAM_TLV */ 154#define ESF_GZ_TLV_VALUE_LBN 16 155#define ESF_GZ_TLV_VALUE_WIDTH 8 156#define ESE_GZ_TLV_VALUE_LENMIN 8 157#define ESE_GZ_TLV_VALUE_LENMAX 2040 158#define ESF_GZ_TLV_LEN_LBN 8 159#define ESF_GZ_TLV_LEN_WIDTH 8 160#define ESF_GZ_TLV_TYPE_LBN 0 161#define ESF_GZ_TLV_TYPE_WIDTH 8 162#define ESE_GZ_DP_NMMU_GROUP_SIZE 5 163#define ESE_GZ_DP_EVQ_UNSOL_CREDIT_SEQ_BITS 4 164#define ESE_GZ_DP_TX_EV_NUM_DESCS_BITS 3 165#define ESE_GZ_DP_RX_EV_NUM_PACKETS_BITS 2 166#define ESE_GZ_DP_PARTIAL_TSTAMP_SUB_NANO_BITS 1 167#define ESE_GZ_DP_PAD 0 168#define ESE_GZ_PARAM_TLV_STRUCT_SIZE 24 169 170/* PCI_EXPRESS_XCAP_HDR */ 171#define ESF_GZ_PCI_EXPRESS_XCAP_NEXT_LBN 20 172#define ESF_GZ_PCI_EXPRESS_XCAP_NEXT_WIDTH 12 173#define ESF_GZ_PCI_EXPRESS_XCAP_VER_LBN 16 174#define ESF_GZ_PCI_EXPRESS_XCAP_VER_WIDTH 4 175#define ESE_GZ_PCI_EXPRESS_XCAP_VER_VSEC 1 176#define ESF_GZ_PCI_EXPRESS_XCAP_ID_LBN 0 177#define ESF_GZ_PCI_EXPRESS_XCAP_ID_WIDTH 16 178#define ESE_GZ_PCI_EXPRESS_XCAP_ID_VNDR 0xb 179#define ESE_GZ_PCI_EXPRESS_XCAP_HDR_STRUCT_SIZE 32 180 181/* RHEAD_BASE_EVENT */ 182#define ESF_GZ_E_TYPE_LBN 60 183#define ESF_GZ_E_TYPE_WIDTH 4 184#define ESE_GZ_EF100_EV_DRIVER 5 185#define ESE_GZ_EF100_EV_MCDI 4 186#define ESE_GZ_EF100_EV_CONTROL 3 187#define ESE_GZ_EF100_EV_TX_TIMESTAMP 2 188#define ESE_GZ_EF100_EV_TX_COMPLETION 1 189#define ESE_GZ_EF100_EV_RX_PKTS 0 190#define ESF_GZ_EV_EVQ_PHASE_LBN 59 191#define ESF_GZ_EV_EVQ_PHASE_WIDTH 1 192#define ESE_GZ_RHEAD_BASE_EVENT_STRUCT_SIZE 64 193 194/* RHEAD_EW_EVENT */ 195#define ESF_GZ_EV_256_EV32_PHASE_LBN 255 196#define ESF_GZ_EV_256_EV32_PHASE_WIDTH 1 197#define ESF_GZ_EV_256_EV32_TYPE_LBN 251 198#define ESF_GZ_EV_256_EV32_TYPE_WIDTH 4 199#define ESE_GZ_EF100_EVEW_VIRTQ_DESC 2 200#define ESE_GZ_EF100_EVEW_TXQ_DESC 1 201#define ESE_GZ_EF100_EVEW_64BIT 0 202#define ESE_GZ_RHEAD_EW_EVENT_STRUCT_SIZE 256 203 204/* RX_DESC */ 205#define ESF_GZ_RX_BUF_ADDR_LBN 0 206#define ESF_GZ_RX_BUF_ADDR_WIDTH 64 207#define ESE_GZ_RX_DESC_STRUCT_SIZE 64 208 209/* TXQ_DESC_PROXY_EVENT */ 210#define ESF_GZ_EV_TXQ_DP_VI_ID_LBN 128 211#define ESF_GZ_EV_TXQ_DP_VI_ID_WIDTH 16 212#define ESF_GZ_EV_TXQ_DP_TXQ_DESC_LBN 0 213#define ESF_GZ_EV_TXQ_DP_TXQ_DESC_WIDTH 128 214#define ESE_GZ_TXQ_DESC_PROXY_EVENT_STRUCT_SIZE 144 215 216/* TX_DESC_TYPE */ 217#define ESF_GZ_TX_DESC_TYPE_LBN 124 218#define ESF_GZ_TX_DESC_TYPE_WIDTH 4 219#define ESE_GZ_TX_DESC_TYPE_DESC2CMPT 7 220#define ESE_GZ_TX_DESC_TYPE_MEM2MEM 4 221#define ESE_GZ_TX_DESC_TYPE_SEG 3 222#define ESE_GZ_TX_DESC_TYPE_TSO 2 223#define ESE_GZ_TX_DESC_TYPE_PREFIX 1 224#define ESE_GZ_TX_DESC_TYPE_SEND 0 225#define ESE_GZ_TX_DESC_TYPE_STRUCT_SIZE 128 226 227/* VIRTQ_DESC_PROXY_EVENT */ 228#define ESF_GZ_EV_VQ_DP_AVAIL_ENTRY_LBN 144 229#define ESF_GZ_EV_VQ_DP_AVAIL_ENTRY_WIDTH 16 230#define ESF_GZ_EV_VQ_DP_VI_ID_LBN 128 231#define ESF_GZ_EV_VQ_DP_VI_ID_WIDTH 16 232#define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_LBN 0 233#define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_WIDTH 128 234#define ESE_GZ_VIRTQ_DESC_PROXY_EVENT_STRUCT_SIZE 160 235 236/* XIL_CFGBAR_TBL_ENTRY */ 237#define ESF_GZ_CFGBAR_CONT_CAP_OFF_HI_LBN 96 238#define ESF_GZ_CFGBAR_CONT_CAP_OFF_HI_WIDTH 32 239#define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_LBN 68 240#define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_WIDTH 60 241#define ESE_GZ_CONT_CAP_OFFSET_BYTES_SHIFT 4 242#define ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF_LBN 67 243#define ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF_WIDTH 29 244#define ESE_GZ_EF100_FUNC_CTL_WIN_OFF_SHIFT 4 245#define ESF_GZ_CFGBAR_CONT_CAP_OFF_LO_LBN 68 246#define ESF_GZ_CFGBAR_CONT_CAP_OFF_LO_WIDTH 28 247#define ESF_GZ_CFGBAR_CONT_CAP_RSV_LBN 67 248#define ESF_GZ_CFGBAR_CONT_CAP_RSV_WIDTH 1 249#define ESF_GZ_CFGBAR_EF100_BAR_LBN 64 250#define ESF_GZ_CFGBAR_EF100_BAR_WIDTH 3 251#define ESE_GZ_CFGBAR_EF100_BAR_NUM_INVALID 7 252#define ESE_GZ_CFGBAR_EF100_BAR_NUM_EXPANSION_ROM 6 253#define ESF_GZ_CFGBAR_CONT_CAP_BAR_LBN 64 254#define ESF_GZ_CFGBAR_CONT_CAP_BAR_WIDTH 3 255#define ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_INVALID 7 256#define ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_EXPANSION_ROM 6 257#define ESF_GZ_CFGBAR_ENTRY_SIZE_LBN 32 258#define ESF_GZ_CFGBAR_ENTRY_SIZE_WIDTH 32 259#define ESE_GZ_CFGBAR_ENTRY_SIZE_EF100 12 260#define ESE_GZ_CFGBAR_ENTRY_HEADER_SIZE 8 261#define ESF_GZ_CFGBAR_ENTRY_LAST_LBN 28 262#define ESF_GZ_CFGBAR_ENTRY_LAST_WIDTH 1 263#define ESF_GZ_CFGBAR_ENTRY_REV_LBN 20 264#define ESF_GZ_CFGBAR_ENTRY_REV_WIDTH 8 265#define ESE_GZ_CFGBAR_ENTRY_REV_EF100 0 266#define ESF_GZ_CFGBAR_ENTRY_FORMAT_LBN 0 267#define ESF_GZ_CFGBAR_ENTRY_FORMAT_WIDTH 20 268#define ESE_GZ_CFGBAR_ENTRY_LAST 0xfffff 269#define ESE_GZ_CFGBAR_ENTRY_CONT_CAP_ADDR 0xffffe 270#define ESE_GZ_CFGBAR_ENTRY_EF100 0xef100 271#define ESE_GZ_XIL_CFGBAR_TBL_ENTRY_STRUCT_SIZE 128 272 273/* XIL_CFGBAR_VSEC */ 274#define ESF_GZ_VSEC_TBL_OFF_HI_LBN 64 275#define ESF_GZ_VSEC_TBL_OFF_HI_WIDTH 32 276#define ESE_GZ_VSEC_TBL_OFF_HI_BYTES_SHIFT 32 277#define ESF_GZ_VSEC_TBL_OFF_LO_LBN 36 278#define ESF_GZ_VSEC_TBL_OFF_LO_WIDTH 28 279#define ESE_GZ_VSEC_TBL_OFF_LO_BYTES_SHIFT 4 280#define ESF_GZ_VSEC_TBL_BAR_LBN 32 281#define ESF_GZ_VSEC_TBL_BAR_WIDTH 4 282#define ESE_GZ_VSEC_BAR_NUM_INVALID 7 283#define ESE_GZ_VSEC_BAR_NUM_EXPANSION_ROM 6 284#define ESF_GZ_VSEC_LEN_LBN 20 285#define ESF_GZ_VSEC_LEN_WIDTH 12 286#define ESE_GZ_VSEC_LEN_HIGH_OFFT 16 287#define ESE_GZ_VSEC_LEN_MIN 12 288#define ESF_GZ_VSEC_VER_LBN 16 289#define ESF_GZ_VSEC_VER_WIDTH 4 290#define ESE_GZ_VSEC_VER_XIL_CFGBAR 0 291#define ESF_GZ_VSEC_ID_LBN 0 292#define ESF_GZ_VSEC_ID_WIDTH 16 293#define ESE_GZ_XILINX_VSEC_ID 0x20 294#define ESE_GZ_XIL_CFGBAR_VSEC_STRUCT_SIZE 96 295 296/* rh_egres_hclass */ 297#define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_LBN 15 298#define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_WIDTH 1 299#define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L3_CLASS_LBN 13 300#define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L3_CLASS_WIDTH 2 301#define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM_LBN 12 302#define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM_WIDTH 1 303#define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CLASS_LBN 10 304#define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CLASS_WIDTH 2 305#define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_LBN 8 306#define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_WIDTH 2 307#define ESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS_LBN 5 308#define ESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS_WIDTH 3 309#define ESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN_LBN 3 310#define ESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN_WIDTH 2 311#define ESF_GZ_RX_PREFIX_HCLASS_L2_CLASS_LBN 2 312#define ESF_GZ_RX_PREFIX_HCLASS_L2_CLASS_WIDTH 1 313#define ESF_GZ_RX_PREFIX_HCLASS_L2_STATUS_LBN 0 314#define ESF_GZ_RX_PREFIX_HCLASS_L2_STATUS_WIDTH 2 315#define ESE_GZ_RH_EGRES_HCLASS_STRUCT_SIZE 16 316 317/* sf_driver */ 318#define ESF_GZ_DRIVER_E_TYPE_LBN 60 319#define ESF_GZ_DRIVER_E_TYPE_WIDTH 4 320#define ESF_GZ_DRIVER_PHASE_LBN 59 321#define ESF_GZ_DRIVER_PHASE_WIDTH 1 322#define ESF_GZ_DRIVER_DATA_LBN 0 323#define ESF_GZ_DRIVER_DATA_WIDTH 59 324#define ESE_GZ_SF_DRIVER_STRUCT_SIZE 64 325 326/* sf_ev_rsvd */ 327#define ESF_GZ_EV_RSVD_TBD_NEXT_LBN 34 328#define ESF_GZ_EV_RSVD_TBD_NEXT_WIDTH 3 329#define ESF_GZ_EV_RSVD_EVENT_GEN_FLAGS_LBN 30 330#define ESF_GZ_EV_RSVD_EVENT_GEN_FLAGS_WIDTH 4 331#define ESF_GZ_EV_RSVD_SRC_QID_LBN 18 332#define ESF_GZ_EV_RSVD_SRC_QID_WIDTH 12 333#define ESF_GZ_EV_RSVD_SEQ_NUM_LBN 2 334#define ESF_GZ_EV_RSVD_SEQ_NUM_WIDTH 16 335#define ESF_GZ_EV_RSVD_TBD_LBN 0 336#define ESF_GZ_EV_RSVD_TBD_WIDTH 2 337#define ESE_GZ_SF_EV_RSVD_STRUCT_SIZE 37 338 339/* sf_flush_evnt */ 340#define ESF_GZ_EV_FLSH_E_TYPE_LBN 60 341#define ESF_GZ_EV_FLSH_E_TYPE_WIDTH 4 342#define ESF_GZ_EV_FLSH_PHASE_LBN 59 343#define ESF_GZ_EV_FLSH_PHASE_WIDTH 1 344#define ESF_GZ_EV_FLSH_SUB_TYPE_LBN 53 345#define ESF_GZ_EV_FLSH_SUB_TYPE_WIDTH 6 346#define ESF_GZ_EV_FLSH_RSVD_LBN 10 347#define ESF_GZ_EV_FLSH_RSVD_WIDTH 43 348#define ESF_GZ_EV_FLSH_LABEL_LBN 4 349#define ESF_GZ_EV_FLSH_LABEL_WIDTH 6 350#define ESF_GZ_EV_FLSH_FLUSH_TYPE_LBN 0 351#define ESF_GZ_EV_FLSH_FLUSH_TYPE_WIDTH 4 352#define ESE_GZ_SF_FLUSH_EVNT_STRUCT_SIZE 64 353 354/* sf_rx_pkts */ 355#define ESF_GZ_EV_RXPKTS_E_TYPE_LBN 60 356#define ESF_GZ_EV_RXPKTS_E_TYPE_WIDTH 4 357#define ESF_GZ_EV_RXPKTS_PHASE_LBN 59 358#define ESF_GZ_EV_RXPKTS_PHASE_WIDTH 1 359#define ESF_GZ_EV_RXPKTS_RSVD_LBN 22 360#define ESF_GZ_EV_RXPKTS_RSVD_WIDTH 37 361#define ESF_GZ_EV_RXPKTS_Q_LABEL_LBN 16 362#define ESF_GZ_EV_RXPKTS_Q_LABEL_WIDTH 6 363#define ESF_GZ_EV_RXPKTS_NUM_PKT_LBN 0 364#define ESF_GZ_EV_RXPKTS_NUM_PKT_WIDTH 16 365#define ESE_GZ_SF_RX_PKTS_STRUCT_SIZE 64 366 367/* sf_rx_prefix */ 368#define ESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_LBN 160 369#define ESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_WIDTH 16 370#define ESF_GZ_RX_PREFIX_CSUM_FRAME_LBN 144 371#define ESF_GZ_RX_PREFIX_CSUM_FRAME_WIDTH 16 372#define ESF_GZ_RX_PREFIX_INGRESS_VPORT_LBN 128 373#define ESF_GZ_RX_PREFIX_INGRESS_VPORT_WIDTH 16 374#define ESF_GZ_RX_PREFIX_USER_MARK_LBN 96 375#define ESF_GZ_RX_PREFIX_USER_MARK_WIDTH 32 376#define ESF_GZ_RX_PREFIX_RSS_HASH_LBN 64 377#define ESF_GZ_RX_PREFIX_RSS_HASH_WIDTH 32 378#define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN 32 379#define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_WIDTH 32 380#define ESF_GZ_RX_PREFIX_CLASS_LBN 16 381#define ESF_GZ_RX_PREFIX_CLASS_WIDTH 16 382#define ESF_GZ_RX_PREFIX_USER_FLAG_LBN 15 383#define ESF_GZ_RX_PREFIX_USER_FLAG_WIDTH 1 384#define ESF_GZ_RX_PREFIX_RSS_HASH_VALID_LBN 14 385#define ESF_GZ_RX_PREFIX_RSS_HASH_VALID_WIDTH 1 386#define ESF_GZ_RX_PREFIX_LENGTH_LBN 0 387#define ESF_GZ_RX_PREFIX_LENGTH_WIDTH 14 388#define ESE_GZ_SF_RX_PREFIX_STRUCT_SIZE 176 389 390/* sf_rxtx_generic */ 391#define ESF_GZ_EV_BARRIER_LBN 167 392#define ESF_GZ_EV_BARRIER_WIDTH 1 393#define ESF_GZ_EV_RSVD_LBN 130 394#define ESF_GZ_EV_RSVD_WIDTH 37 395#define ESF_GZ_EV_DPRXY_LBN 129 396#define ESF_GZ_EV_DPRXY_WIDTH 1 397#define ESF_GZ_EV_VIRTIO_LBN 128 398#define ESF_GZ_EV_VIRTIO_WIDTH 1 399#define ESF_GZ_EV_COUNT_LBN 0 400#define ESF_GZ_EV_COUNT_WIDTH 128 401#define ESE_GZ_SF_RXTX_GENERIC_STRUCT_SIZE 168 402 403/* sf_ts_stamp */ 404#define ESF_GZ_EV_TS_E_TYPE_LBN 60 405#define ESF_GZ_EV_TS_E_TYPE_WIDTH 4 406#define ESF_GZ_EV_TS_PHASE_LBN 59 407#define ESF_GZ_EV_TS_PHASE_WIDTH 1 408#define ESF_GZ_EV_TS_RSVD_LBN 56 409#define ESF_GZ_EV_TS_RSVD_WIDTH 3 410#define ESF_GZ_EV_TS_STATUS_LBN 54 411#define ESF_GZ_EV_TS_STATUS_WIDTH 2 412#define ESF_GZ_EV_TS_Q_LABEL_LBN 48 413#define ESF_GZ_EV_TS_Q_LABEL_WIDTH 6 414#define ESF_GZ_EV_TS_DESC_ID_LBN 32 415#define ESF_GZ_EV_TS_DESC_ID_WIDTH 16 416#define ESF_GZ_EV_TS_PARTIAL_STAMP_LBN 0 417#define ESF_GZ_EV_TS_PARTIAL_STAMP_WIDTH 32 418#define ESE_GZ_SF_TS_STAMP_STRUCT_SIZE 64 419 420/* sf_tx_cmplt */ 421#define ESF_GZ_EV_TXCMPL_E_TYPE_LBN 60 422#define ESF_GZ_EV_TXCMPL_E_TYPE_WIDTH 4 423#define ESF_GZ_EV_TXCMPL_PHASE_LBN 59 424#define ESF_GZ_EV_TXCMPL_PHASE_WIDTH 1 425#define ESF_GZ_EV_TXCMPL_RSVD_LBN 22 426#define ESF_GZ_EV_TXCMPL_RSVD_WIDTH 37 427#define ESF_GZ_EV_TXCMPL_Q_LABEL_LBN 16 428#define ESF_GZ_EV_TXCMPL_Q_LABEL_WIDTH 6 429#define ESF_GZ_EV_TXCMPL_NUM_DESC_LBN 0 430#define ESF_GZ_EV_TXCMPL_NUM_DESC_WIDTH 16 431#define ESE_GZ_SF_TX_CMPLT_STRUCT_SIZE 64 432 433/* sf_tx_desc2cmpt_dsc_fmt */ 434#define ESF_GZ_D2C_TGT_VI_ID_LBN 108 435#define ESF_GZ_D2C_TGT_VI_ID_WIDTH 16 436#define ESF_GZ_D2C_CMPT2_LBN 107 437#define ESF_GZ_D2C_CMPT2_WIDTH 1 438#define ESF_GZ_D2C_ABS_VI_ID_LBN 106 439#define ESF_GZ_D2C_ABS_VI_ID_WIDTH 1 440#define ESF_GZ_D2C_ORDERED_LBN 105 441#define ESF_GZ_D2C_ORDERED_WIDTH 1 442#define ESF_GZ_D2C_SKIP_N_LBN 97 443#define ESF_GZ_D2C_SKIP_N_WIDTH 8 444#define ESF_GZ_D2C_RSVD_LBN 64 445#define ESF_GZ_D2C_RSVD_WIDTH 33 446#define ESF_GZ_D2C_COMPLETION_LBN 0 447#define ESF_GZ_D2C_COMPLETION_WIDTH 64 448#define ESE_GZ_SF_TX_DESC2CMPT_DSC_FMT_STRUCT_SIZE 124 449 450/* sf_tx_mem2mem_dsc_fmt */ 451#define ESF_GZ_M2M_ADDR_SPC_EN_LBN 123 452#define ESF_GZ_M2M_ADDR_SPC_EN_WIDTH 1 453#define ESF_GZ_M2M_TRANSLATE_ADDR_LBN 122 454#define ESF_GZ_M2M_TRANSLATE_ADDR_WIDTH 1 455#define ESF_GZ_M2M_RSVD_LBN 120 456#define ESF_GZ_M2M_RSVD_WIDTH 2 457#define ESF_GZ_M2M_ADDR_SPC_LBN 108 458#define ESF_GZ_M2M_ADDR_SPC_WIDTH 12 459#define ESF_GZ_M2M_ADDR_SPC_PASID_LBN 86 460#define ESF_GZ_M2M_ADDR_SPC_PASID_WIDTH 22 461#define ESF_GZ_M2M_ADDR_SPC_MODE_LBN 84 462#define ESF_GZ_M2M_ADDR_SPC_MODE_WIDTH 2 463#define ESF_GZ_M2M_LEN_MINUS_1_LBN 64 464#define ESF_GZ_M2M_LEN_MINUS_1_WIDTH 20 465#define ESF_GZ_M2M_ADDR_LBN 0 466#define ESF_GZ_M2M_ADDR_WIDTH 64 467#define ESE_GZ_SF_TX_MEM2MEM_DSC_FMT_STRUCT_SIZE 124 468 469/* sf_tx_ovr_dsc_fmt */ 470#define ESF_GZ_TX_PREFIX_MARK_EN_LBN 123 471#define ESF_GZ_TX_PREFIX_MARK_EN_WIDTH 1 472#define ESF_GZ_TX_PREFIX_INGRESS_MPORT_EN_LBN 122 473#define ESF_GZ_TX_PREFIX_INGRESS_MPORT_EN_WIDTH 1 474#define ESF_GZ_TX_PREFIX_INLINE_CAPSULE_META_LBN 121 475#define ESF_GZ_TX_PREFIX_INLINE_CAPSULE_META_WIDTH 1 476#define ESF_GZ_TX_PREFIX_EGRESS_MPORT_EN_LBN 120 477#define ESF_GZ_TX_PREFIX_EGRESS_MPORT_EN_WIDTH 1 478#define ESF_GZ_TX_PREFIX_RSRVD_LBN 64 479#define ESF_GZ_TX_PREFIX_RSRVD_WIDTH 56 480#define ESF_GZ_TX_PREFIX_EGRESS_MPORT_LBN 48 481#define ESF_GZ_TX_PREFIX_EGRESS_MPORT_WIDTH 16 482#define ESF_GZ_TX_PREFIX_INGRESS_MPORT_LBN 32 483#define ESF_GZ_TX_PREFIX_INGRESS_MPORT_WIDTH 16 484#define ESF_GZ_TX_PREFIX_MARK_LBN 0 485#define ESF_GZ_TX_PREFIX_MARK_WIDTH 32 486#define ESE_GZ_SF_TX_OVR_DSC_FMT_STRUCT_SIZE 124 487 488/* sf_tx_seg_dsc_fmt */ 489#define ESF_GZ_TX_SEG_ADDR_SPC_EN_LBN 123 490#define ESF_GZ_TX_SEG_ADDR_SPC_EN_WIDTH 1 491#define ESF_GZ_TX_SEG_TRANSLATE_ADDR_LBN 122 492#define ESF_GZ_TX_SEG_TRANSLATE_ADDR_WIDTH 1 493#define ESF_GZ_TX_SEG_RSVD2_LBN 120 494#define ESF_GZ_TX_SEG_RSVD2_WIDTH 2 495#define ESF_GZ_TX_SEG_ADDR_SPC_LBN 108 496#define ESF_GZ_TX_SEG_ADDR_SPC_WIDTH 12 497#define ESF_GZ_TX_SEG_ADDR_SPC_PASID_LBN 86 498#define ESF_GZ_TX_SEG_ADDR_SPC_PASID_WIDTH 22 499#define ESF_GZ_TX_SEG_ADDR_SPC_MODE_LBN 84 500#define ESF_GZ_TX_SEG_ADDR_SPC_MODE_WIDTH 2 501#define ESF_GZ_TX_SEG_RSVD_LBN 80 502#define ESF_GZ_TX_SEG_RSVD_WIDTH 4 503#define ESF_GZ_TX_SEG_LEN_LBN 64 504#define ESF_GZ_TX_SEG_LEN_WIDTH 16 505#define ESF_GZ_TX_SEG_ADDR_LBN 0 506#define ESF_GZ_TX_SEG_ADDR_WIDTH 64 507#define ESE_GZ_SF_TX_SEG_DSC_FMT_STRUCT_SIZE 124 508 509/* sf_tx_std_dsc_fmt */ 510#define ESF_GZ_TX_SEND_VLAN_INSERT_TCI_LBN 108 511#define ESF_GZ_TX_SEND_VLAN_INSERT_TCI_WIDTH 16 512#define ESF_GZ_TX_SEND_VLAN_INSERT_EN_LBN 107 513#define ESF_GZ_TX_SEND_VLAN_INSERT_EN_WIDTH 1 514#define ESF_GZ_TX_SEND_TSTAMP_REQ_LBN 106 515#define ESF_GZ_TX_SEND_TSTAMP_REQ_WIDTH 1 516#define ESF_GZ_TX_SEND_CSO_OUTER_L4_LBN 105 517#define ESF_GZ_TX_SEND_CSO_OUTER_L4_WIDTH 1 518#define ESF_GZ_TX_SEND_CSO_OUTER_L3_LBN 104 519#define ESF_GZ_TX_SEND_CSO_OUTER_L3_WIDTH 1 520#define ESF_GZ_TX_SEND_CSO_INNER_L3_LBN 101 521#define ESF_GZ_TX_SEND_CSO_INNER_L3_WIDTH 3 522#define ESF_GZ_TX_SEND_RSVD_LBN 99 523#define ESF_GZ_TX_SEND_RSVD_WIDTH 2 524#define ESF_GZ_TX_SEND_CSO_PARTIAL_EN_LBN 97 525#define ESF_GZ_TX_SEND_CSO_PARTIAL_EN_WIDTH 2 526#define ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W_LBN 92 527#define ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W_WIDTH 5 528#define ESF_GZ_TX_SEND_CSO_PARTIAL_START_W_LBN 83 529#define ESF_GZ_TX_SEND_CSO_PARTIAL_START_W_WIDTH 9 530#define ESF_GZ_TX_SEND_NUM_SEGS_LBN 78 531#define ESF_GZ_TX_SEND_NUM_SEGS_WIDTH 5 532#define ESF_GZ_TX_SEND_LEN_LBN 64 533#define ESF_GZ_TX_SEND_LEN_WIDTH 14 534#define ESF_GZ_TX_SEND_ADDR_LBN 0 535#define ESF_GZ_TX_SEND_ADDR_WIDTH 64 536#define ESE_GZ_SF_TX_STD_DSC_FMT_STRUCT_SIZE 124 537 538/* sf_tx_tso_dsc_fmt */ 539#define ESF_GZ_TX_TSO_VLAN_INSERT_TCI_LBN 108 540#define ESF_GZ_TX_TSO_VLAN_INSERT_TCI_WIDTH 16 541#define ESF_GZ_TX_TSO_VLAN_INSERT_EN_LBN 107 542#define ESF_GZ_TX_TSO_VLAN_INSERT_EN_WIDTH 1 543#define ESF_GZ_TX_TSO_TSTAMP_REQ_LBN 106 544#define ESF_GZ_TX_TSO_TSTAMP_REQ_WIDTH 1 545#define ESF_GZ_TX_TSO_CSO_OUTER_L4_LBN 105 546#define ESF_GZ_TX_TSO_CSO_OUTER_L4_WIDTH 1 547#define ESF_GZ_TX_TSO_CSO_OUTER_L3_LBN 104 548#define ESF_GZ_TX_TSO_CSO_OUTER_L3_WIDTH 1 549#define ESF_GZ_TX_TSO_CSO_INNER_L3_LBN 101 550#define ESF_GZ_TX_TSO_CSO_INNER_L3_WIDTH 3 551#define ESF_GZ_TX_TSO_RSVD_LBN 94 552#define ESF_GZ_TX_TSO_RSVD_WIDTH 7 553#define ESF_GZ_TX_TSO_CSO_INNER_L4_LBN 93 554#define ESF_GZ_TX_TSO_CSO_INNER_L4_WIDTH 1 555#define ESF_GZ_TX_TSO_INNER_L4_OFF_W_LBN 85 556#define ESF_GZ_TX_TSO_INNER_L4_OFF_W_WIDTH 8 557#define ESF_GZ_TX_TSO_INNER_L3_OFF_W_LBN 77 558#define ESF_GZ_TX_TSO_INNER_L3_OFF_W_WIDTH 8 559#define ESF_GZ_TX_TSO_OUTER_L4_OFF_W_LBN 69 560#define ESF_GZ_TX_TSO_OUTER_L4_OFF_W_WIDTH 8 561#define ESF_GZ_TX_TSO_OUTER_L3_OFF_W_LBN 64 562#define ESF_GZ_TX_TSO_OUTER_L3_OFF_W_WIDTH 5 563#define ESF_GZ_TX_TSO_PAYLOAD_LEN_LBN 42 564#define ESF_GZ_TX_TSO_PAYLOAD_LEN_WIDTH 22 565#define ESF_GZ_TX_TSO_HDR_LEN_W_LBN 34 566#define ESF_GZ_TX_TSO_HDR_LEN_W_WIDTH 8 567#define ESF_GZ_TX_TSO_ED_OUTER_UDP_LEN_LBN 33 568#define ESF_GZ_TX_TSO_ED_OUTER_UDP_LEN_WIDTH 1 569#define ESF_GZ_TX_TSO_ED_INNER_IP_LEN_LBN 32 570#define ESF_GZ_TX_TSO_ED_INNER_IP_LEN_WIDTH 1 571#define ESF_GZ_TX_TSO_ED_OUTER_IP_LEN_LBN 31 572#define ESF_GZ_TX_TSO_ED_OUTER_IP_LEN_WIDTH 1 573#define ESF_GZ_TX_TSO_ED_INNER_IP4_ID_LBN 29 574#define ESF_GZ_TX_TSO_ED_INNER_IP4_ID_WIDTH 2 575#define ESF_GZ_TX_TSO_ED_OUTER_IP4_ID_LBN 27 576#define ESF_GZ_TX_TSO_ED_OUTER_IP4_ID_WIDTH 2 577#define ESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS_LBN 17 578#define ESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS_WIDTH 10 579#define ESF_GZ_TX_TSO_HDR_NUM_SEGS_LBN 14 580#define ESF_GZ_TX_TSO_HDR_NUM_SEGS_WIDTH 3 581#define ESF_GZ_TX_TSO_MSS_LBN 0 582#define ESF_GZ_TX_TSO_MSS_WIDTH 14 583#define ESE_GZ_SF_TX_TSO_DSC_FMT_STRUCT_SIZE 124 584 585 586/* Enum DESIGN_PARAMS */ 587#define ESE_EF100_DP_GZ_RX_MAX_RUNT 17 588#define ESE_EF100_DP_GZ_VI_STRIDES 16 589#define ESE_EF100_DP_GZ_NMMU_PAGE_SIZES 15 590#define ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS 14 591#define ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN 13 592#define ESE_EF100_DP_GZ_COMPAT 12 593#define ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES 11 594#define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS 10 595#define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN 9 596#define ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY 8 597#define ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY 7 598#define ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS 6 599#define ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN 5 600#define ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS 4 601#define ESE_EF100_DP_GZ_NMMU_GROUP_SIZE 3 602#define ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS 2 603#define ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS 1 604#define ESE_EF100_DP_GZ_PAD 0 605 606/* Enum DESIGN_PARAM_DEFAULTS */ 607#define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT 0x3fffff 608#define ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT 8192 609#define ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN_DEFAULT 8192 610#define ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS_DEFAULT 0x1106 611#define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT 0x3ff 612#define ESE_EF100_DP_GZ_RX_MAX_RUNT_DEFAULT 640 613#define ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS_DEFAULT 512 614#define ESE_EF100_DP_GZ_NMMU_PAGE_SIZES_DEFAULT 512 615#define ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT 192 616#define ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY_DEFAULT 64 617#define ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY_DEFAULT 64 618#define ESE_EF100_DP_GZ_NMMU_GROUP_SIZE_DEFAULT 32 619#define ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT 16 620#define ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS_DEFAULT 7 621#define ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT 4 622#define ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS_DEFAULT 2 623#define ESE_EF100_DP_GZ_COMPAT_DEFAULT 0 624 625/* Enum HOST_IF_CONSTANTS */ 626#define ESE_GZ_FCW_LEN 0x4C 627#define ESE_GZ_RX_PKT_PREFIX_LEN 22 628 629/* Enum PCI_CONSTANTS */ 630#define ESE_GZ_PCI_BASE_CONFIG_SPACE_SIZE 256 631#define ESE_GZ_PCI_EXPRESS_XCAP_HDR_SIZE 4 632 633/* Enum RH_HCLASS_L2_CLASS */ 634#define ESE_GZ_RH_HCLASS_L2_CLASS_E2_0123VLAN 1 635#define ESE_GZ_RH_HCLASS_L2_CLASS_OTHER 0 636 637/* Enum RH_HCLASS_L2_STATUS */ 638#define ESE_GZ_RH_HCLASS_L2_STATUS_RESERVED 3 639#define ESE_GZ_RH_HCLASS_L2_STATUS_FCS_ERR 2 640#define ESE_GZ_RH_HCLASS_L2_STATUS_LEN_ERR 1 641#define ESE_GZ_RH_HCLASS_L2_STATUS_OK 0 642 643/* Enum RH_HCLASS_L3_CLASS */ 644#define ESE_GZ_RH_HCLASS_L3_CLASS_OTHER 3 645#define ESE_GZ_RH_HCLASS_L3_CLASS_IP6 2 646#define ESE_GZ_RH_HCLASS_L3_CLASS_IP4BAD 1 647#define ESE_GZ_RH_HCLASS_L3_CLASS_IP4GOOD 0 648 649/* Enum RH_HCLASS_L4_CLASS */ 650#define ESE_GZ_RH_HCLASS_L4_CLASS_OTHER 3 651#define ESE_GZ_RH_HCLASS_L4_CLASS_FRAG 2 652#define ESE_GZ_RH_HCLASS_L4_CLASS_UDP 1 653#define ESE_GZ_RH_HCLASS_L4_CLASS_TCP 0 654 655/* Enum RH_HCLASS_L4_CSUM */ 656#define ESE_GZ_RH_HCLASS_L4_CSUM_GOOD 1 657#define ESE_GZ_RH_HCLASS_L4_CSUM_BAD_OR_UNKNOWN 0 658 659/* Enum RH_HCLASS_TUNNEL_CLASS */ 660#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_7 7 661#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_6 6 662#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_5 5 663#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_4 4 664#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_GENEVE 3 665#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_NVGRE 2 666#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_VXLAN 1 667#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_NONE 0 668 669/* Enum TX_DESC_CSO_PARTIAL_EN */ 670#define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_TCP 2 671#define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_UDP 1 672#define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_OFF 0 673 674/* Enum TX_DESC_CS_INNER_L3 */ 675#define ESE_GZ_TX_DESC_CS_INNER_L3_GENEVE 3 676#define ESE_GZ_TX_DESC_CS_INNER_L3_NVGRE 2 677#define ESE_GZ_TX_DESC_CS_INNER_L3_VXLAN 1 678#define ESE_GZ_TX_DESC_CS_INNER_L3_OFF 0 679 680/* Enum TX_DESC_IP4_ID */ 681#define ESE_GZ_TX_DESC_IP4_ID_INC_MOD16 2 682#define ESE_GZ_TX_DESC_IP4_ID_INC_MOD15 1 683#define ESE_GZ_TX_DESC_IP4_ID_NO_OP 0 684/**************************************************************************/ 685 686#define ESF_GZ_EV_DEBUG_EVENT_GEN_FLAGS_LBN 44 687#define ESF_GZ_EV_DEBUG_EVENT_GEN_FLAGS_WIDTH 4 688#define ESF_GZ_EV_DEBUG_SRC_QID_LBN 32 689#define ESF_GZ_EV_DEBUG_SRC_QID_WIDTH 12 690#define ESF_GZ_EV_DEBUG_SEQ_NUM_LBN 16 691#define ESF_GZ_EV_DEBUG_SEQ_NUM_WIDTH 16 692 693#endif /* EFX_EF100_REGS_H */ 694