1
2
3
4
5
6
7
8#include <linux/bitops.h>
9#include <linux/delay.h>
10#include <linux/pci.h>
11#include <linux/module.h>
12#include <linux/slab.h>
13#include <linux/random.h>
14#include "net_driver.h"
15#include "bitfield.h"
16#include "efx.h"
17#include "efx_common.h"
18#include "nic.h"
19#include "farch_regs.h"
20#include "io.h"
21#include "workarounds.h"
22#include "mcdi.h"
23#include "mcdi_pcol.h"
24#include "mcdi_port.h"
25#include "mcdi_port_common.h"
26#include "selftest.h"
27#include "siena_sriov.h"
28#include "rx_common.h"
29
30
31
32static void siena_init_wol(struct efx_nic *efx);
33
34
35static void siena_push_irq_moderation(struct efx_channel *channel)
36{
37 struct efx_nic *efx = channel->efx;
38 efx_dword_t timer_cmd;
39
40 if (channel->irq_moderation_us) {
41 unsigned int ticks;
42
43 ticks = efx_usecs_to_ticks(efx, channel->irq_moderation_us);
44 EFX_POPULATE_DWORD_2(timer_cmd,
45 FRF_CZ_TC_TIMER_MODE,
46 FFE_CZ_TIMER_MODE_INT_HLDOFF,
47 FRF_CZ_TC_TIMER_VAL,
48 ticks - 1);
49 } else {
50 EFX_POPULATE_DWORD_2(timer_cmd,
51 FRF_CZ_TC_TIMER_MODE,
52 FFE_CZ_TIMER_MODE_DIS,
53 FRF_CZ_TC_TIMER_VAL, 0);
54 }
55 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
56 channel->channel);
57}
58
59void siena_prepare_flush(struct efx_nic *efx)
60{
61 if (efx->fc_disable++ == 0)
62 efx_mcdi_set_mac(efx);
63}
64
65void siena_finish_flush(struct efx_nic *efx)
66{
67 if (--efx->fc_disable == 0)
68 efx_mcdi_set_mac(efx);
69}
70
71static const struct efx_farch_register_test siena_register_tests[] = {
72 { FR_AZ_ADR_REGION,
73 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
74 { FR_CZ_USR_EV_CFG,
75 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
76 { FR_AZ_RX_CFG,
77 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
78 { FR_AZ_TX_CFG,
79 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
80 { FR_AZ_TX_RESERVED,
81 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
82 { FR_AZ_SRM_TX_DC_CFG,
83 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
84 { FR_AZ_RX_DC_CFG,
85 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
86 { FR_AZ_RX_DC_PF_WM,
87 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
88 { FR_BZ_DP_CTRL,
89 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
90 { FR_BZ_RX_RSS_TKEY,
91 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
92 { FR_CZ_RX_RSS_IPV6_REG1,
93 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
94 { FR_CZ_RX_RSS_IPV6_REG2,
95 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
96 { FR_CZ_RX_RSS_IPV6_REG3,
97 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
98};
99
100static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
101{
102 enum reset_type reset_method = RESET_TYPE_ALL;
103 int rc, rc2;
104
105 efx_reset_down(efx, reset_method);
106
107
108
109
110 rc = efx_mcdi_reset(efx, reset_method);
111 if (rc)
112 goto out;
113
114 tests->registers =
115 efx_farch_test_registers(efx, siena_register_tests,
116 ARRAY_SIZE(siena_register_tests))
117 ? -1 : 1;
118
119 rc = efx_mcdi_reset(efx, reset_method);
120out:
121 rc2 = efx_reset_up(efx, reset_method, rc == 0);
122 return rc ? rc : rc2;
123}
124
125
126
127
128
129
130
131
132static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
133{
134 _efx_writed(efx, cpu_to_le32(host_time),
135 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
136}
137
138static int siena_ptp_set_ts_config(struct efx_nic *efx,
139 struct hwtstamp_config *init)
140{
141 int rc;
142
143 switch (init->rx_filter) {
144 case HWTSTAMP_FILTER_NONE:
145
146 return efx_ptp_change_mode(efx,
147 init->tx_type != HWTSTAMP_TX_OFF,
148 efx_ptp_get_mode(efx));
149 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
150 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
151 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
152 init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
153 return efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1);
154 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
155 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
156 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
157 init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
158 rc = efx_ptp_change_mode(efx, true,
159 MC_CMD_PTP_MODE_V2_ENHANCED);
160
161
162
163
164
165 if (rc != 0)
166 rc = efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V2);
167 return rc;
168 default:
169 return -ERANGE;
170 }
171}
172
173
174
175
176
177
178
179
180static int siena_map_reset_flags(u32 *flags)
181{
182 enum {
183 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
184 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
185 ETH_RESET_PHY),
186 SIENA_RESET_MC = (SIENA_RESET_PORT |
187 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
188 };
189
190 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
191 *flags &= ~SIENA_RESET_MC;
192 return RESET_TYPE_WORLD;
193 }
194
195 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
196 *flags &= ~SIENA_RESET_PORT;
197 return RESET_TYPE_ALL;
198 }
199
200
201
202 return -EINVAL;
203}
204
205#ifdef CONFIG_EEH
206
207
208
209
210
211
212static void siena_monitor(struct efx_nic *efx)
213{
214 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
215
216 eeh_dev_check_failure(eehdev);
217}
218#endif
219
220static int siena_probe_nvconfig(struct efx_nic *efx)
221{
222 u32 caps = 0;
223 int rc;
224
225 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
226
227 efx->timer_quantum_ns =
228 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
229 3072 : 6144;
230 efx->timer_max_ns = efx->type->timer_period_max *
231 efx->timer_quantum_ns;
232
233 return rc;
234}
235
236static int siena_dimension_resources(struct efx_nic *efx)
237{
238
239
240
241
242 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
243 return 0;
244}
245
246
247
248
249static unsigned int siena_mem_bar(struct efx_nic *efx)
250{
251 return 2;
252}
253
254static unsigned int siena_mem_map_size(struct efx_nic *efx)
255{
256 return FR_CZ_MC_TREG_SMEM +
257 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
258}
259
260static int siena_probe_nic(struct efx_nic *efx)
261{
262 struct siena_nic_data *nic_data;
263 efx_oword_t reg;
264 int rc;
265
266
267 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
268 if (!nic_data)
269 return -ENOMEM;
270 nic_data->efx = efx;
271 efx->nic_data = nic_data;
272
273 if (efx_farch_fpga_ver(efx) != 0) {
274 netif_err(efx, probe, efx->net_dev,
275 "Siena FPGA not supported\n");
276 rc = -ENODEV;
277 goto fail1;
278 }
279
280 efx->max_channels = EFX_MAX_CHANNELS;
281 efx->max_vis = EFX_MAX_CHANNELS;
282 efx->max_tx_channels = EFX_MAX_CHANNELS;
283 efx->tx_queues_per_channel = 4;
284
285 efx_reado(efx, ®, FR_AZ_CS_DEBUG);
286 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
287
288 rc = efx_mcdi_init(efx);
289 if (rc)
290 goto fail1;
291
292
293 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
294 if (rc) {
295 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
296 goto fail3;
297 }
298
299 siena_init_wol(efx);
300
301
302 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
303 GFP_KERNEL);
304 if (rc)
305 goto fail4;
306 BUG_ON(efx->irq_status.dma_addr & 0x0f);
307
308 netif_dbg(efx, probe, efx->net_dev,
309 "INT_KER at %llx (virt %p phys %llx)\n",
310 (unsigned long long)efx->irq_status.dma_addr,
311 efx->irq_status.addr,
312 (unsigned long long)virt_to_phys(efx->irq_status.addr));
313
314
315 rc = siena_probe_nvconfig(efx);
316 if (rc == -EINVAL) {
317 netif_err(efx, probe, efx->net_dev,
318 "NVRAM is invalid therefore using defaults\n");
319 efx->phy_type = PHY_TYPE_NONE;
320 efx->mdio.prtad = MDIO_PRTAD_NONE;
321 } else if (rc) {
322 goto fail5;
323 }
324
325 rc = efx_mcdi_mon_probe(efx);
326 if (rc)
327 goto fail5;
328
329#ifdef CONFIG_SFC_SRIOV
330 efx_siena_sriov_probe(efx);
331#endif
332 efx_ptp_defer_probe_with_channel(efx);
333
334 return 0;
335
336fail5:
337 efx_nic_free_buffer(efx, &efx->irq_status);
338fail4:
339fail3:
340 efx_mcdi_detach(efx);
341 efx_mcdi_fini(efx);
342fail1:
343 kfree(efx->nic_data);
344 return rc;
345}
346
347static int siena_rx_pull_rss_config(struct efx_nic *efx)
348{
349 efx_oword_t temp;
350
351
352
353
354
355 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
356 memcpy(efx->rss_context.rx_hash_key, &temp, sizeof(temp));
357 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
358 memcpy(efx->rss_context.rx_hash_key + sizeof(temp), &temp, sizeof(temp));
359 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
360 memcpy(efx->rss_context.rx_hash_key + 2 * sizeof(temp), &temp,
361 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
362 efx_farch_rx_pull_indir_table(efx);
363 return 0;
364}
365
366static int siena_rx_push_rss_config(struct efx_nic *efx, bool user,
367 const u32 *rx_indir_table, const u8 *key)
368{
369 efx_oword_t temp;
370
371
372 if (key)
373 memcpy(efx->rss_context.rx_hash_key, key, sizeof(temp));
374 memcpy(&temp, efx->rss_context.rx_hash_key, sizeof(temp));
375 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
376
377
378 BUILD_BUG_ON(sizeof(efx->rss_context.rx_hash_key) <
379 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
380 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
381 memcpy(&temp, efx->rss_context.rx_hash_key, sizeof(temp));
382 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
383 memcpy(&temp, efx->rss_context.rx_hash_key + sizeof(temp), sizeof(temp));
384 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
385 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
386 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
387 memcpy(&temp, efx->rss_context.rx_hash_key + 2 * sizeof(temp),
388 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
389 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
390
391 memcpy(efx->rss_context.rx_indir_table, rx_indir_table,
392 sizeof(efx->rss_context.rx_indir_table));
393 efx_farch_rx_push_indir_table(efx);
394
395 return 0;
396}
397
398
399
400
401
402static int siena_init_nic(struct efx_nic *efx)
403{
404 efx_oword_t temp;
405 int rc;
406
407
408 rc = efx_mcdi_handle_assertion(efx);
409 if (rc)
410 return rc;
411
412
413 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
414 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
415 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
416
417
418
419
420 efx_reado(efx, &temp, FR_AZ_TX_CFG);
421 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
422 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
423 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
424
425 efx_reado(efx, &temp, FR_AZ_RX_CFG);
426 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
427 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
428
429
430
431 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
432 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
433 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
434 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
435 EFX_RX_USR_BUF_SIZE >> 5);
436 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
437
438 siena_rx_push_rss_config(efx, false, efx->rss_context.rx_indir_table, NULL);
439 efx->rss_context.context_id = 0;
440
441
442 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
443 if (rc)
444 return rc;
445
446
447 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
448 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
449
450 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
451 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
452
453 efx_farch_init_common(efx);
454 return 0;
455}
456
457static void siena_remove_nic(struct efx_nic *efx)
458{
459 efx_mcdi_mon_remove(efx);
460
461 efx_nic_free_buffer(efx, &efx->irq_status);
462
463 efx_mcdi_reset(efx, RESET_TYPE_ALL);
464
465 efx_mcdi_detach(efx);
466 efx_mcdi_fini(efx);
467
468
469 kfree(efx->nic_data);
470 efx->nic_data = NULL;
471}
472
473#define SIENA_DMA_STAT(ext_name, mcdi_name) \
474 [SIENA_STAT_ ## ext_name] = \
475 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
476#define SIENA_OTHER_STAT(ext_name) \
477 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
478#define GENERIC_SW_STAT(ext_name) \
479 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
480
481static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
482 SIENA_DMA_STAT(tx_bytes, TX_BYTES),
483 SIENA_OTHER_STAT(tx_good_bytes),
484 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
485 SIENA_DMA_STAT(tx_packets, TX_PKTS),
486 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
487 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
488 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
489 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
490 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
491 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
492 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
493 SIENA_DMA_STAT(tx_64, TX_64_PKTS),
494 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
495 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
496 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
497 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
498 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
499 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
500 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
501 SIENA_OTHER_STAT(tx_collision),
502 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
503 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
504 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
505 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
506 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
507 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
508 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
509 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
510 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
511 SIENA_DMA_STAT(rx_bytes, RX_BYTES),
512 SIENA_OTHER_STAT(rx_good_bytes),
513 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
514 SIENA_DMA_STAT(rx_packets, RX_PKTS),
515 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
516 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
517 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
518 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
519 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
520 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
521 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
522 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
523 SIENA_DMA_STAT(rx_64, RX_64_PKTS),
524 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
525 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
526 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
527 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
528 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
529 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
530 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
531 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
532 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
533 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
534 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
535 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
536 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
537 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
538 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
539 GENERIC_SW_STAT(rx_nodesc_trunc),
540 GENERIC_SW_STAT(rx_noskb_drops),
541};
542static const unsigned long siena_stat_mask[] = {
543 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
544};
545
546static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
547{
548 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
549 siena_stat_mask, names);
550}
551
552static int siena_try_update_nic_stats(struct efx_nic *efx)
553{
554 struct siena_nic_data *nic_data = efx->nic_data;
555 u64 *stats = nic_data->stats;
556 __le64 *dma_stats;
557 __le64 generation_start, generation_end;
558
559 dma_stats = efx->stats_buffer.addr;
560
561 generation_end = dma_stats[efx->num_mac_stats - 1];
562 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
563 return 0;
564 rmb();
565 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
566 stats, efx->stats_buffer.addr, false);
567 rmb();
568 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
569 if (generation_end != generation_start)
570 return -EAGAIN;
571
572
573 efx_nic_fix_nodesc_drop_stat(efx,
574 &stats[SIENA_STAT_rx_nodesc_drop_cnt]);
575 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
576 stats[SIENA_STAT_tx_bytes] -
577 stats[SIENA_STAT_tx_bad_bytes]);
578 stats[SIENA_STAT_tx_collision] =
579 stats[SIENA_STAT_tx_single_collision] +
580 stats[SIENA_STAT_tx_multiple_collision] +
581 stats[SIENA_STAT_tx_excessive_collision] +
582 stats[SIENA_STAT_tx_late_collision];
583 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
584 stats[SIENA_STAT_rx_bytes] -
585 stats[SIENA_STAT_rx_bad_bytes]);
586 efx_update_sw_stats(efx, stats);
587 return 0;
588}
589
590static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
591 struct rtnl_link_stats64 *core_stats)
592{
593 struct siena_nic_data *nic_data = efx->nic_data;
594 u64 *stats = nic_data->stats;
595 int retry;
596
597
598
599 for (retry = 0; retry < 100; ++retry) {
600 if (siena_try_update_nic_stats(efx) == 0)
601 break;
602 udelay(100);
603 }
604
605 if (full_stats)
606 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
607
608 if (core_stats) {
609 core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
610 core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
611 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
612 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
613 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt] +
614 stats[GENERIC_STAT_rx_nodesc_trunc] +
615 stats[GENERIC_STAT_rx_noskb_drops];
616 core_stats->multicast = stats[SIENA_STAT_rx_multicast];
617 core_stats->collisions = stats[SIENA_STAT_tx_collision];
618 core_stats->rx_length_errors =
619 stats[SIENA_STAT_rx_gtjumbo] +
620 stats[SIENA_STAT_rx_length_error];
621 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
622 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
623 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
624 core_stats->tx_window_errors =
625 stats[SIENA_STAT_tx_late_collision];
626
627 core_stats->rx_errors = (core_stats->rx_length_errors +
628 core_stats->rx_crc_errors +
629 core_stats->rx_frame_errors +
630 stats[SIENA_STAT_rx_symbol_error]);
631 core_stats->tx_errors = (core_stats->tx_window_errors +
632 stats[SIENA_STAT_tx_bad]);
633 }
634
635 return SIENA_STAT_COUNT;
636}
637
638static int siena_mac_reconfigure(struct efx_nic *efx, bool mtu_only __always_unused)
639{
640 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
641 int rc;
642
643 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
644 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
645 sizeof(efx->multicast_hash));
646
647 efx_farch_filter_sync_rx_mode(efx);
648
649 WARN_ON(!mutex_is_locked(&efx->mac_lock));
650
651 rc = efx_mcdi_set_mac(efx);
652 if (rc != 0)
653 return rc;
654
655 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
656 efx->multicast_hash.byte, sizeof(efx->multicast_hash));
657 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
658 inbuf, sizeof(inbuf), NULL, 0, NULL);
659}
660
661
662
663
664
665
666
667
668static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
669{
670 struct siena_nic_data *nic_data = efx->nic_data;
671
672 wol->supported = WAKE_MAGIC;
673 if (nic_data->wol_filter_id != -1)
674 wol->wolopts = WAKE_MAGIC;
675 else
676 wol->wolopts = 0;
677 memset(&wol->sopass, 0, sizeof(wol->sopass));
678}
679
680
681static int siena_set_wol(struct efx_nic *efx, u32 type)
682{
683 struct siena_nic_data *nic_data = efx->nic_data;
684 int rc;
685
686 if (type & ~WAKE_MAGIC)
687 return -EINVAL;
688
689 if (type & WAKE_MAGIC) {
690 if (nic_data->wol_filter_id != -1)
691 efx_mcdi_wol_filter_remove(efx,
692 nic_data->wol_filter_id);
693 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
694 &nic_data->wol_filter_id);
695 if (rc)
696 goto fail;
697
698 pci_wake_from_d3(efx->pci_dev, true);
699 } else {
700 rc = efx_mcdi_wol_filter_reset(efx);
701 nic_data->wol_filter_id = -1;
702 pci_wake_from_d3(efx->pci_dev, false);
703 if (rc)
704 goto fail;
705 }
706
707 return 0;
708 fail:
709 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
710 __func__, type, rc);
711 return rc;
712}
713
714
715static void siena_init_wol(struct efx_nic *efx)
716{
717 struct siena_nic_data *nic_data = efx->nic_data;
718 int rc;
719
720 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
721
722 if (rc != 0) {
723
724
725 efx_mcdi_wol_filter_reset(efx);
726 nic_data->wol_filter_id = -1;
727 } else if (nic_data->wol_filter_id != -1) {
728 pci_wake_from_d3(efx->pci_dev, true);
729 }
730}
731
732
733
734
735
736
737
738
739#define MCDI_PDU(efx) \
740 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
741#define MCDI_DOORBELL(efx) \
742 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
743#define MCDI_STATUS(efx) \
744 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
745
746static void siena_mcdi_request(struct efx_nic *efx,
747 const efx_dword_t *hdr, size_t hdr_len,
748 const efx_dword_t *sdu, size_t sdu_len)
749{
750 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
751 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
752 unsigned int i;
753 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
754
755 EFX_WARN_ON_PARANOID(hdr_len != 4);
756
757 efx_writed(efx, hdr, pdu);
758
759 for (i = 0; i < inlen_dw; i++)
760 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
761
762
763 wmb();
764
765
766 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
767}
768
769static bool siena_mcdi_poll_response(struct efx_nic *efx)
770{
771 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
772 efx_dword_t hdr;
773
774 efx_readd(efx, &hdr, pdu);
775
776
777
778
779
780 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
781 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
782}
783
784static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
785 size_t offset, size_t outlen)
786{
787 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
788 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
789 int i;
790
791 for (i = 0; i < outlen_dw; i++)
792 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
793}
794
795static int siena_mcdi_poll_reboot(struct efx_nic *efx)
796{
797 struct siena_nic_data *nic_data = efx->nic_data;
798 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
799 efx_dword_t reg;
800 u32 value;
801
802 efx_readd(efx, ®, addr);
803 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
804
805 if (value == 0)
806 return 0;
807
808 EFX_ZERO_DWORD(reg);
809 efx_writed(efx, ®, addr);
810
811
812
813
814 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
815 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
816
817 if (value == MC_STATUS_DWORD_ASSERT)
818 return -EINTR;
819 else
820 return -EIO;
821}
822
823
824
825
826
827
828
829
830#ifdef CONFIG_SFC_MTD
831
832struct siena_nvram_type_info {
833 int port;
834 const char *name;
835};
836
837static const struct siena_nvram_type_info siena_nvram_types[] = {
838 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
839 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
840 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
841 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
842 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
843 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
844 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
845 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
846 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
847 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
848 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
849 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
850 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
851};
852
853static int siena_mtd_probe_partition(struct efx_nic *efx,
854 struct efx_mcdi_mtd_partition *part,
855 unsigned int type)
856{
857 const struct siena_nvram_type_info *info;
858 size_t size, erase_size;
859 bool protected;
860 int rc;
861
862 if (type >= ARRAY_SIZE(siena_nvram_types) ||
863 siena_nvram_types[type].name == NULL)
864 return -ENODEV;
865
866 info = &siena_nvram_types[type];
867
868 if (info->port != efx_port_num(efx))
869 return -ENODEV;
870
871 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
872 if (rc)
873 return rc;
874 if (protected)
875 return -ENODEV;
876
877 part->nvram_type = type;
878 part->common.dev_type_name = "Siena NVRAM manager";
879 part->common.type_name = info->name;
880
881 part->common.mtd.type = MTD_NORFLASH;
882 part->common.mtd.flags = MTD_CAP_NORFLASH;
883 part->common.mtd.size = size;
884 part->common.mtd.erasesize = erase_size;
885
886 return 0;
887}
888
889static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
890 struct efx_mcdi_mtd_partition *parts,
891 size_t n_parts)
892{
893 uint16_t fw_subtype_list[
894 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
895 size_t i;
896 int rc;
897
898 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
899 if (rc)
900 return rc;
901
902 for (i = 0; i < n_parts; i++)
903 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
904
905 return 0;
906}
907
908static int siena_mtd_probe(struct efx_nic *efx)
909{
910 struct efx_mcdi_mtd_partition *parts;
911 u32 nvram_types;
912 unsigned int type;
913 size_t n_parts;
914 int rc;
915
916 ASSERT_RTNL();
917
918 rc = efx_mcdi_nvram_types(efx, &nvram_types);
919 if (rc)
920 return rc;
921
922 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
923 if (!parts)
924 return -ENOMEM;
925
926 type = 0;
927 n_parts = 0;
928
929 while (nvram_types != 0) {
930 if (nvram_types & 1) {
931 rc = siena_mtd_probe_partition(efx, &parts[n_parts],
932 type);
933 if (rc == 0)
934 n_parts++;
935 else if (rc != -ENODEV)
936 goto fail;
937 }
938 type++;
939 nvram_types >>= 1;
940 }
941
942 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
943 if (rc)
944 goto fail;
945
946 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
947fail:
948 if (rc)
949 kfree(parts);
950 return rc;
951}
952
953#endif
954
955static unsigned int siena_check_caps(const struct efx_nic *efx,
956 u8 flag, u32 offset)
957{
958
959 return 0;
960}
961
962static unsigned int efx_siena_recycle_ring_size(const struct efx_nic *efx)
963{
964
965 return EFX_RECYCLE_RING_SIZE_10G;
966}
967
968
969
970
971
972
973
974
975const struct efx_nic_type siena_a0_nic_type = {
976 .is_vf = false,
977 .mem_bar = siena_mem_bar,
978 .mem_map_size = siena_mem_map_size,
979 .probe = siena_probe_nic,
980 .remove = siena_remove_nic,
981 .init = siena_init_nic,
982 .dimension_resources = siena_dimension_resources,
983 .fini = efx_port_dummy_op_void,
984#ifdef CONFIG_EEH
985 .monitor = siena_monitor,
986#else
987 .monitor = NULL,
988#endif
989 .map_reset_reason = efx_mcdi_map_reset_reason,
990 .map_reset_flags = siena_map_reset_flags,
991 .reset = efx_mcdi_reset,
992 .probe_port = efx_mcdi_port_probe,
993 .remove_port = efx_mcdi_port_remove,
994 .fini_dmaq = efx_farch_fini_dmaq,
995 .prepare_flush = siena_prepare_flush,
996 .finish_flush = siena_finish_flush,
997 .prepare_flr = efx_port_dummy_op_void,
998 .finish_flr = efx_farch_finish_flr,
999 .describe_stats = siena_describe_nic_stats,
1000 .update_stats = siena_update_nic_stats,
1001 .start_stats = efx_mcdi_mac_start_stats,
1002 .pull_stats = efx_mcdi_mac_pull_stats,
1003 .stop_stats = efx_mcdi_mac_stop_stats,
1004 .push_irq_moderation = siena_push_irq_moderation,
1005 .reconfigure_mac = siena_mac_reconfigure,
1006 .check_mac_fault = efx_mcdi_mac_check_fault,
1007 .reconfigure_port = efx_mcdi_port_reconfigure,
1008 .get_wol = siena_get_wol,
1009 .set_wol = siena_set_wol,
1010 .resume_wol = siena_init_wol,
1011 .test_chip = siena_test_chip,
1012 .test_nvram = efx_mcdi_nvram_test_all,
1013 .mcdi_request = siena_mcdi_request,
1014 .mcdi_poll_response = siena_mcdi_poll_response,
1015 .mcdi_read_response = siena_mcdi_read_response,
1016 .mcdi_poll_reboot = siena_mcdi_poll_reboot,
1017 .irq_enable_master = efx_farch_irq_enable_master,
1018 .irq_test_generate = efx_farch_irq_test_generate,
1019 .irq_disable_non_ev = efx_farch_irq_disable_master,
1020 .irq_handle_msi = efx_farch_msi_interrupt,
1021 .irq_handle_legacy = efx_farch_legacy_interrupt,
1022 .tx_probe = efx_farch_tx_probe,
1023 .tx_init = efx_farch_tx_init,
1024 .tx_remove = efx_farch_tx_remove,
1025 .tx_write = efx_farch_tx_write,
1026 .tx_limit_len = efx_farch_tx_limit_len,
1027 .tx_enqueue = __efx_enqueue_skb,
1028 .rx_push_rss_config = siena_rx_push_rss_config,
1029 .rx_pull_rss_config = siena_rx_pull_rss_config,
1030 .rx_probe = efx_farch_rx_probe,
1031 .rx_init = efx_farch_rx_init,
1032 .rx_remove = efx_farch_rx_remove,
1033 .rx_write = efx_farch_rx_write,
1034 .rx_defer_refill = efx_farch_rx_defer_refill,
1035 .rx_packet = __efx_rx_packet,
1036 .ev_probe = efx_farch_ev_probe,
1037 .ev_init = efx_farch_ev_init,
1038 .ev_fini = efx_farch_ev_fini,
1039 .ev_remove = efx_farch_ev_remove,
1040 .ev_process = efx_farch_ev_process,
1041 .ev_read_ack = efx_farch_ev_read_ack,
1042 .ev_test_generate = efx_farch_ev_test_generate,
1043 .filter_table_probe = efx_farch_filter_table_probe,
1044 .filter_table_restore = efx_farch_filter_table_restore,
1045 .filter_table_remove = efx_farch_filter_table_remove,
1046 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
1047 .filter_insert = efx_farch_filter_insert,
1048 .filter_remove_safe = efx_farch_filter_remove_safe,
1049 .filter_get_safe = efx_farch_filter_get_safe,
1050 .filter_clear_rx = efx_farch_filter_clear_rx,
1051 .filter_count_rx_used = efx_farch_filter_count_rx_used,
1052 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
1053 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
1054#ifdef CONFIG_RFS_ACCEL
1055 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
1056#endif
1057#ifdef CONFIG_SFC_MTD
1058 .mtd_probe = siena_mtd_probe,
1059 .mtd_rename = efx_mcdi_mtd_rename,
1060 .mtd_read = efx_mcdi_mtd_read,
1061 .mtd_erase = efx_mcdi_mtd_erase,
1062 .mtd_write = efx_mcdi_mtd_write,
1063 .mtd_sync = efx_mcdi_mtd_sync,
1064#endif
1065 .ptp_write_host_time = siena_ptp_write_host_time,
1066 .ptp_set_ts_config = siena_ptp_set_ts_config,
1067#ifdef CONFIG_SFC_SRIOV
1068 .sriov_configure = efx_siena_sriov_configure,
1069 .sriov_init = efx_siena_sriov_init,
1070 .sriov_fini = efx_siena_sriov_fini,
1071 .sriov_wanted = efx_siena_sriov_wanted,
1072 .sriov_reset = efx_siena_sriov_reset,
1073 .sriov_flr = efx_siena_sriov_flr,
1074 .sriov_set_vf_mac = efx_siena_sriov_set_vf_mac,
1075 .sriov_set_vf_vlan = efx_siena_sriov_set_vf_vlan,
1076 .sriov_set_vf_spoofchk = efx_siena_sriov_set_vf_spoofchk,
1077 .sriov_get_vf_config = efx_siena_sriov_get_vf_config,
1078 .vswitching_probe = efx_port_dummy_op_int,
1079 .vswitching_restore = efx_port_dummy_op_int,
1080 .vswitching_remove = efx_port_dummy_op_void,
1081 .set_mac_address = efx_siena_sriov_mac_address_changed,
1082#endif
1083
1084 .revision = EFX_REV_SIENA_A0,
1085 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1086 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1087 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1088 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1089 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1090 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1091 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
1092 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
1093 .rx_buffer_padding = 0,
1094 .can_rx_scatter = true,
1095 .option_descriptors = false,
1096 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
1097 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
1098 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1099 NETIF_F_RXHASH | NETIF_F_NTUPLE),
1100 .mcdi_max_ver = 1,
1101 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
1102 .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE |
1103 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT |
1104 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT),
1105 .rx_hash_key_size = 16,
1106 .check_caps = siena_check_caps,
1107 .sensor_event = efx_mcdi_sensor_event,
1108 .rx_recycle_ring_size = efx_siena_recycle_ring_size,
1109};
1110
