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55#ifndef _3W_XXXX_H
56#define _3W_XXXX_H
57
58#include <linux/types.h>
59
60
61static char *tw_aen_string[] = {
62 [0x000] = "INFO: AEN queue empty",
63 [0x001] = "INFO: Soft reset occurred",
64 [0x002] = "ERROR: Unit degraded: Unit #",
65 [0x003] = "ERROR: Controller error",
66 [0x004] = "ERROR: Rebuild failed: Unit #",
67 [0x005] = "INFO: Rebuild complete: Unit #",
68 [0x006] = "ERROR: Incomplete unit detected: Unit #",
69 [0x007] = "INFO: Initialization complete: Unit #",
70 [0x008] = "WARNING: Unclean shutdown detected: Unit #",
71 [0x009] = "WARNING: ATA port timeout: Port #",
72 [0x00A] = "ERROR: Drive error: Port #",
73 [0x00B] = "INFO: Rebuild started: Unit #",
74 [0x00C] = "INFO: Initialization started: Unit #",
75 [0x00D] = "ERROR: Logical unit deleted: Unit #",
76 [0x00F] = "WARNING: SMART threshold exceeded: Port #",
77 [0x021] = "WARNING: ATA UDMA downgrade: Port #",
78 [0x022] = "WARNING: ATA UDMA upgrade: Port #",
79 [0x023] = "WARNING: Sector repair occurred: Port #",
80 [0x024] = "ERROR: SBUF integrity check failure",
81 [0x025] = "ERROR: Lost cached write: Port #",
82 [0x026] = "ERROR: Drive ECC error detected: Port #",
83 [0x027] = "ERROR: DCB checksum error: Port #",
84 [0x028] = "ERROR: DCB unsupported version: Port #",
85 [0x029] = "INFO: Verify started: Unit #",
86 [0x02A] = "ERROR: Verify failed: Port #",
87 [0x02B] = "INFO: Verify complete: Unit #",
88 [0x02C] = "WARNING: Overwrote bad sector during rebuild: Port #",
89 [0x02D] = "ERROR: Encountered bad sector during rebuild: Port #",
90 [0x02E] = "ERROR: Replacement drive is too small: Port #",
91 [0x02F] = "WARNING: Verify error: Unit not previously initialized: Unit #",
92 [0x030] = "ERROR: Drive not supported: Port #"
93};
94
95
96
97
98
99static unsigned char tw_sense_table[][4] =
100{
101
102
103 {0x01, 0x03, 0x13, 0x00},
104 {0x04, 0x0b, 0x00, 0x00},
105 {0x10, 0x0b, 0x14, 0x00},
106 {0x40, 0x03, 0x11, 0x00},
107 {0x61, 0x04, 0x00, 0x00},
108 {0x84, 0x0b, 0x47, 0x00},
109 {0xd0, 0x0b, 0x00, 0x00},
110 {0xd1, 0x0b, 0x00, 0x00},
111 {0x37, 0x02, 0x04, 0x00},
112 {0x09, 0x02, 0x04, 0x00},
113
114
115
116 {0x51, 0x0b, 0x00, 0x00}
117};
118
119
120#define TW_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
121#define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
122#define TW_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
123#define TW_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
124#define TW_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
125#define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
126#define TW_CONTROL_CLEAR_ERROR_STATUS 0x00000200
127#define TW_CONTROL_ISSUE_SOFT_RESET 0x00000100
128#define TW_CONTROL_ENABLE_INTERRUPTS 0x00000080
129#define TW_CONTROL_DISABLE_INTERRUPTS 0x00000040
130#define TW_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
131#define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000
132#define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000
133#define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000
134#define TW_CONTROL_CLEAR_SBUF_WRITE_ERROR 0x00000008
135
136
137#define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000
138#define TW_STATUS_MINOR_VERSION_MASK 0x0F000000
139#define TW_STATUS_PCI_PARITY_ERROR 0x00800000
140#define TW_STATUS_QUEUE_ERROR 0x00400000
141#define TW_STATUS_MICROCONTROLLER_ERROR 0x00200000
142#define TW_STATUS_PCI_ABORT 0x00100000
143#define TW_STATUS_HOST_INTERRUPT 0x00080000
144#define TW_STATUS_ATTENTION_INTERRUPT 0x00040000
145#define TW_STATUS_COMMAND_INTERRUPT 0x00020000
146#define TW_STATUS_RESPONSE_INTERRUPT 0x00010000
147#define TW_STATUS_COMMAND_QUEUE_FULL 0x00008000
148#define TW_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
149#define TW_STATUS_MICROCONTROLLER_READY 0x00002000
150#define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
151#define TW_STATUS_ALL_INTERRUPTS 0x000F0000
152#define TW_STATUS_CLEARABLE_BITS 0x00D00000
153#define TW_STATUS_EXPECTED_BITS 0x00002000
154#define TW_STATUS_UNEXPECTED_BITS 0x00F00008
155#define TW_STATUS_SBUF_WRITE_ERROR 0x00000008
156#define TW_STATUS_VALID_INTERRUPT 0x00DF0008
157
158
159#define TW_RESPONSE_ID_MASK 0x00000FF0
160
161
162#define TW_IO_ADDRESS_RANGE 0x10
163#define TW_DEVICE_NAME "3ware Storage Controller"
164#define TW_VENDOR_ID (0x13C1)
165#define TW_DEVICE_ID (0x1000)
166#define TW_DEVICE_ID2 (0x1001)
167#define TW_NUMDEVICES 2
168#define TW_PCI_CLEAR_PARITY_ERRORS 0xc100
169#define TW_PCI_CLEAR_PCI_ABORT 0x2000
170
171
172#define TW_OP_NOP 0x0
173#define TW_OP_INIT_CONNECTION 0x1
174#define TW_OP_READ 0x2
175#define TW_OP_WRITE 0x3
176#define TW_OP_VERIFY 0x4
177#define TW_OP_GET_PARAM 0x12
178#define TW_OP_SET_PARAM 0x13
179#define TW_OP_SECTOR_INFO 0x1a
180#define TW_OP_AEN_LISTEN 0x1c
181#define TW_OP_FLUSH_CACHE 0x0e
182#define TW_CMD_PACKET 0x1d
183#define TW_CMD_PACKET_WITH_DATA 0x1f
184
185
186#define TW_AEN_QUEUE_EMPTY 0x0000
187#define TW_AEN_SOFT_RESET 0x0001
188#define TW_AEN_DEGRADED_MIRROR 0x0002
189#define TW_AEN_CONTROLLER_ERROR 0x0003
190#define TW_AEN_REBUILD_FAIL 0x0004
191#define TW_AEN_REBUILD_DONE 0x0005
192#define TW_AEN_QUEUE_FULL 0x00ff
193#define TW_AEN_TABLE_UNDEFINED 0x15
194#define TW_AEN_APORT_TIMEOUT 0x0009
195#define TW_AEN_DRIVE_ERROR 0x000A
196#define TW_AEN_SMART_FAIL 0x000F
197#define TW_AEN_SBUF_FAIL 0x0024
198
199
200#define TW_ALIGNMENT_6000 64
201#define TW_ALIGNMENT_7000 4
202#define TW_MAX_UNITS 16
203#define TW_COMMAND_ALIGNMENT_MASK 0x1ff
204#define TW_INIT_MESSAGE_CREDITS 0x100
205#define TW_INIT_COMMAND_PACKET_SIZE 0x3
206#define TW_POLL_MAX_RETRIES 20000
207#define TW_MAX_SGL_LENGTH 62
208#define TW_ATA_PASS_SGL_MAX 60
209#define TW_Q_LENGTH 256
210#define TW_Q_START 0
211#define TW_MAX_SLOT 32
212#define TW_MAX_PCI_BUSES 255
213#define TW_MAX_RESET_TRIES 3
214#define TW_UNIT_INFORMATION_TABLE_BASE 0x300
215#define TW_MAX_CMDS_PER_LUN 254
216
217
218#define TW_BLOCK_SIZE 0x200
219#define TW_IOCTL 0x80
220#define TW_UNIT_ONLINE 1
221#define TW_IN_INTR 1
222#define TW_IN_RESET 2
223#define TW_IN_CHRDEV_IOCTL 3
224#define TW_MAX_SECTORS 256
225#define TW_MAX_IOCTL_SECTORS 512
226#define TW_AEN_WAIT_TIME 1000
227#define TW_IOCTL_WAIT_TIME (1 * HZ)
228#define TW_ISR_DONT_COMPLETE 2
229#define TW_ISR_DONT_RESULT 3
230#define TW_IOCTL_TIMEOUT 25
231#define TW_IOCTL_CHRDEV_TIMEOUT 60
232#define TW_IOCTL_CHRDEV_FREE -1
233#define TW_MAX_CDB_LEN 16
234
235
236
237
238#define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
239#define TW_SGL_OUT(x) ((x >> 5) & 0x7)
240
241
242#define TW_RESID_OUT(x) ((x >> 4) & 0xff)
243
244
245#define TW_UNITHOST_IN(x,y) ((x << 4) | ( y & 0xf))
246#define TW_UNIT_OUT(x) (x & 0xf)
247
248
249#define TW_CONTROL_REG_ADDR(x) (x->base_addr)
250#define TW_STATUS_REG_ADDR(x) (x->base_addr + 0x4)
251#define TW_COMMAND_QUEUE_REG_ADDR(x) (x->base_addr + 0x8)
252#define TW_RESPONSE_QUEUE_REG_ADDR(x) (x->base_addr + 0xC)
253#define TW_CLEAR_ALL_INTERRUPTS(x) \
254 (outl(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
255#define TW_CLEAR_ATTENTION_INTERRUPT(x) \
256 (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
257#define TW_CLEAR_HOST_INTERRUPT(x) \
258 (outl(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
259#define TW_DISABLE_INTERRUPTS(x) \
260 (outl(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
261#define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) \
262 (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
263 TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | \
264 TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
265#define TW_MASK_COMMAND_INTERRUPT(x) \
266 (outl(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
267#define TW_UNMASK_COMMAND_INTERRUPT(x) \
268 (outl(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
269#define TW_SOFT_RESET(x) (outl(TW_CONTROL_ISSUE_SOFT_RESET | \
270 TW_CONTROL_CLEAR_HOST_INTERRUPT | \
271 TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
272 TW_CONTROL_MASK_COMMAND_INTERRUPT | \
273 TW_CONTROL_MASK_RESPONSE_INTERRUPT | \
274 TW_CONTROL_CLEAR_ERROR_STATUS | \
275 TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
276#define TW_STATUS_ERRORS(x) \
277 (((x & TW_STATUS_PCI_ABORT) || \
278 (x & TW_STATUS_PCI_PARITY_ERROR) || \
279 (x & TW_STATUS_QUEUE_ERROR) || \
280 (x & TW_STATUS_MICROCONTROLLER_ERROR)) && \
281 (x & TW_STATUS_MICROCONTROLLER_READY))
282
283#ifdef TW_DEBUG
284#define dprintk(msg...) printk(msg)
285#else
286#define dprintk(msg...) do { } while(0)
287#endif
288
289#pragma pack(1)
290
291
292typedef struct TAG_TW_SG_Entry {
293 u32 address;
294 u32 length;
295} TW_SG_Entry;
296
297typedef unsigned char TW_Sector[512];
298
299
300typedef struct TW_Command {
301 unsigned char opcode__sgloffset;
302 unsigned char size;
303 unsigned char request_id;
304 unsigned char unit__hostid;
305
306 unsigned char status;
307 unsigned char flags;
308 union {
309 unsigned short block_count;
310 unsigned short parameter_count;
311 unsigned short message_credits;
312 } byte6;
313 union {
314 struct {
315 u32 lba;
316 TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
317 u32 padding;
318 } io;
319 struct {
320 TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
321 u32 padding[2];
322 } param;
323 struct {
324 u32 response_queue_pointer;
325 u32 padding[125];
326 } init_connection;
327 struct {
328 char version[504];
329 } ioctl_miniport_version;
330 } byte8;
331} TW_Command;
332
333#pragma pack()
334
335typedef struct TAG_TW_Ioctl {
336 unsigned char opcode;
337 unsigned short table_id;
338 unsigned char parameter_id;
339 unsigned char parameter_size_bytes;
340 unsigned char unit_index;
341 unsigned char data[1];
342} TW_Ioctl;
343
344#pragma pack(1)
345
346
347typedef struct TAG_TW_New_Ioctl {
348 unsigned int data_buffer_length;
349 unsigned char padding [508];
350 TW_Command firmware_command;
351 char data_buffer[1];
352} TW_New_Ioctl;
353
354
355typedef struct {
356 unsigned short table_id;
357 unsigned char parameter_id;
358 unsigned char parameter_size_bytes;
359 unsigned char data[1];
360} TW_Param, *PTW_Param;
361
362
363typedef union TAG_TW_Response_Queue {
364 u32 response_id;
365 u32 value;
366} TW_Response_Queue;
367
368typedef int TW_Cmd_State;
369
370#define TW_S_INITIAL 0x1
371#define TW_S_STARTED 0x2
372#define TW_S_POSTED 0x4
373#define TW_S_PENDING 0x8
374#define TW_S_COMPLETED 0x10
375#define TW_S_FINISHED 0x20
376#define TW_START_MASK (TW_S_STARTED | TW_S_POSTED | TW_S_PENDING | TW_S_COMPLETED)
377
378
379typedef struct TAG_TW_Passthru
380{
381 unsigned char opcode__sgloffset;
382 unsigned char size;
383 unsigned char request_id;
384 unsigned char aport__hostid;
385 unsigned char status;
386 unsigned char flags;
387 unsigned short param;
388 unsigned short features;
389 unsigned short sector_count;
390 unsigned short sector_num;
391 unsigned short cylinder_lo;
392 unsigned short cylinder_hi;
393 unsigned char drive_head;
394 unsigned char command;
395 TW_SG_Entry sg_list[TW_ATA_PASS_SGL_MAX];
396 unsigned char padding[12];
397} TW_Passthru;
398
399#pragma pack()
400
401typedef struct TAG_TW_Device_Extension {
402 u32 base_addr;
403 unsigned long *alignment_virtual_address[TW_Q_LENGTH];
404 unsigned long alignment_physical_address[TW_Q_LENGTH];
405 int is_unit_present[TW_MAX_UNITS];
406 unsigned long *command_packet_virtual_address[TW_Q_LENGTH];
407 unsigned long command_packet_physical_address[TW_Q_LENGTH];
408 struct pci_dev *tw_pci_dev;
409 struct scsi_cmnd *srb[TW_Q_LENGTH];
410 unsigned char free_queue[TW_Q_LENGTH];
411 unsigned char free_head;
412 unsigned char free_tail;
413 unsigned char pending_queue[TW_Q_LENGTH];
414 unsigned char pending_head;
415 unsigned char pending_tail;
416 TW_Cmd_State state[TW_Q_LENGTH];
417 u32 posted_request_count;
418 u32 max_posted_request_count;
419 u32 request_count_marked_pending;
420 u32 pending_request_count;
421 u32 max_pending_request_count;
422 u32 max_sgl_entries;
423 u32 sgl_entries;
424 u32 num_resets;
425 u32 sector_count;
426 u32 max_sector_count;
427 u32 aen_count;
428 struct Scsi_Host *host;
429 struct mutex ioctl_lock;
430 unsigned short aen_queue[TW_Q_LENGTH];
431 unsigned char aen_head;
432 unsigned char aen_tail;
433 volatile long flags;
434 int reset_print;
435 volatile int chrdev_request_id;
436 wait_queue_head_t ioctl_wqueue;
437} TW_Device_Extension;
438
439#endif
440