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8#include <linux/spinlock.h>
9#include <linux/interrupt.h>
10#include <linux/delay.h>
11#include <linux/errno.h>
12#include <linux/err.h>
13#include <linux/clk.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17
18#include <linux/spi/spi.h>
19#include <linux/spi/spi_bitbang.h>
20#include <linux/spi/s3c24xx.h>
21#include <linux/spi/s3c24xx-fiq.h>
22#include <linux/module.h>
23
24#include <asm/fiq.h>
25
26#include "spi-s3c24xx-regs.h"
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33
34
35struct s3c24xx_spi_devstate {
36 unsigned int hz;
37 unsigned int mode;
38 u8 spcon;
39 u8 sppre;
40};
41
42enum spi_fiq_mode {
43 FIQ_MODE_NONE = 0,
44 FIQ_MODE_TX = 1,
45 FIQ_MODE_RX = 2,
46 FIQ_MODE_TXRX = 3,
47};
48
49struct s3c24xx_spi {
50
51 struct spi_bitbang bitbang;
52 struct completion done;
53
54 void __iomem *regs;
55 int irq;
56 int len;
57 int count;
58
59 struct fiq_handler fiq_handler;
60 enum spi_fiq_mode fiq_mode;
61 unsigned char fiq_inuse;
62 unsigned char fiq_claimed;
63
64
65 const unsigned char *tx;
66 unsigned char *rx;
67
68 struct clk *clk;
69 struct spi_master *master;
70 struct spi_device *curdev;
71 struct device *dev;
72 struct s3c2410_spi_info *pdata;
73};
74
75#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
76#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
77
78static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
79{
80 return spi_master_get_devdata(sdev->master);
81}
82
83static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
84{
85 struct s3c24xx_spi_devstate *cs = spi->controller_state;
86 struct s3c24xx_spi *hw = to_hw(spi);
87
88
89
90 switch (value) {
91 case BITBANG_CS_INACTIVE:
92 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
93 break;
94
95 case BITBANG_CS_ACTIVE:
96 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
97 hw->regs + S3C2410_SPCON);
98 break;
99 }
100}
101
102static int s3c24xx_spi_update_state(struct spi_device *spi,
103 struct spi_transfer *t)
104{
105 struct s3c24xx_spi *hw = to_hw(spi);
106 struct s3c24xx_spi_devstate *cs = spi->controller_state;
107 unsigned int hz;
108 unsigned int div;
109 unsigned long clk;
110
111 hz = t ? t->speed_hz : spi->max_speed_hz;
112
113 if (!hz)
114 hz = spi->max_speed_hz;
115
116 if (spi->mode != cs->mode) {
117 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
118
119 if (spi->mode & SPI_CPHA)
120 spcon |= S3C2410_SPCON_CPHA_FMTB;
121
122 if (spi->mode & SPI_CPOL)
123 spcon |= S3C2410_SPCON_CPOL_HIGH;
124
125 cs->mode = spi->mode;
126 cs->spcon = spcon;
127 }
128
129 if (cs->hz != hz) {
130 clk = clk_get_rate(hw->clk);
131 div = DIV_ROUND_UP(clk, hz * 2) - 1;
132
133 if (div > 255)
134 div = 255;
135
136 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
137 div, hz, clk / (2 * (div + 1)));
138
139 cs->hz = hz;
140 cs->sppre = div;
141 }
142
143 return 0;
144}
145
146static int s3c24xx_spi_setupxfer(struct spi_device *spi,
147 struct spi_transfer *t)
148{
149 struct s3c24xx_spi_devstate *cs = spi->controller_state;
150 struct s3c24xx_spi *hw = to_hw(spi);
151 int ret;
152
153 ret = s3c24xx_spi_update_state(spi, t);
154 if (!ret)
155 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
156
157 return ret;
158}
159
160static int s3c24xx_spi_setup(struct spi_device *spi)
161{
162 struct s3c24xx_spi_devstate *cs = spi->controller_state;
163 struct s3c24xx_spi *hw = to_hw(spi);
164 int ret;
165
166
167 if (!cs) {
168 cs = devm_kzalloc(&spi->dev,
169 sizeof(struct s3c24xx_spi_devstate),
170 GFP_KERNEL);
171 if (!cs)
172 return -ENOMEM;
173
174 cs->spcon = SPCON_DEFAULT;
175 cs->hz = -1;
176 spi->controller_state = cs;
177 }
178
179
180 ret = s3c24xx_spi_update_state(spi, NULL);
181 if (ret)
182 return ret;
183
184 mutex_lock(&hw->bitbang.lock);
185 if (!hw->bitbang.busy) {
186 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
187
188 }
189 mutex_unlock(&hw->bitbang.lock);
190
191 return 0;
192}
193
194static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
195{
196 return hw->tx ? hw->tx[count] : 0;
197}
198
199#ifdef CONFIG_SPI_S3C24XX_FIQ
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211
212
213
214struct spi_fiq_code {
215 u32 length;
216 u32 ack_offset;
217 u8 data[];
218};
219
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229
230
231static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
232{
233 struct pt_regs regs;
234 enum spi_fiq_mode mode;
235 struct spi_fiq_code *code;
236 u32 *ack_ptr = NULL;
237 int ret;
238
239 if (!hw->fiq_claimed) {
240
241
242
243 ret = claim_fiq(&hw->fiq_handler);
244 if (ret)
245 return;
246 }
247
248 if (hw->tx && !hw->rx)
249 mode = FIQ_MODE_TX;
250 else if (hw->rx && !hw->tx)
251 mode = FIQ_MODE_RX;
252 else
253 mode = FIQ_MODE_TXRX;
254
255 regs.uregs[fiq_rspi] = (long)hw->regs;
256 regs.uregs[fiq_rrx] = (long)hw->rx;
257 regs.uregs[fiq_rtx] = (long)hw->tx + 1;
258 regs.uregs[fiq_rcount] = hw->len - 1;
259
260 set_fiq_regs(®s);
261
262 if (hw->fiq_mode != mode) {
263 hw->fiq_mode = mode;
264
265 switch (mode) {
266 case FIQ_MODE_TX:
267 code = &s3c24xx_spi_fiq_tx;
268 break;
269 case FIQ_MODE_RX:
270 code = &s3c24xx_spi_fiq_rx;
271 break;
272 case FIQ_MODE_TXRX:
273 code = &s3c24xx_spi_fiq_txrx;
274 break;
275 default:
276 code = NULL;
277 }
278
279 BUG_ON(!code);
280
281 ack_ptr = (u32 *)&code->data[code->ack_offset];
282 set_fiq_handler(&code->data, code->length);
283 }
284
285 s3c24xx_set_fiq(hw->irq, ack_ptr, true);
286
287 hw->fiq_mode = mode;
288 hw->fiq_inuse = 1;
289}
290
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297
298
299
300static int s3c24xx_spi_fiqop(void *pw, int release)
301{
302 struct s3c24xx_spi *hw = pw;
303 int ret = 0;
304
305 if (release) {
306 if (hw->fiq_inuse)
307 ret = -EBUSY;
308
309
310
311
312 hw->fiq_mode = FIQ_MODE_NONE;
313 hw->fiq_claimed = 0;
314 } else {
315 hw->fiq_claimed = 1;
316 }
317
318 return ret;
319}
320
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326
327static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
328{
329 hw->fiq_handler.dev_id = hw;
330 hw->fiq_handler.name = dev_name(hw->dev);
331 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
332}
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341static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
342{
343 return hw->pdata->use_fiq;
344}
345
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350
351
352
353static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
354{
355 return spi->fiq_inuse;
356}
357#else
358
359static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
360static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
361static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
362static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
363
364#endif
365
366static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
367{
368 struct s3c24xx_spi *hw = to_hw(spi);
369
370 hw->tx = t->tx_buf;
371 hw->rx = t->rx_buf;
372 hw->len = t->len;
373 hw->count = 0;
374
375 init_completion(&hw->done);
376
377 hw->fiq_inuse = 0;
378 if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
379 s3c24xx_spi_tryfiq(hw);
380
381
382 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
383
384 wait_for_completion(&hw->done);
385 return hw->count;
386}
387
388static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
389{
390 struct s3c24xx_spi *hw = dev;
391 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
392 unsigned int count = hw->count;
393
394 if (spsta & S3C2410_SPSTA_DCOL) {
395 dev_dbg(hw->dev, "data-collision\n");
396 complete(&hw->done);
397 goto irq_done;
398 }
399
400 if (!(spsta & S3C2410_SPSTA_READY)) {
401 dev_dbg(hw->dev, "spi not ready for tx?\n");
402 complete(&hw->done);
403 goto irq_done;
404 }
405
406 if (!s3c24xx_spi_usingfiq(hw)) {
407 hw->count++;
408
409 if (hw->rx)
410 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
411
412 count++;
413
414 if (count < hw->len)
415 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
416 else
417 complete(&hw->done);
418 } else {
419 hw->count = hw->len;
420 hw->fiq_inuse = 0;
421
422 if (hw->rx)
423 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
424
425 complete(&hw->done);
426 }
427
428 irq_done:
429 return IRQ_HANDLED;
430}
431
432static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
433{
434
435
436 clk_enable(hw->clk);
437
438
439
440 writeb(0xff, hw->regs + S3C2410_SPPRE);
441 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
442 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
443}
444
445static int s3c24xx_spi_probe(struct platform_device *pdev)
446{
447 struct s3c2410_spi_info *pdata;
448 struct s3c24xx_spi *hw;
449 struct spi_master *master;
450 int err = 0;
451
452 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
453 if (master == NULL) {
454 dev_err(&pdev->dev, "No memory for spi_master\n");
455 return -ENOMEM;
456 }
457
458 hw = spi_master_get_devdata(master);
459
460 hw->master = master;
461 hw->pdata = pdata = dev_get_platdata(&pdev->dev);
462 hw->dev = &pdev->dev;
463
464 if (pdata == NULL) {
465 dev_err(&pdev->dev, "No platform data supplied\n");
466 err = -ENOENT;
467 goto err_no_pdata;
468 }
469
470 platform_set_drvdata(pdev, hw);
471 init_completion(&hw->done);
472
473
474
475 s3c24xx_spi_initfiq(hw);
476
477
478
479
480 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
481
482 master->num_chipselect = hw->pdata->num_cs;
483 master->bus_num = pdata->bus_num;
484 master->bits_per_word_mask = SPI_BPW_MASK(8);
485
486 master->flags = SPI_MASTER_GPIO_SS;
487 master->use_gpio_descriptors = true;
488
489
490
491 hw->bitbang.master = hw->master;
492 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
493 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
494 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
495
496 hw->master->setup = s3c24xx_spi_setup;
497
498 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
499
500
501 hw->regs = devm_platform_ioremap_resource(pdev, 0);
502 if (IS_ERR(hw->regs)) {
503 err = PTR_ERR(hw->regs);
504 goto err_no_pdata;
505 }
506
507 hw->irq = platform_get_irq(pdev, 0);
508 if (hw->irq < 0) {
509 err = -ENOENT;
510 goto err_no_pdata;
511 }
512
513 err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
514 pdev->name, hw);
515 if (err) {
516 dev_err(&pdev->dev, "Cannot claim IRQ\n");
517 goto err_no_pdata;
518 }
519
520 hw->clk = devm_clk_get(&pdev->dev, "spi");
521 if (IS_ERR(hw->clk)) {
522 dev_err(&pdev->dev, "No clock for device\n");
523 err = PTR_ERR(hw->clk);
524 goto err_no_pdata;
525 }
526
527 s3c24xx_spi_initialsetup(hw);
528
529
530
531 err = spi_bitbang_start(&hw->bitbang);
532 if (err) {
533 dev_err(&pdev->dev, "Failed to register SPI master\n");
534 goto err_register;
535 }
536
537 return 0;
538
539 err_register:
540 clk_disable(hw->clk);
541
542 err_no_pdata:
543 spi_master_put(hw->master);
544 return err;
545}
546
547static int s3c24xx_spi_remove(struct platform_device *dev)
548{
549 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
550
551 spi_bitbang_stop(&hw->bitbang);
552 clk_disable(hw->clk);
553 spi_master_put(hw->master);
554 return 0;
555}
556
557
558#ifdef CONFIG_PM
559
560static int s3c24xx_spi_suspend(struct device *dev)
561{
562 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
563 int ret;
564
565 ret = spi_master_suspend(hw->master);
566 if (ret)
567 return ret;
568
569 clk_disable(hw->clk);
570 return 0;
571}
572
573static int s3c24xx_spi_resume(struct device *dev)
574{
575 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
576
577 s3c24xx_spi_initialsetup(hw);
578 return spi_master_resume(hw->master);
579}
580
581static const struct dev_pm_ops s3c24xx_spi_pmops = {
582 .suspend = s3c24xx_spi_suspend,
583 .resume = s3c24xx_spi_resume,
584};
585
586#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
587#else
588#define S3C24XX_SPI_PMOPS NULL
589#endif
590
591MODULE_ALIAS("platform:s3c2410-spi");
592static struct platform_driver s3c24xx_spi_driver = {
593 .probe = s3c24xx_spi_probe,
594 .remove = s3c24xx_spi_remove,
595 .driver = {
596 .name = "s3c2410-spi",
597 .pm = S3C24XX_SPI_PMOPS,
598 },
599};
600module_platform_driver(s3c24xx_spi_driver);
601
602MODULE_DESCRIPTION("S3C24XX SPI Driver");
603MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
604MODULE_LICENSE("GPL");
605