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6#ifndef __LINUX_CLK_PROVIDER_H
7#define __LINUX_CLK_PROVIDER_H
8
9#include <linux/of.h>
10#include <linux/of_clk.h>
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19#define CLK_SET_RATE_GATE BIT(0)
20#define CLK_SET_PARENT_GATE BIT(1)
21#define CLK_SET_RATE_PARENT BIT(2)
22#define CLK_IGNORE_UNUSED BIT(3)
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24
25#define CLK_GET_RATE_NOCACHE BIT(6)
26#define CLK_SET_RATE_NO_REPARENT BIT(7)
27#define CLK_GET_ACCURACY_NOCACHE BIT(8)
28#define CLK_RECALC_NEW_RATES BIT(9)
29#define CLK_SET_RATE_UNGATE BIT(10)
30#define CLK_IS_CRITICAL BIT(11)
31
32#define CLK_OPS_PARENT_ENABLE BIT(12)
33
34#define CLK_DUTY_CYCLE_PARENT BIT(13)
35
36struct clk;
37struct clk_hw;
38struct clk_core;
39struct dentry;
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55struct clk_rate_request {
56 unsigned long rate;
57 unsigned long min_rate;
58 unsigned long max_rate;
59 unsigned long best_parent_rate;
60 struct clk_hw *best_parent_hw;
61};
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69struct clk_duty {
70 unsigned int num;
71 unsigned int den;
72};
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220struct clk_ops {
221 int (*prepare)(struct clk_hw *hw);
222 void (*unprepare)(struct clk_hw *hw);
223 int (*is_prepared)(struct clk_hw *hw);
224 void (*unprepare_unused)(struct clk_hw *hw);
225 int (*enable)(struct clk_hw *hw);
226 void (*disable)(struct clk_hw *hw);
227 int (*is_enabled)(struct clk_hw *hw);
228 void (*disable_unused)(struct clk_hw *hw);
229 int (*save_context)(struct clk_hw *hw);
230 void (*restore_context)(struct clk_hw *hw);
231 unsigned long (*recalc_rate)(struct clk_hw *hw,
232 unsigned long parent_rate);
233 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
234 unsigned long *parent_rate);
235 int (*determine_rate)(struct clk_hw *hw,
236 struct clk_rate_request *req);
237 int (*set_parent)(struct clk_hw *hw, u8 index);
238 u8 (*get_parent)(struct clk_hw *hw);
239 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
240 unsigned long parent_rate);
241 int (*set_rate_and_parent)(struct clk_hw *hw,
242 unsigned long rate,
243 unsigned long parent_rate, u8 index);
244 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
245 unsigned long parent_accuracy);
246 int (*get_phase)(struct clk_hw *hw);
247 int (*set_phase)(struct clk_hw *hw, int degrees);
248 int (*get_duty_cycle)(struct clk_hw *hw,
249 struct clk_duty *duty);
250 int (*set_duty_cycle)(struct clk_hw *hw,
251 struct clk_duty *duty);
252 int (*init)(struct clk_hw *hw);
253 void (*terminate)(struct clk_hw *hw);
254 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
255};
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264struct clk_parent_data {
265 const struct clk_hw *hw;
266 const char *fw_name;
267 const char *name;
268 int index;
269};
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285struct clk_init_data {
286 const char *name;
287 const struct clk_ops *ops;
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289 const char * const *parent_names;
290 const struct clk_parent_data *parent_data;
291 const struct clk_hw **parent_hws;
292 u8 num_parents;
293 unsigned long flags;
294};
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312struct clk_hw {
313 struct clk_core *core;
314 struct clk *clk;
315 const struct clk_init_data *init;
316};
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338struct clk_fixed_rate {
339 struct clk_hw hw;
340 unsigned long fixed_rate;
341 unsigned long fixed_accuracy;
342 unsigned long flags;
343};
344
345#define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
346
347extern const struct clk_ops clk_fixed_rate_ops;
348struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
349 struct device_node *np, const char *name,
350 const char *parent_name, const struct clk_hw *parent_hw,
351 const struct clk_parent_data *parent_data, unsigned long flags,
352 unsigned long fixed_rate, unsigned long fixed_accuracy,
353 unsigned long clk_fixed_flags);
354struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
355 const char *parent_name, unsigned long flags,
356 unsigned long fixed_rate);
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366#define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
367 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
368 NULL, (flags), (fixed_rate), 0, 0)
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378#define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
379 fixed_rate) \
380 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
381 NULL, (flags), (fixed_rate), 0, 0)
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391#define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \
392 fixed_rate) \
393 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
394 (parent_data), (flags), (fixed_rate), 0, \
395 0)
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406#define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
407 flags, fixed_rate, \
408 fixed_accuracy) \
409 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
410 NULL, NULL, (flags), (fixed_rate), \
411 (fixed_accuracy), 0)
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422#define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
423 parent_hw, flags, fixed_rate, fixed_accuracy) \
424 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \
425 NULL, NULL, (flags), (fixed_rate), \
426 (fixed_accuracy), 0)
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437#define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
438 parent_data, flags, fixed_rate, fixed_accuracy) \
439 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
440 (parent_data), NULL, (flags), \
441 (fixed_rate), (fixed_accuracy), 0)
442
443void clk_unregister_fixed_rate(struct clk *clk);
444void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
445
446void of_fixed_clk_setup(struct device_node *np);
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471struct clk_gate {
472 struct clk_hw hw;
473 void __iomem *reg;
474 u8 bit_idx;
475 u8 flags;
476 spinlock_t *lock;
477};
478
479#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
480
481#define CLK_GATE_SET_TO_DISABLE BIT(0)
482#define CLK_GATE_HIWORD_MASK BIT(1)
483#define CLK_GATE_BIG_ENDIAN BIT(2)
484
485extern const struct clk_ops clk_gate_ops;
486struct clk_hw *__clk_hw_register_gate(struct device *dev,
487 struct device_node *np, const char *name,
488 const char *parent_name, const struct clk_hw *parent_hw,
489 const struct clk_parent_data *parent_data,
490 unsigned long flags,
491 void __iomem *reg, u8 bit_idx,
492 u8 clk_gate_flags, spinlock_t *lock);
493struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
494 struct device_node *np, const char *name,
495 const char *parent_name, const struct clk_hw *parent_hw,
496 const struct clk_parent_data *parent_data,
497 unsigned long flags,
498 void __iomem *reg, u8 bit_idx,
499 u8 clk_gate_flags, spinlock_t *lock);
500struct clk *clk_register_gate(struct device *dev, const char *name,
501 const char *parent_name, unsigned long flags,
502 void __iomem *reg, u8 bit_idx,
503 u8 clk_gate_flags, spinlock_t *lock);
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515#define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
516 clk_gate_flags, lock) \
517 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
518 NULL, (flags), (reg), (bit_idx), \
519 (clk_gate_flags), (lock))
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532#define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
533 bit_idx, clk_gate_flags, lock) \
534 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
535 NULL, (flags), (reg), (bit_idx), \
536 (clk_gate_flags), (lock))
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549#define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
550 bit_idx, clk_gate_flags, lock) \
551 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
552 (flags), (reg), (bit_idx), \
553 (clk_gate_flags), (lock))
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565#define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\
566 clk_gate_flags, lock) \
567 __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
568 NULL, (flags), (reg), (bit_idx), \
569 (clk_gate_flags), (lock))
570void clk_unregister_gate(struct clk *clk);
571void clk_hw_unregister_gate(struct clk_hw *hw);
572int clk_gate_is_enabled(struct clk_hw *hw);
573
574struct clk_div_table {
575 unsigned int val;
576 unsigned int div;
577};
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619struct clk_divider {
620 struct clk_hw hw;
621 void __iomem *reg;
622 u8 shift;
623 u8 width;
624 u8 flags;
625 const struct clk_div_table *table;
626 spinlock_t *lock;
627};
628
629#define clk_div_mask(width) ((1 << (width)) - 1)
630#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
631
632#define CLK_DIVIDER_ONE_BASED BIT(0)
633#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
634#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
635#define CLK_DIVIDER_HIWORD_MASK BIT(3)
636#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
637#define CLK_DIVIDER_READ_ONLY BIT(5)
638#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
639#define CLK_DIVIDER_BIG_ENDIAN BIT(7)
640
641extern const struct clk_ops clk_divider_ops;
642extern const struct clk_ops clk_divider_ro_ops;
643
644unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
645 unsigned int val, const struct clk_div_table *table,
646 unsigned long flags, unsigned long width);
647long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
648 unsigned long rate, unsigned long *prate,
649 const struct clk_div_table *table,
650 u8 width, unsigned long flags);
651long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
652 unsigned long rate, unsigned long *prate,
653 const struct clk_div_table *table, u8 width,
654 unsigned long flags, unsigned int val);
655int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
656 const struct clk_div_table *table, u8 width,
657 unsigned long flags);
658int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
659 const struct clk_div_table *table, u8 width,
660 unsigned long flags, unsigned int val);
661int divider_get_val(unsigned long rate, unsigned long parent_rate,
662 const struct clk_div_table *table, u8 width,
663 unsigned long flags);
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665struct clk_hw *__clk_hw_register_divider(struct device *dev,
666 struct device_node *np, const char *name,
667 const char *parent_name, const struct clk_hw *parent_hw,
668 const struct clk_parent_data *parent_data, unsigned long flags,
669 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
670 const struct clk_div_table *table, spinlock_t *lock);
671struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
672 struct device_node *np, const char *name,
673 const char *parent_name, const struct clk_hw *parent_hw,
674 const struct clk_parent_data *parent_data, unsigned long flags,
675 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
676 const struct clk_div_table *table, spinlock_t *lock);
677struct clk *clk_register_divider_table(struct device *dev, const char *name,
678 const char *parent_name, unsigned long flags,
679 void __iomem *reg, u8 shift, u8 width,
680 u8 clk_divider_flags, const struct clk_div_table *table,
681 spinlock_t *lock);
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694#define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
695 clk_divider_flags, lock) \
696 clk_register_divider_table((dev), (name), (parent_name), (flags), \
697 (reg), (shift), (width), \
698 (clk_divider_flags), NULL, (lock))
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711#define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
712 width, clk_divider_flags, lock) \
713 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
714 NULL, (flags), (reg), (shift), (width), \
715 (clk_divider_flags), NULL, (lock))
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729#define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
730 shift, width, clk_divider_flags, \
731 lock) \
732 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
733 NULL, (flags), (reg), (shift), (width), \
734 (clk_divider_flags), NULL, (lock))
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748#define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
749 reg, shift, width, \
750 clk_divider_flags, lock) \
751 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
752 (parent_data), (flags), (reg), (shift), \
753 (width), (clk_divider_flags), NULL, (lock))
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768#define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
769 shift, width, clk_divider_flags, table, \
770 lock) \
771 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
772 NULL, (flags), (reg), (shift), (width), \
773 (clk_divider_flags), (table), (lock))
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788#define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
789 reg, shift, width, \
790 clk_divider_flags, table, \
791 lock) \
792 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
793 NULL, (flags), (reg), (shift), (width), \
794 (clk_divider_flags), (table), (lock))
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809#define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
810 flags, reg, shift, width, \
811 clk_divider_flags, table, \
812 lock) \
813 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
814 (parent_data), (flags), (reg), (shift), \
815 (width), (clk_divider_flags), (table), \
816 (lock))
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829#define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
830 width, clk_divider_flags, lock) \
831 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
832 NULL, (flags), (reg), (shift), (width), \
833 (clk_divider_flags), NULL, (lock))
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848#define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \
849 reg, shift, width, \
850 clk_divider_flags, table, lock) \
851 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \
852 NULL, NULL, (flags), (reg), (shift), \
853 (width), (clk_divider_flags), (table), \
854 (lock))
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856void clk_unregister_divider(struct clk *clk);
857void clk_hw_unregister_divider(struct clk_hw *hw);
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888struct clk_mux {
889 struct clk_hw hw;
890 void __iomem *reg;
891 const u32 *table;
892 u32 mask;
893 u8 shift;
894 u8 flags;
895 spinlock_t *lock;
896};
897
898#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
899
900#define CLK_MUX_INDEX_ONE BIT(0)
901#define CLK_MUX_INDEX_BIT BIT(1)
902#define CLK_MUX_HIWORD_MASK BIT(2)
903#define CLK_MUX_READ_ONLY BIT(3)
904#define CLK_MUX_ROUND_CLOSEST BIT(4)
905#define CLK_MUX_BIG_ENDIAN BIT(5)
906
907extern const struct clk_ops clk_mux_ops;
908extern const struct clk_ops clk_mux_ro_ops;
909
910struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
911 const char *name, u8 num_parents,
912 const char * const *parent_names,
913 const struct clk_hw **parent_hws,
914 const struct clk_parent_data *parent_data,
915 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
916 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
917struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
918 const char *name, u8 num_parents,
919 const char * const *parent_names,
920 const struct clk_hw **parent_hws,
921 const struct clk_parent_data *parent_data,
922 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
923 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
924struct clk *clk_register_mux_table(struct device *dev, const char *name,
925 const char * const *parent_names, u8 num_parents,
926 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
927 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
928
929#define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
930 shift, width, clk_mux_flags, lock) \
931 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
932 (flags), (reg), (shift), BIT((width)) - 1, \
933 (clk_mux_flags), NULL, (lock))
934#define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
935 flags, reg, shift, mask, clk_mux_flags, \
936 table, lock) \
937 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
938 (parent_names), NULL, NULL, (flags), (reg), \
939 (shift), (mask), (clk_mux_flags), (table), \
940 (lock))
941#define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
942 shift, width, clk_mux_flags, lock) \
943 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
944 (parent_names), NULL, NULL, (flags), (reg), \
945 (shift), BIT((width)) - 1, (clk_mux_flags), \
946 NULL, (lock))
947#define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
948 reg, shift, width, clk_mux_flags, lock) \
949 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
950 (parent_hws), NULL, (flags), (reg), (shift), \
951 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
952#define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
953 flags, reg, shift, width, \
954 clk_mux_flags, lock) \
955 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
956 (parent_data), (flags), (reg), (shift), \
957 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
958#define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
959 shift, width, clk_mux_flags, lock) \
960 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \
961 (parent_names), NULL, NULL, (flags), (reg), \
962 (shift), BIT((width)) - 1, (clk_mux_flags), \
963 NULL, (lock))
964
965int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,
966 unsigned int val);
967unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index);
968
969void clk_unregister_mux(struct clk *clk);
970void clk_hw_unregister_mux(struct clk_hw *hw);
971
972void of_fixed_factor_clk_setup(struct device_node *node);
973
974
975
976
977
978
979
980
981
982
983
984
985
986struct clk_fixed_factor {
987 struct clk_hw hw;
988 unsigned int mult;
989 unsigned int div;
990};
991
992#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
993
994extern const struct clk_ops clk_fixed_factor_ops;
995struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
996 const char *parent_name, unsigned long flags,
997 unsigned int mult, unsigned int div);
998void clk_unregister_fixed_factor(struct clk *clk);
999struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
1000 const char *name, const char *parent_name, unsigned long flags,
1001 unsigned int mult, unsigned int div);
1002void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
1003struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
1004 const char *name, const char *parent_name, unsigned long flags,
1005 unsigned int mult, unsigned int div);
1006struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
1007 const char *name, unsigned int index, unsigned long flags,
1008 unsigned int mult, unsigned int div);
1009
1010
1011
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1016
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1020
1021
1022
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1024
1025
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1032
1033
1034
1035
1036
1037struct clk_fractional_divider {
1038 struct clk_hw hw;
1039 void __iomem *reg;
1040 u8 mshift;
1041 u8 mwidth;
1042 u32 mmask;
1043 u8 nshift;
1044 u8 nwidth;
1045 u32 nmask;
1046 u8 flags;
1047 void (*approximation)(struct clk_hw *hw,
1048 unsigned long rate, unsigned long *parent_rate,
1049 unsigned long *m, unsigned long *n);
1050 spinlock_t *lock;
1051};
1052
1053#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
1054
1055#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
1056#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
1057#define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2)
1058
1059struct clk *clk_register_fractional_divider(struct device *dev,
1060 const char *name, const char *parent_name, unsigned long flags,
1061 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1062 u8 clk_divider_flags, spinlock_t *lock);
1063struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
1064 const char *name, const char *parent_name, unsigned long flags,
1065 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1066 u8 clk_divider_flags, spinlock_t *lock);
1067void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
1068
1069
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1075
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1080
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1092
1093struct clk_multiplier {
1094 struct clk_hw hw;
1095 void __iomem *reg;
1096 u8 shift;
1097 u8 width;
1098 u8 flags;
1099 spinlock_t *lock;
1100};
1101
1102#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1103
1104#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1105#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1106#define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1107
1108extern const struct clk_ops clk_multiplier_ops;
1109
1110
1111
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1120
1121struct clk_composite {
1122 struct clk_hw hw;
1123 struct clk_ops ops;
1124
1125 struct clk_hw *mux_hw;
1126 struct clk_hw *rate_hw;
1127 struct clk_hw *gate_hw;
1128
1129 const struct clk_ops *mux_ops;
1130 const struct clk_ops *rate_ops;
1131 const struct clk_ops *gate_ops;
1132};
1133
1134#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1135
1136struct clk *clk_register_composite(struct device *dev, const char *name,
1137 const char * const *parent_names, int num_parents,
1138 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1139 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1140 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1141 unsigned long flags);
1142struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1143 const struct clk_parent_data *parent_data, int num_parents,
1144 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1145 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1146 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1147 unsigned long flags);
1148void clk_unregister_composite(struct clk *clk);
1149struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1150 const char * const *parent_names, int num_parents,
1151 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1152 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1153 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1154 unsigned long flags);
1155struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1156 const char *name,
1157 const struct clk_parent_data *parent_data, int num_parents,
1158 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1159 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1160 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1161 unsigned long flags);
1162struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
1163 const char *name, const struct clk_parent_data *parent_data,
1164 int num_parents,
1165 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1166 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1167 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1168 unsigned long flags);
1169void clk_hw_unregister_composite(struct clk_hw *hw);
1170
1171struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1172struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1173
1174int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1175int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1176int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1177
1178void clk_unregister(struct clk *clk);
1179void devm_clk_unregister(struct device *dev, struct clk *clk);
1180
1181void clk_hw_unregister(struct clk_hw *hw);
1182void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
1183
1184
1185const char *__clk_get_name(const struct clk *clk);
1186const char *clk_hw_get_name(const struct clk_hw *hw);
1187#ifdef CONFIG_COMMON_CLK
1188struct clk_hw *__clk_get_hw(struct clk *clk);
1189#else
1190static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1191{
1192 return (struct clk_hw *)clk;
1193}
1194#endif
1195
1196struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1197struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1198 const char *con_id);
1199
1200unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1201struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1202struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1203 unsigned int index);
1204int clk_hw_get_parent_index(struct clk_hw *hw);
1205int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1206unsigned int __clk_get_enable_count(struct clk *clk);
1207unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1208unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1209#define clk_hw_can_set_rate_parent(hw) \
1210 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1211
1212bool clk_hw_is_prepared(const struct clk_hw *hw);
1213bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1214bool clk_hw_is_enabled(const struct clk_hw *hw);
1215bool __clk_is_enabled(struct clk *clk);
1216struct clk *__clk_lookup(const char *name);
1217int __clk_mux_determine_rate(struct clk_hw *hw,
1218 struct clk_rate_request *req);
1219int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1220int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1221 struct clk_rate_request *req);
1222int clk_mux_determine_rate_flags(struct clk_hw *hw,
1223 struct clk_rate_request *req,
1224 unsigned long flags);
1225void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1226void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1227 unsigned long max_rate);
1228
1229static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1230{
1231 dst->clk = src->clk;
1232 dst->core = src->core;
1233}
1234
1235static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
1236 unsigned long *prate,
1237 const struct clk_div_table *table,
1238 u8 width, unsigned long flags)
1239{
1240 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
1241 rate, prate, table, width, flags);
1242}
1243
1244static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1245 unsigned long *prate,
1246 const struct clk_div_table *table,
1247 u8 width, unsigned long flags,
1248 unsigned int val)
1249{
1250 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1251 rate, prate, table, width, flags,
1252 val);
1253}
1254
1255
1256
1257
1258unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1259
1260struct clk_onecell_data {
1261 struct clk **clks;
1262 unsigned int clk_num;
1263};
1264
1265struct clk_hw_onecell_data {
1266 unsigned int num;
1267 struct clk_hw *hws[];
1268};
1269
1270#define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
1271
1272
1273
1274
1275
1276#define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1277 static void __init name##_of_clk_init_driver(struct device_node *np) \
1278 { \
1279 of_node_clear_flag(np, OF_POPULATED); \
1280 fn(np); \
1281 } \
1282 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1283
1284#define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1285 (&(struct clk_init_data) { \
1286 .flags = _flags, \
1287 .name = _name, \
1288 .parent_names = (const char *[]) { _parent }, \
1289 .num_parents = 1, \
1290 .ops = _ops, \
1291 })
1292
1293#define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1294 (&(struct clk_init_data) { \
1295 .flags = _flags, \
1296 .name = _name, \
1297 .parent_hws = (const struct clk_hw*[]) { _parent }, \
1298 .num_parents = 1, \
1299 .ops = _ops, \
1300 })
1301
1302
1303
1304
1305
1306
1307#define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1308 (&(struct clk_init_data) { \
1309 .flags = _flags, \
1310 .name = _name, \
1311 .parent_hws = _parent, \
1312 .num_parents = 1, \
1313 .ops = _ops, \
1314 })
1315
1316#define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1317 (&(struct clk_init_data) { \
1318 .flags = _flags, \
1319 .name = _name, \
1320 .parent_data = (const struct clk_parent_data[]) { \
1321 { .fw_name = _parent }, \
1322 }, \
1323 .num_parents = 1, \
1324 .ops = _ops, \
1325 })
1326
1327#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1328 (&(struct clk_init_data) { \
1329 .flags = _flags, \
1330 .name = _name, \
1331 .parent_names = _parents, \
1332 .num_parents = ARRAY_SIZE(_parents), \
1333 .ops = _ops, \
1334 })
1335
1336#define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1337 (&(struct clk_init_data) { \
1338 .flags = _flags, \
1339 .name = _name, \
1340 .parent_hws = _parents, \
1341 .num_parents = ARRAY_SIZE(_parents), \
1342 .ops = _ops, \
1343 })
1344
1345#define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1346 (&(struct clk_init_data) { \
1347 .flags = _flags, \
1348 .name = _name, \
1349 .parent_data = _parents, \
1350 .num_parents = ARRAY_SIZE(_parents), \
1351 .ops = _ops, \
1352 })
1353
1354#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1355 (&(struct clk_init_data) { \
1356 .flags = _flags, \
1357 .name = _name, \
1358 .parent_names = NULL, \
1359 .num_parents = 0, \
1360 .ops = _ops, \
1361 })
1362
1363#define CLK_FIXED_FACTOR(_struct, _name, _parent, \
1364 _div, _mult, _flags) \
1365 struct clk_fixed_factor _struct = { \
1366 .div = _div, \
1367 .mult = _mult, \
1368 .hw.init = CLK_HW_INIT(_name, \
1369 _parent, \
1370 &clk_fixed_factor_ops, \
1371 _flags), \
1372 }
1373
1374#define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1375 _div, _mult, _flags) \
1376 struct clk_fixed_factor _struct = { \
1377 .div = _div, \
1378 .mult = _mult, \
1379 .hw.init = CLK_HW_INIT_HW(_name, \
1380 _parent, \
1381 &clk_fixed_factor_ops, \
1382 _flags), \
1383 }
1384
1385
1386
1387
1388
1389#define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1390 _div, _mult, _flags) \
1391 struct clk_fixed_factor _struct = { \
1392 .div = _div, \
1393 .mult = _mult, \
1394 .hw.init = CLK_HW_INIT_HWS(_name, \
1395 _parent, \
1396 &clk_fixed_factor_ops, \
1397 _flags), \
1398 }
1399
1400#define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1401 _div, _mult, _flags) \
1402 struct clk_fixed_factor _struct = { \
1403 .div = _div, \
1404 .mult = _mult, \
1405 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1406 _parent, \
1407 &clk_fixed_factor_ops, \
1408 _flags), \
1409 }
1410
1411#ifdef CONFIG_OF
1412int of_clk_add_provider(struct device_node *np,
1413 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1414 void *data),
1415 void *data);
1416int of_clk_add_hw_provider(struct device_node *np,
1417 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1418 void *data),
1419 void *data);
1420int devm_of_clk_add_hw_provider(struct device *dev,
1421 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1422 void *data),
1423 void *data);
1424void of_clk_del_provider(struct device_node *np);
1425void devm_of_clk_del_provider(struct device *dev);
1426struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1427 void *data);
1428struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1429 void *data);
1430struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1431struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1432 void *data);
1433int of_clk_parent_fill(struct device_node *np, const char **parents,
1434 unsigned int size);
1435int of_clk_detect_critical(struct device_node *np, int index,
1436 unsigned long *flags);
1437
1438#else
1439
1440static inline int of_clk_add_provider(struct device_node *np,
1441 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1442 void *data),
1443 void *data)
1444{
1445 return 0;
1446}
1447static inline int of_clk_add_hw_provider(struct device_node *np,
1448 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1449 void *data),
1450 void *data)
1451{
1452 return 0;
1453}
1454static inline int devm_of_clk_add_hw_provider(struct device *dev,
1455 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1456 void *data),
1457 void *data)
1458{
1459 return 0;
1460}
1461static inline void of_clk_del_provider(struct device_node *np) {}
1462static inline void devm_of_clk_del_provider(struct device *dev) {}
1463static inline struct clk *of_clk_src_simple_get(
1464 struct of_phandle_args *clkspec, void *data)
1465{
1466 return ERR_PTR(-ENOENT);
1467}
1468static inline struct clk_hw *
1469of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1470{
1471 return ERR_PTR(-ENOENT);
1472}
1473static inline struct clk *of_clk_src_onecell_get(
1474 struct of_phandle_args *clkspec, void *data)
1475{
1476 return ERR_PTR(-ENOENT);
1477}
1478static inline struct clk_hw *
1479of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1480{
1481 return ERR_PTR(-ENOENT);
1482}
1483static inline int of_clk_parent_fill(struct device_node *np,
1484 const char **parents, unsigned int size)
1485{
1486 return 0;
1487}
1488static inline int of_clk_detect_critical(struct device_node *np, int index,
1489 unsigned long *flags)
1490{
1491 return 0;
1492}
1493#endif
1494
1495void clk_gate_restore_context(struct clk_hw *hw);
1496
1497#endif
1498