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33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/irq.h>
40#include <linux/spinlock_types.h>
41#include <linux/semaphore.h>
42#include <linux/slab.h>
43#include <linux/vmalloc.h>
44#include <linux/xarray.h>
45#include <linux/workqueue.h>
46#include <linux/mempool.h>
47#include <linux/interrupt.h>
48#include <linux/idr.h>
49#include <linux/notifier.h>
50#include <linux/refcount.h>
51#include <linux/auxiliary_bus.h>
52
53#include <linux/mlx5/device.h>
54#include <linux/mlx5/doorbell.h>
55#include <linux/mlx5/eq.h>
56#include <linux/timecounter.h>
57#include <linux/ptp_clock_kernel.h>
58#include <net/devlink.h>
59
60#define MLX5_ADEV_NAME "mlx5_core"
61
62#define MLX5_IRQ_EQ_CTRL (U8_MAX)
63
64enum {
65 MLX5_BOARD_ID_LEN = 64,
66};
67
68enum {
69 MLX5_CMD_WQ_MAX_NAME = 32,
70};
71
72enum {
73 CMD_OWNER_SW = 0x0,
74 CMD_OWNER_HW = 0x1,
75 CMD_STATUS_SUCCESS = 0,
76};
77
78enum mlx5_sqp_t {
79 MLX5_SQP_SMI = 0,
80 MLX5_SQP_GSI = 1,
81 MLX5_SQP_IEEE_1588 = 2,
82 MLX5_SQP_SNIFFER = 3,
83 MLX5_SQP_SYNC_UMR = 4,
84};
85
86enum {
87 MLX5_MAX_PORTS = 2,
88};
89
90enum {
91 MLX5_ATOMIC_MODE_OFFSET = 16,
92 MLX5_ATOMIC_MODE_IB_COMP = 1,
93 MLX5_ATOMIC_MODE_CX = 2,
94 MLX5_ATOMIC_MODE_8B = 3,
95 MLX5_ATOMIC_MODE_16B = 4,
96 MLX5_ATOMIC_MODE_32B = 5,
97 MLX5_ATOMIC_MODE_64B = 6,
98 MLX5_ATOMIC_MODE_128B = 7,
99 MLX5_ATOMIC_MODE_256B = 8,
100};
101
102enum {
103 MLX5_REG_QPTS = 0x4002,
104 MLX5_REG_QETCR = 0x4005,
105 MLX5_REG_QTCT = 0x400a,
106 MLX5_REG_QPDPM = 0x4013,
107 MLX5_REG_QCAM = 0x4019,
108 MLX5_REG_DCBX_PARAM = 0x4020,
109 MLX5_REG_DCBX_APP = 0x4021,
110 MLX5_REG_FPGA_CAP = 0x4022,
111 MLX5_REG_FPGA_CTRL = 0x4023,
112 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
113 MLX5_REG_CORE_DUMP = 0x402e,
114 MLX5_REG_PCAP = 0x5001,
115 MLX5_REG_PMTU = 0x5003,
116 MLX5_REG_PTYS = 0x5004,
117 MLX5_REG_PAOS = 0x5006,
118 MLX5_REG_PFCC = 0x5007,
119 MLX5_REG_PPCNT = 0x5008,
120 MLX5_REG_PPTB = 0x500b,
121 MLX5_REG_PBMC = 0x500c,
122 MLX5_REG_PMAOS = 0x5012,
123 MLX5_REG_PUDE = 0x5009,
124 MLX5_REG_PMPE = 0x5010,
125 MLX5_REG_PELC = 0x500e,
126 MLX5_REG_PVLC = 0x500f,
127 MLX5_REG_PCMR = 0x5041,
128 MLX5_REG_PDDR = 0x5031,
129 MLX5_REG_PMLP = 0x5002,
130 MLX5_REG_PPLM = 0x5023,
131 MLX5_REG_PCAM = 0x507f,
132 MLX5_REG_NODE_DESC = 0x6001,
133 MLX5_REG_HOST_ENDIANNESS = 0x7004,
134 MLX5_REG_MCIA = 0x9014,
135 MLX5_REG_MFRL = 0x9028,
136 MLX5_REG_MLCR = 0x902b,
137 MLX5_REG_MRTC = 0x902d,
138 MLX5_REG_MTRC_CAP = 0x9040,
139 MLX5_REG_MTRC_CONF = 0x9041,
140 MLX5_REG_MTRC_STDB = 0x9042,
141 MLX5_REG_MTRC_CTRL = 0x9043,
142 MLX5_REG_MPEIN = 0x9050,
143 MLX5_REG_MPCNT = 0x9051,
144 MLX5_REG_MTPPS = 0x9053,
145 MLX5_REG_MTPPSE = 0x9054,
146 MLX5_REG_MTUTC = 0x9055,
147 MLX5_REG_MPEGC = 0x9056,
148 MLX5_REG_MCQS = 0x9060,
149 MLX5_REG_MCQI = 0x9061,
150 MLX5_REG_MCC = 0x9062,
151 MLX5_REG_MCDA = 0x9063,
152 MLX5_REG_MCAM = 0x907f,
153 MLX5_REG_MIRC = 0x9162,
154 MLX5_REG_SBCAM = 0xB01F,
155 MLX5_REG_RESOURCE_DUMP = 0xC000,
156 MLX5_REG_DTOR = 0xC00E,
157};
158
159enum mlx5_qpts_trust_state {
160 MLX5_QPTS_TRUST_PCP = 1,
161 MLX5_QPTS_TRUST_DSCP = 2,
162};
163
164enum mlx5_dcbx_oper_mode {
165 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
166 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
167};
168
169enum {
170 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
171 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
172 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
173 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
174};
175
176enum mlx5_page_fault_resume_flags {
177 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
178 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
179 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
180 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
181};
182
183enum dbg_rsc_type {
184 MLX5_DBG_RSC_QP,
185 MLX5_DBG_RSC_EQ,
186 MLX5_DBG_RSC_CQ,
187};
188
189enum port_state_policy {
190 MLX5_POLICY_DOWN = 0,
191 MLX5_POLICY_UP = 1,
192 MLX5_POLICY_FOLLOW = 2,
193 MLX5_POLICY_INVALID = 0xffffffff
194};
195
196enum mlx5_coredev_type {
197 MLX5_COREDEV_PF,
198 MLX5_COREDEV_VF,
199 MLX5_COREDEV_SF,
200};
201
202struct mlx5_field_desc {
203 int i;
204};
205
206struct mlx5_rsc_debug {
207 struct mlx5_core_dev *dev;
208 void *object;
209 enum dbg_rsc_type type;
210 struct dentry *root;
211 struct mlx5_field_desc fields[];
212};
213
214enum mlx5_dev_event {
215 MLX5_DEV_EVENT_SYS_ERROR = 128,
216 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
217};
218
219enum mlx5_port_status {
220 MLX5_PORT_UP = 1,
221 MLX5_PORT_DOWN = 2,
222};
223
224enum mlx5_cmdif_state {
225 MLX5_CMDIF_STATE_UNINITIALIZED,
226 MLX5_CMDIF_STATE_UP,
227 MLX5_CMDIF_STATE_DOWN,
228};
229
230struct mlx5_cmd_first {
231 __be32 data[4];
232};
233
234struct mlx5_cmd_msg {
235 struct list_head list;
236 struct cmd_msg_cache *parent;
237 u32 len;
238 struct mlx5_cmd_first first;
239 struct mlx5_cmd_mailbox *next;
240};
241
242struct mlx5_cmd_debug {
243 struct dentry *dbg_root;
244 void *in_msg;
245 void *out_msg;
246 u8 status;
247 u16 inlen;
248 u16 outlen;
249};
250
251struct cmd_msg_cache {
252
253
254 spinlock_t lock;
255 struct list_head head;
256 unsigned int max_inbox_size;
257 unsigned int num_ent;
258};
259
260enum {
261 MLX5_NUM_COMMAND_CACHES = 5,
262};
263
264struct mlx5_cmd_stats {
265 u64 sum;
266 u64 n;
267
268 u64 failed;
269
270 u64 failed_mbox_status;
271
272 u32 last_failed_errno;
273
274 u8 last_failed_mbox_status;
275 struct dentry *root;
276
277 spinlock_t lock;
278};
279
280struct mlx5_cmd {
281 struct mlx5_nb nb;
282
283 enum mlx5_cmdif_state state;
284 void *cmd_alloc_buf;
285 dma_addr_t alloc_dma;
286 int alloc_size;
287 void *cmd_buf;
288 dma_addr_t dma;
289 u16 cmdif_rev;
290 u8 log_sz;
291 u8 log_stride;
292 int max_reg_cmds;
293 int events;
294 u32 __iomem *vector;
295
296
297
298 spinlock_t alloc_lock;
299
300
301
302 spinlock_t token_lock;
303 u8 token;
304 unsigned long bitmask;
305 char wq_name[MLX5_CMD_WQ_MAX_NAME];
306 struct workqueue_struct *wq;
307 struct semaphore sem;
308 struct semaphore pages_sem;
309 int mode;
310 u16 allowed_opcode;
311 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
312 struct dma_pool *pool;
313 struct mlx5_cmd_debug dbg;
314 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
315 int checksum_disabled;
316 struct mlx5_cmd_stats *stats;
317};
318
319struct mlx5_cmd_mailbox {
320 void *buf;
321 dma_addr_t dma;
322 struct mlx5_cmd_mailbox *next;
323};
324
325struct mlx5_buf_list {
326 void *buf;
327 dma_addr_t map;
328};
329
330struct mlx5_frag_buf {
331 struct mlx5_buf_list *frags;
332 int npages;
333 int size;
334 u8 page_shift;
335};
336
337struct mlx5_frag_buf_ctrl {
338 struct mlx5_buf_list *frags;
339 u32 sz_m1;
340 u16 frag_sz_m1;
341 u16 strides_offset;
342 u8 log_sz;
343 u8 log_stride;
344 u8 log_frag_strides;
345};
346
347struct mlx5_core_psv {
348 u32 psv_idx;
349 struct psv_layout {
350 u32 pd;
351 u16 syndrome;
352 u16 reserved;
353 u16 bg;
354 u16 app_tag;
355 u32 ref_tag;
356 } psv;
357};
358
359struct mlx5_core_sig_ctx {
360 struct mlx5_core_psv psv_memory;
361 struct mlx5_core_psv psv_wire;
362 struct ib_sig_err err_item;
363 bool sig_status_checked;
364 bool sig_err_exists;
365 u32 sigerr_count;
366};
367
368#define MLX5_24BIT_MASK ((1 << 24) - 1)
369
370enum mlx5_res_type {
371 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
372 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
373 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
374 MLX5_RES_SRQ = 3,
375 MLX5_RES_XSRQ = 4,
376 MLX5_RES_XRQ = 5,
377 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
378};
379
380struct mlx5_core_rsc_common {
381 enum mlx5_res_type res;
382 refcount_t refcount;
383 struct completion free;
384};
385
386struct mlx5_uars_page {
387 void __iomem *map;
388 bool wc;
389 u32 index;
390 struct list_head list;
391 unsigned int bfregs;
392 unsigned long *reg_bitmap;
393 unsigned long *fp_bitmap;
394 unsigned int reg_avail;
395 unsigned int fp_avail;
396 struct kref ref_count;
397 struct mlx5_core_dev *mdev;
398};
399
400struct mlx5_bfreg_head {
401
402 struct mutex lock;
403 struct list_head list;
404};
405
406struct mlx5_bfreg_data {
407 struct mlx5_bfreg_head reg_head;
408 struct mlx5_bfreg_head wc_head;
409};
410
411struct mlx5_sq_bfreg {
412 void __iomem *map;
413 struct mlx5_uars_page *up;
414 bool wc;
415 u32 index;
416 unsigned int offset;
417};
418
419struct mlx5_core_health {
420 struct health_buffer __iomem *health;
421 __be32 __iomem *health_counter;
422 struct timer_list timer;
423 u32 prev;
424 int miss_counter;
425 u8 synd;
426 u32 fatal_error;
427 u32 crdump_size;
428
429 spinlock_t wq_lock;
430 struct workqueue_struct *wq;
431 unsigned long flags;
432 struct work_struct fatal_report_work;
433 struct work_struct report_work;
434 struct devlink_health_reporter *fw_reporter;
435 struct devlink_health_reporter *fw_fatal_reporter;
436 struct delayed_work update_fw_log_ts_work;
437};
438
439struct mlx5_qp_table {
440 struct notifier_block nb;
441
442
443
444 spinlock_t lock;
445 struct radix_tree_root tree;
446};
447
448struct mlx5_vf_context {
449 int enabled;
450 u64 port_guid;
451 u64 node_guid;
452
453
454
455 u8 port_guid_valid:1;
456 u8 node_guid_valid:1;
457 enum port_state_policy policy;
458};
459
460struct mlx5_core_sriov {
461 struct mlx5_vf_context *vfs_ctx;
462 int num_vfs;
463 u16 max_vfs;
464};
465
466struct mlx5_fc_pool {
467 struct mlx5_core_dev *dev;
468 struct mutex pool_lock;
469 struct list_head fully_used;
470 struct list_head partially_used;
471 struct list_head unused;
472 int available_fcs;
473 int used_fcs;
474 int threshold;
475};
476
477struct mlx5_fc_stats {
478 spinlock_t counters_idr_lock;
479 struct idr counters_idr;
480 struct list_head counters;
481 struct llist_head addlist;
482 struct llist_head dellist;
483
484 struct workqueue_struct *wq;
485 struct delayed_work work;
486 unsigned long next_query;
487 unsigned long sampling_interval;
488 u32 *bulk_query_out;
489 int bulk_query_len;
490 size_t num_counters;
491 bool bulk_query_alloc_failed;
492 unsigned long next_bulk_query_alloc;
493 struct mlx5_fc_pool fc_pool;
494};
495
496struct mlx5_events;
497struct mlx5_mpfs;
498struct mlx5_eswitch;
499struct mlx5_lag;
500struct mlx5_devcom;
501struct mlx5_fw_reset;
502struct mlx5_eq_table;
503struct mlx5_irq_table;
504struct mlx5_vhca_state_notifier;
505struct mlx5_sf_dev_table;
506struct mlx5_sf_hw_table;
507struct mlx5_sf_table;
508
509struct mlx5_rate_limit {
510 u32 rate;
511 u32 max_burst_sz;
512 u16 typical_pkt_sz;
513};
514
515struct mlx5_rl_entry {
516 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
517 u64 refcount;
518 u16 index;
519 u16 uid;
520 u8 dedicated : 1;
521};
522
523struct mlx5_rl_table {
524
525 struct mutex rl_lock;
526 u16 max_size;
527 u32 max_rate;
528 u32 min_rate;
529 struct mlx5_rl_entry *rl_entry;
530 u64 refcount;
531};
532
533struct mlx5_core_roce {
534 struct mlx5_flow_table *ft;
535 struct mlx5_flow_group *fg;
536 struct mlx5_flow_handle *allow_rule;
537};
538
539enum {
540 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
541 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
542
543
544
545 MLX5_PRIV_FLAGS_DETACH = 1 << 2,
546};
547
548struct mlx5_adev {
549 struct auxiliary_device adev;
550 struct mlx5_core_dev *mdev;
551 int idx;
552};
553
554struct mlx5_debugfs_entries {
555 struct dentry *dbg_root;
556 struct dentry *qp_debugfs;
557 struct dentry *eq_debugfs;
558 struct dentry *cq_debugfs;
559 struct dentry *cmdif_debugfs;
560 struct dentry *pages_debugfs;
561};
562
563struct mlx5_ft_pool;
564struct mlx5_priv {
565
566 struct mlx5_irq_table *irq_table;
567 struct mlx5_eq_table *eq_table;
568
569
570 struct mlx5_nb pg_nb;
571 struct workqueue_struct *pg_wq;
572 struct xarray page_root_xa;
573 u32 fw_pages;
574 atomic_t reg_pages;
575 struct list_head free_list;
576 u32 vfs_pages;
577 u32 host_pf_pages;
578 u32 fw_pages_alloc_failed;
579 u32 give_pages_dropped;
580 u32 reclaim_pages_discard;
581
582 struct mlx5_core_health health;
583 struct list_head traps;
584
585 struct mlx5_debugfs_entries dbg;
586
587
588
589 struct mutex alloc_mutex;
590 int numa_node;
591
592 struct mutex pgdir_mutex;
593 struct list_head pgdir_list;
594
595
596 struct list_head ctx_list;
597 spinlock_t ctx_lock;
598 struct mlx5_adev **adev;
599 int adev_idx;
600 struct mlx5_events *events;
601
602 struct mlx5_flow_steering *steering;
603 struct mlx5_mpfs *mpfs;
604 struct mlx5_eswitch *eswitch;
605 struct mlx5_core_sriov sriov;
606 struct mlx5_lag *lag;
607 u32 flags;
608 struct mlx5_devcom *devcom;
609 struct mlx5_fw_reset *fw_reset;
610 struct mlx5_core_roce roce;
611 struct mlx5_fc_stats fc_stats;
612 struct mlx5_rl_table rl_table;
613 struct mlx5_ft_pool *ft_pool;
614
615 struct mlx5_bfreg_data bfregs;
616 struct mlx5_uars_page *uar;
617#ifdef CONFIG_MLX5_SF
618 struct mlx5_vhca_state_notifier *vhca_state_notifier;
619 struct mlx5_sf_dev_table *sf_dev_table;
620 struct mlx5_core_dev *parent_mdev;
621#endif
622#ifdef CONFIG_MLX5_SF_MANAGER
623 struct mlx5_sf_hw_table *sf_hw_table;
624 struct mlx5_sf_table *sf_table;
625#endif
626};
627
628enum mlx5_device_state {
629 MLX5_DEVICE_STATE_UP = 1,
630 MLX5_DEVICE_STATE_INTERNAL_ERROR,
631};
632
633enum mlx5_interface_state {
634 MLX5_INTERFACE_STATE_UP = BIT(0),
635};
636
637enum mlx5_pci_status {
638 MLX5_PCI_STATUS_DISABLED,
639 MLX5_PCI_STATUS_ENABLED,
640};
641
642enum mlx5_pagefault_type_flags {
643 MLX5_PFAULT_REQUESTOR = 1 << 0,
644 MLX5_PFAULT_WRITE = 1 << 1,
645 MLX5_PFAULT_RDMA = 1 << 2,
646};
647
648struct mlx5_td {
649
650 struct mutex list_lock;
651 struct list_head tirs_list;
652 u32 tdn;
653};
654
655struct mlx5e_resources {
656 struct mlx5e_hw_objs {
657 u32 pdn;
658 struct mlx5_td td;
659 u32 mkey;
660 struct mlx5_sq_bfreg bfreg;
661 } hw_objs;
662 struct devlink_port dl_port;
663 struct net_device *uplink_netdev;
664};
665
666enum mlx5_sw_icm_type {
667 MLX5_SW_ICM_TYPE_STEERING,
668 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
669};
670
671#define MLX5_MAX_RESERVED_GIDS 8
672
673struct mlx5_rsvd_gids {
674 unsigned int start;
675 unsigned int count;
676 struct ida ida;
677};
678
679#define MAX_PIN_NUM 8
680struct mlx5_pps {
681 u8 pin_caps[MAX_PIN_NUM];
682 struct work_struct out_work;
683 u64 start[MAX_PIN_NUM];
684 u8 enabled;
685};
686
687struct mlx5_timer {
688 struct cyclecounter cycles;
689 struct timecounter tc;
690 u32 nominal_c_mult;
691 unsigned long overflow_period;
692 struct delayed_work overflow_work;
693};
694
695struct mlx5_clock {
696 struct mlx5_nb pps_nb;
697 seqlock_t lock;
698 struct hwtstamp_config hwtstamp_config;
699 struct ptp_clock *ptp;
700 struct ptp_clock_info ptp_info;
701 struct mlx5_pps pps_info;
702 struct mlx5_timer timer;
703};
704
705struct mlx5_dm;
706struct mlx5_fw_tracer;
707struct mlx5_vxlan;
708struct mlx5_geneve;
709struct mlx5_hv_vhca;
710
711#define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
712#define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
713
714enum {
715 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
716 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
717};
718
719enum {
720 MR_CACHE_LAST_STD_ENTRY = 20,
721 MLX5_IMR_MTT_CACHE_ENTRY,
722 MLX5_IMR_KSM_CACHE_ENTRY,
723 MAX_MR_CACHE_ENTRIES
724};
725
726struct mlx5_profile {
727 u64 mask;
728 u8 log_max_qp;
729 struct {
730 int size;
731 int limit;
732 } mr_cache[MAX_MR_CACHE_ENTRIES];
733};
734
735struct mlx5_hca_cap {
736 u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
737 u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
738};
739
740struct mlx5_core_dev {
741 struct device *device;
742 enum mlx5_coredev_type coredev_type;
743 struct pci_dev *pdev;
744
745 struct mutex pci_status_mutex;
746 enum mlx5_pci_status pci_status;
747 u8 rev_id;
748 char board_id[MLX5_BOARD_ID_LEN];
749 struct mlx5_cmd cmd;
750 struct {
751 struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
752 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
753 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
754 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
755 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
756 u8 embedded_cpu;
757 } caps;
758 struct mlx5_timeouts *timeouts;
759 u64 sys_image_guid;
760 phys_addr_t iseg_base;
761 struct mlx5_init_seg __iomem *iseg;
762 phys_addr_t bar_addr;
763 enum mlx5_device_state state;
764
765 struct mutex intf_state_mutex;
766 unsigned long intf_state;
767 struct mlx5_priv priv;
768 struct mlx5_profile profile;
769 u32 issi;
770 struct mlx5e_resources mlx5e_res;
771 struct mlx5_dm *dm;
772 struct mlx5_vxlan *vxlan;
773 struct mlx5_geneve *geneve;
774 struct {
775 struct mlx5_rsvd_gids reserved_gids;
776 u32 roce_en;
777 } roce;
778#ifdef CONFIG_MLX5_FPGA
779 struct mlx5_fpga_device *fpga;
780#endif
781#ifdef CONFIG_MLX5_ACCEL
782 const struct mlx5_accel_ipsec_ops *ipsec_ops;
783#endif
784 struct mlx5_clock clock;
785 struct mlx5_ib_clock_info *clock_info;
786 struct mlx5_fw_tracer *tracer;
787 struct mlx5_rsc_dump *rsc_dump;
788 u32 vsc_addr;
789 struct mlx5_hv_vhca *hv_vhca;
790};
791
792struct mlx5_db {
793 __be32 *db;
794 union {
795 struct mlx5_db_pgdir *pgdir;
796 struct mlx5_ib_user_db_page *user_page;
797 } u;
798 dma_addr_t dma;
799 int index;
800};
801
802enum {
803 MLX5_COMP_EQ_SIZE = 1024,
804};
805
806enum {
807 MLX5_PTYS_IB = 1 << 0,
808 MLX5_PTYS_EN = 1 << 2,
809};
810
811typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
812
813enum {
814 MLX5_CMD_ENT_STATE_PENDING_COMP,
815};
816
817struct mlx5_cmd_work_ent {
818 unsigned long state;
819 struct mlx5_cmd_msg *in;
820 struct mlx5_cmd_msg *out;
821 void *uout;
822 int uout_size;
823 mlx5_cmd_cbk_t callback;
824 struct delayed_work cb_timeout_work;
825 void *context;
826 int idx;
827 struct completion handling;
828 struct completion done;
829 struct mlx5_cmd *cmd;
830 struct work_struct work;
831 struct mlx5_cmd_layout *lay;
832 int ret;
833 int page_queue;
834 u8 status;
835 u8 token;
836 u64 ts1;
837 u64 ts2;
838 u16 op;
839 bool polling;
840
841 refcount_t refcnt;
842};
843
844struct mlx5_pas {
845 u64 pa;
846 u8 log_sz;
847};
848
849enum phy_port_state {
850 MLX5_AAA_111
851};
852
853struct mlx5_hca_vport_context {
854 u32 field_select;
855 bool sm_virt_aware;
856 bool has_smi;
857 bool has_raw;
858 enum port_state_policy policy;
859 enum phy_port_state phys_state;
860 enum ib_port_state vport_state;
861 u8 port_physical_state;
862 u64 sys_image_guid;
863 u64 port_guid;
864 u64 node_guid;
865 u32 cap_mask1;
866 u32 cap_mask1_perm;
867 u16 cap_mask2;
868 u16 cap_mask2_perm;
869 u16 lid;
870 u8 init_type_reply;
871 u8 lmc;
872 u8 subnet_timeout;
873 u16 sm_lid;
874 u8 sm_sl;
875 u16 qkey_violation_counter;
876 u16 pkey_violation_counter;
877 bool grh_required;
878};
879
880#define STRUCT_FIELD(header, field) \
881 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
882 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
883
884extern struct dentry *mlx5_debugfs_root;
885
886static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
887{
888 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
889}
890
891static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
892{
893 return ioread32be(&dev->iseg->fw_rev) >> 16;
894}
895
896static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
897{
898 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
899}
900
901static inline u32 mlx5_base_mkey(const u32 key)
902{
903 return key & 0xffffff00u;
904}
905
906static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
907{
908 return ((u32)1 << log_sz) << log_stride;
909}
910
911static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
912 u8 log_stride, u8 log_sz,
913 u16 strides_offset,
914 struct mlx5_frag_buf_ctrl *fbc)
915{
916 fbc->frags = frags;
917 fbc->log_stride = log_stride;
918 fbc->log_sz = log_sz;
919 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
920 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
921 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
922 fbc->strides_offset = strides_offset;
923}
924
925static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
926 u8 log_stride, u8 log_sz,
927 struct mlx5_frag_buf_ctrl *fbc)
928{
929 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
930}
931
932static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
933 u32 ix)
934{
935 unsigned int frag;
936
937 ix += fbc->strides_offset;
938 frag = ix >> fbc->log_frag_strides;
939
940 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
941}
942
943static inline u32
944mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
945{
946 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
947
948 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
949}
950
951enum {
952 CMD_ALLOWED_OPCODE_ALL,
953};
954
955void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
956void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
957void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
958
959struct mlx5_async_ctx {
960 struct mlx5_core_dev *dev;
961 atomic_t num_inflight;
962 struct wait_queue_head wait;
963};
964
965struct mlx5_async_work;
966
967typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
968
969struct mlx5_async_work {
970 struct mlx5_async_ctx *ctx;
971 mlx5_async_cbk_t user_callback;
972 u16 opcode;
973 void *out;
974};
975
976void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
977 struct mlx5_async_ctx *ctx);
978void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
979int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
980 void *out, int out_size, mlx5_async_cbk_t callback,
981 struct mlx5_async_work *work);
982void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
983int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
984int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
985int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
986 int out_size);
987
988#define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
989 ({ \
990 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
991 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
992 })
993
994#define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
995 ({ \
996 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
997 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
998 })
999
1000int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1001 void *out, int out_size);
1002bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1003
1004int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
1005void mlx5_health_flush(struct mlx5_core_dev *dev);
1006void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1007int mlx5_health_init(struct mlx5_core_dev *dev);
1008void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1009void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1010void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1011void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1012int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1013 struct mlx5_frag_buf *buf, int node);
1014void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1015struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1016 gfp_t flags, int npages);
1017void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1018 struct mlx5_cmd_mailbox *head);
1019int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1020 int inlen);
1021int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1022int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1023 int outlen);
1024int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1025int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1026int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1027void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1028void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1029void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1030void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1031void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1032void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1033 s32 npages, bool ec_function);
1034int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1035int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1036void mlx5_register_debugfs(void);
1037void mlx5_unregister_debugfs(void);
1038
1039void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1040void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1041int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn);
1042int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1043int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1044
1045struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1046void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1047void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1048int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1049 void *data_out, int size_out, u16 reg_id, int arg,
1050 int write, bool verbose);
1051int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1052 int size_in, void *data_out, int size_out,
1053 u16 reg_num, int arg, int write);
1054
1055int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1056int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1057 int node);
1058void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1059
1060const char *mlx5_command_str(int command);
1061void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1062void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1063int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1064 int npsvs, u32 *sig_index);
1065int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1066void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1067int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1068 struct mlx5_odp_caps *odp_caps);
1069int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1070 u8 port_num, void *out, size_t sz);
1071
1072int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1073void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1074int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1075 struct mlx5_rate_limit *rl);
1076void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1077bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1078int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1079 bool dedicated_entry, u16 *index);
1080void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1081bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1082 struct mlx5_rate_limit *rl_1);
1083int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1084 bool map_wc, bool fast_path);
1085void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1086
1087unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1088struct cpumask *
1089mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1090unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1091int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1092 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1093 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1094
1095static inline u32 mlx5_mkey_to_idx(u32 mkey)
1096{
1097 return mkey >> 8;
1098}
1099
1100static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1101{
1102 return mkey_idx << 8;
1103}
1104
1105static inline u8 mlx5_mkey_variant(u32 mkey)
1106{
1107 return mkey & 0xff;
1108}
1109
1110
1111
1112
1113
1114int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1115int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1116
1117
1118
1119
1120
1121int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1122int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1123
1124
1125int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1126int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1127int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1128 void *data);
1129
1130int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1131
1132int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1133int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1134bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1135bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1136bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1137bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1138bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1139struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1140u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1141 struct net_device *slave);
1142int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1143 u64 *values,
1144 int num_counters,
1145 size_t *offsets);
1146struct mlx5_core_dev *mlx5_lag_get_peer_mdev(struct mlx5_core_dev *dev);
1147struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1148void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1149int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1150 u64 length, u32 log_alignment, u16 uid,
1151 phys_addr_t *addr, u32 *obj_id);
1152int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1153 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1154
1155struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1156void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1157
1158#ifdef CONFIG_MLX5_CORE_IPOIB
1159struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1160 struct ib_device *ibdev,
1161 const char *name,
1162 void (*setup)(struct net_device *));
1163#endif
1164int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1165 struct ib_device *device,
1166 struct rdma_netdev_alloc_params *params);
1167
1168enum {
1169 MLX5_PCI_DEV_IS_VF = 1 << 0,
1170};
1171
1172static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1173{
1174 return dev->coredev_type == MLX5_COREDEV_PF;
1175}
1176
1177static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1178{
1179 return dev->coredev_type == MLX5_COREDEV_VF;
1180}
1181
1182static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1183{
1184 return dev->caps.embedded_cpu;
1185}
1186
1187static inline bool
1188mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1189{
1190 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1191}
1192
1193static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1194{
1195 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1196}
1197
1198static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1199{
1200 return dev->priv.sriov.max_vfs;
1201}
1202
1203static inline int mlx5_get_gid_table_len(u16 param)
1204{
1205 if (param > 4) {
1206 pr_warn("gid table length is zero\n");
1207 return 0;
1208 }
1209
1210 return 8 * (1 << param);
1211}
1212
1213static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1214{
1215 return !!(dev->priv.rl_table.max_size);
1216}
1217
1218static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1219{
1220 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1221 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1222}
1223
1224static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1225{
1226 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1227}
1228
1229static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1230{
1231 return mlx5_core_is_mp_slave(dev) ||
1232 mlx5_core_is_mp_master(dev);
1233}
1234
1235static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1236{
1237 if (!mlx5_core_mp_enabled(dev))
1238 return 1;
1239
1240 return MLX5_CAP_GEN(dev, native_port_num);
1241}
1242
1243static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1244{
1245 int idx = MLX5_CAP_GEN(dev, native_port_num);
1246
1247 if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1248 return idx - 1;
1249 else
1250 return PCI_FUNC(dev->pdev->devfn);
1251}
1252
1253enum {
1254 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1255};
1256
1257static inline bool mlx5_is_roce_init_enabled(struct mlx5_core_dev *dev)
1258{
1259 struct devlink *devlink = priv_to_devlink(dev);
1260 union devlink_param_value val;
1261 int err;
1262
1263 err = devlink_param_driverinit_value_get(devlink,
1264 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1265 &val);
1266 return err ? MLX5_CAP_GEN(dev, roce) : val.vbool;
1267}
1268
1269#endif
1270
