LXR linux/include/linux/soc/samsung/s3c-cpu-freq.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (c) 2006-2007 Simtec Electronics
   4 *      http://armlinux.simtec.co.uk/
   5 *      Ben Dooks <ben@simtec.co.uk>
   6 *
   7 * S3C CPU frequency scaling support - driver and board
   8 */
   9#ifndef __LINUX_SOC_SAMSUNG_S3C_CPU_FREQ_H
  10#define __LINUX_SOC_SAMSUNG_S3C_CPU_FREQ_H
  11
  12#include <linux/cpufreq.h>
  13
  14struct s3c_cpufreq_info;
  15struct s3c_cpufreq_board;
  16struct s3c_iotimings;
  17
  18/**
  19 * struct s3c_freq - frequency information (mainly for core drivers)
  20 * @fclk: The FCLK frequency in Hz.
  21 * @armclk: The ARMCLK frequency in Hz.
  22 * @hclk_tns: HCLK cycle time in 10ths of nano-seconds.
  23 * @hclk: The HCLK frequency in Hz.
  24 * @pclk: The PCLK frequency in Hz.
  25 *
  26 * This contains the frequency information about the current configuration
  27 * mainly for the core drivers to ensure we do not end up passing about
  28 * a large number of parameters.
  29 *
  30 * The @hclk_tns field is a useful cache for the parts of the drivers that
  31 * need to calculate IO timings and suchlike.
  32 */
  33struct s3c_freq {
  34        unsigned long   fclk;
  35        unsigned long   armclk;
  36        unsigned long   hclk_tns;       /* in 10ths of ns */
  37        unsigned long   hclk;
  38        unsigned long   pclk;
  39};
  40
  41/**
  42 * struct s3c_cpufreq_freqs - s3c cpufreq notification information.
  43 * @freqs: The cpufreq setting information.
  44 * @old: The old clock settings.
  45 * @new: The new clock settings.
  46 * @pll_changing: Set if the PLL is changing.
  47 *
  48 * Wrapper 'struct cpufreq_freqs' so that any drivers receiving the
  49 * notification can use this information that is not provided by just
  50 * having the core frequency alone.
  51 *
  52 * The pll_changing flag is used to indicate if the PLL itself is
  53 * being set during this change. This is important as the clocks
  54 * will temporarily be set to the XTAL clock during this time, so
  55 * drivers may want to close down their output during this time.
  56 *
  57 * Note, this is not being used by any current drivers and therefore
  58 * may be removed in the future.
  59 */
  60struct s3c_cpufreq_freqs {
  61        struct cpufreq_freqs    freqs;
  62        struct s3c_freq         old;
  63        struct s3c_freq         new;
  64
  65        unsigned int            pll_changing:1;
  66};
  67
  68#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
  69
  70/**
  71 * struct s3c_clkdivs - clock divisor information
  72 * @p_divisor: Divisor from FCLK to PCLK.
  73 * @h_divisor: Divisor from FCLK to HCLK.
  74 * @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs).
  75 * @dvs: Non-zero if using DVS mode for ARMCLK.
  76 *
  77 * Divisor settings for the core clocks.
  78 */
  79struct s3c_clkdivs {
  80        int             p_divisor;
  81        int             h_divisor;
  82        int             arm_divisor;
  83        unsigned char   dvs;
  84};
  85
  86#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
  87
  88/**
  89 * struct s3c_pllval - PLL value entry.
  90 * @freq: The frequency for this entry in Hz.
  91 * @pll_reg: The PLL register setting for this PLL value.
  92 */
  93struct s3c_pllval {
  94        unsigned long           freq;
  95        unsigned long           pll_reg;
  96};
  97
  98/**
  99 * struct s3c_cpufreq_board - per-board cpu frequency informatin
 100 * @refresh: The SDRAM refresh period in nanoseconds.
 101 * @auto_io: Set if the IO timing settings should be generated from the
 102 *      initialisation time hardware registers.
 103 * @need_io: Set if the board has external IO on any of the chipselect
 104 *      lines that will require the hardware timing registers to be
 105 *      updated on a clock change.
 106 * @max: The maxium frequency limits for the system. Any field that
 107 *      is left at zero will use the CPU's settings.
 108 *
 109 * This contains the board specific settings that affect how the CPU
 110 * drivers chose settings. These include the memory refresh and IO
 111 * timing information.
 112 *
 113 * Registration depends on the driver being used, the ARMCLK only
 114 * implementation does not currently need this but the older style
 115 * driver requires this to be available.
 116 */
 117struct s3c_cpufreq_board {
 118        unsigned int    refresh;
 119        unsigned int    auto_io:1;      /* automatically init io timings. */
 120        unsigned int    need_io:1;      /* set if needs io timing support. */
 121
 122        /* any non-zero field in here is taken as an upper limit. */
 123        struct s3c_freq max;    /* frequency limits */
 124};
 125
 126/* Things depending on frequency scaling. */
 127#ifdef CONFIG_ARM_S3C_CPUFREQ
 128#define __init_or_cpufreq
 129#else
 130#define __init_or_cpufreq __init
 131#endif
 132
 133/* Board functions */
 134
 135#ifdef CONFIG_ARM_S3C_CPUFREQ
 136extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board);
 137#else
 138
 139static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
 140{
 141        return 0;
 142}
 143#endif  /* CONFIG_ARM_S3C_CPUFREQ */
 144
 145#endif
 146