LXR linux/sound/soc/sof/intel/hda-dsp.c

   1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
   2//
   3// This file is provided under a dual BSD/GPLv2 license.  When using or
   4// redistributing this file, you may do so under either license.
   5//
   6// Copyright(c) 2018 Intel Corporation. All rights reserved.
   7//
   8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
   9//          Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
  10//          Rander Wang <rander.wang@intel.com>
  11//          Keyon Jie <yang.jie@linux.intel.com>
  12//
  13
  14/*
  15 * Hardware interface for generic Intel audio DSP HDA IP
  16 */
  17
  18#include <linux/module.h>
  19#include <sound/hdaudio_ext.h>
  20#include <sound/hda_register.h>
  21#include "../sof-audio.h"
  22#include "../ops.h"
  23#include "hda.h"
  24#include "hda-ipc.h"
  25
  26static bool hda_enable_trace_D0I3_S0;
  27#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
  28module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444);
  29MODULE_PARM_DESC(enable_trace_D0I3_S0,
  30                 "SOF HDA enable trace when the DSP is in D0I3 in S0");
  31#endif
  32
  33/*
  34 * DSP Core control.
  35 */
  36
  37static int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
  38{
  39        u32 adspcs;
  40        u32 reset;
  41        int ret;
  42
  43        /* set reset bits for cores */
  44        reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
  45        snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
  46                                         HDA_DSP_REG_ADSPCS,
  47                                         reset, reset);
  48
  49        /* poll with timeout to check if operation successful */
  50        ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
  51                                        HDA_DSP_REG_ADSPCS, adspcs,
  52                                        ((adspcs & reset) == reset),
  53                                        HDA_DSP_REG_POLL_INTERVAL_US,
  54                                        HDA_DSP_RESET_TIMEOUT_US);
  55        if (ret < 0) {
  56                dev_err(sdev->dev,
  57                        "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
  58                        __func__);
  59                return ret;
  60        }
  61
  62        /* has core entered reset ? */
  63        adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
  64                                  HDA_DSP_REG_ADSPCS);
  65        if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
  66                HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
  67                dev_err(sdev->dev,
  68                        "error: reset enter failed: core_mask %x adspcs 0x%x\n",
  69                        core_mask, adspcs);
  70                ret = -EIO;
  71        }
  72
  73        return ret;
  74}
  75
  76static int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
  77{
  78        unsigned int crst;
  79        u32 adspcs;
  80        int ret;
  81
  82        /* clear reset bits for cores */
  83        snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
  84                                         HDA_DSP_REG_ADSPCS,
  85                                         HDA_DSP_ADSPCS_CRST_MASK(core_mask),
  86                                         0);
  87
  88        /* poll with timeout to check if operation successful */
  89        crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
  90        ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
  91                                            HDA_DSP_REG_ADSPCS, adspcs,
  92                                            !(adspcs & crst),
  93                                            HDA_DSP_REG_POLL_INTERVAL_US,
  94                                            HDA_DSP_RESET_TIMEOUT_US);
  95
  96        if (ret < 0) {
  97                dev_err(sdev->dev,
  98                        "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
  99                        __func__);
 100                return ret;
 101        }
 102
 103        /* has core left reset ? */
 104        adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
 105                                  HDA_DSP_REG_ADSPCS);
 106        if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
 107                dev_err(sdev->dev,
 108                        "error: reset leave failed: core_mask %x adspcs 0x%x\n",
 109                        core_mask, adspcs);
 110                ret = -EIO;
 111        }
 112
 113        return ret;
 114}
 115
 116static int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
 117{
 118        /* stall core */
 119        snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
 120                                         HDA_DSP_REG_ADSPCS,
 121                                         HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
 122                                         HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
 123
 124        /* set reset state */
 125        return hda_dsp_core_reset_enter(sdev, core_mask);
 126}
 127
 128static bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask)
 129{
 130        int val;
 131        bool is_enable;
 132
 133        val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
 134
 135#define MASK_IS_EQUAL(v, m, field) ({   \
 136        u32 _m = field(m);              \
 137        ((v) & _m) == _m;               \
 138})
 139
 140        is_enable = MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_CPA_MASK) &&
 141                MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_SPA_MASK) &&
 142                !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
 143                !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
 144
 145#undef MASK_IS_EQUAL
 146
 147        dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
 148                is_enable, core_mask);
 149
 150        return is_enable;
 151}
 152
 153int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
 154{
 155        int ret;
 156
 157        /* leave reset state */
 158        ret = hda_dsp_core_reset_leave(sdev, core_mask);
 159        if (ret < 0)
 160                return ret;
 161
 162        /* run core */
 163        dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
 164        snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
 165                                         HDA_DSP_REG_ADSPCS,
 166                                         HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
 167                                         0);
 168
 169        /* is core now running ? */
 170        if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
 171                hda_dsp_core_stall_reset(sdev, core_mask);
 172                dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
 173                        core_mask);
 174                ret = -EIO;
 175        }
 176
 177        return ret;
 178}
 179
 180/*
 181 * Power Management.
 182 */
 183
 184static int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
 185{
 186        unsigned int cpa;
 187        u32 adspcs;
 188        int ret;
 189
 190        /* update bits */
 191        snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
 192                                HDA_DSP_ADSPCS_SPA_MASK(core_mask),
 193                                HDA_DSP_ADSPCS_SPA_MASK(core_mask));
 194
 195        /* poll with timeout to check if operation successful */
 196        cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask);
 197        ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
 198                                            HDA_DSP_REG_ADSPCS, adspcs,
 199                                            (adspcs & cpa) == cpa,
 200                                            HDA_DSP_REG_POLL_INTERVAL_US,
 201                                            HDA_DSP_RESET_TIMEOUT_US);
 202        if (ret < 0) {
 203                dev_err(sdev->dev,
 204                        "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
 205                        __func__);
 206                return ret;
 207        }
 208
 209        /* did core power up ? */
 210        adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
 211                                  HDA_DSP_REG_ADSPCS);
 212        if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
 213                HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
 214                dev_err(sdev->dev,
 215                        "error: power up core failed core_mask %xadspcs 0x%x\n",
 216                        core_mask, adspcs);
 217                ret = -EIO;
 218        }
 219
 220        return ret;
 221}
 222
 223static int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
 224{
 225        u32 adspcs;
 226        int ret;
 227
 228        /* update bits */
 229        snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
 230                                         HDA_DSP_REG_ADSPCS,
 231                                         HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
 232
 233        ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
 234                                HDA_DSP_REG_ADSPCS, adspcs,
 235                                !(adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)),
 236                                HDA_DSP_REG_POLL_INTERVAL_US,
 237                                HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
 238        if (ret < 0)
 239                dev_err(sdev->dev,
 240                        "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
 241                        __func__);
 242
 243        return ret;
 244}
 245
 246int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
 247{
 248        struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
 249        const struct sof_intel_dsp_desc *chip = hda->desc;
 250        int ret;
 251
 252        /* restrict core_mask to host managed cores mask */
 253        core_mask &= chip->host_managed_cores_mask;
 254
 255        /* return if core_mask is not valid or cores are already enabled */
 256        if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask))
 257                return 0;
 258
 259        /* power up */
 260        ret = hda_dsp_core_power_up(sdev, core_mask);
 261        if (ret < 0) {
 262                dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
 263                        core_mask);
 264                return ret;
 265        }
 266
 267        return hda_dsp_core_run(sdev, core_mask);
 268}
 269
 270int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
 271                                  unsigned int core_mask)
 272{
 273        struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
 274        const struct sof_intel_dsp_desc *chip = hda->desc;
 275        int ret;
 276
 277        /* restrict core_mask to host managed cores mask */
 278        core_mask &= chip->host_managed_cores_mask;
 279
 280        /* return if core_mask is not valid */
 281        if (!core_mask)
 282                return 0;
 283
 284        /* place core in reset prior to power down */
 285        ret = hda_dsp_core_stall_reset(sdev, core_mask);
 286        if (ret < 0) {
 287                dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
 288                        core_mask);
 289                return ret;
 290        }
 291
 292        /* power down core */
 293        ret = hda_dsp_core_power_down(sdev, core_mask);
 294        if (ret < 0) {
 295                dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
 296                        core_mask, ret);
 297                return ret;
 298        }
 299
 300        /* make sure we are in OFF state */
 301        if (hda_dsp_core_is_enabled(sdev, core_mask)) {
 302                dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
 303                        core_mask, ret);
 304                ret = -EIO;
 305        }
 306
 307        return ret;
 308}
 309
 310void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
 311{
 312        struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
 313        const struct sof_intel_dsp_desc *chip = hda->desc;
 314
 315        /* enable IPC DONE and BUSY interrupts */
 316        snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
 317                        HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY,
 318                        HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY);
 319
 320        /* enable IPC interrupt */
 321        snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
 322                                HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
 323}
 324
 325void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
 326{
 327        struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
 328        const struct sof_intel_dsp_desc *chip = hda->desc;
 329
 330        /* disable IPC interrupt */
 331        snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
 332                                HDA_DSP_ADSPIC_IPC, 0);
 333
 334        /* disable IPC BUSY and DONE interrupt */
 335        snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
 336                        HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
 337}
 338
 339static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
 340{
 341        struct hdac_bus *bus = sof_to_bus(sdev);
 342        int retry = HDA_DSP_REG_POLL_RETRY_COUNT;
 343
 344        while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) {
 345                if (!retry--)
 346                        return -ETIMEDOUT;
 347                usleep_range(10, 15);
 348        }
 349
 350        return 0;
 351}
 352
 353static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
 354{
 355        struct sof_ipc_pm_gate pm_gate;
 356        struct sof_ipc_reply reply;
 357
 358        memset(&pm_gate, 0, sizeof(pm_gate));
 359
 360        /* configure pm_gate ipc message */
 361        pm_gate.hdr.size = sizeof(pm_gate);
 362        pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
 363        pm_gate.flags = flags;
 364
 365        /* send pm_gate ipc to dsp */
 366        return sof_ipc_tx_message_no_pm(sdev->ipc, pm_gate.hdr.cmd,
 367                                        &pm_gate, sizeof(pm_gate), &reply,
 368                                        sizeof(reply));
 369}
 370
 371static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
 372{
 373        struct hdac_bus *bus = sof_to_bus(sdev);
 374        int ret;
 375
 376        /* Write to D0I3C after Command-In-Progress bit is cleared */
 377        ret = hda_dsp_wait_d0i3c_done(sdev);
 378        if (ret < 0) {
 379                dev_err(bus->dev, "CIP timeout before D0I3C update!\n");
 380                return ret;
 381        }
 382
 383        /* Update D0I3C register */
 384        snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
 385
 386        /* Wait for cmd in progress to be cleared before exiting the function */
 387        ret = hda_dsp_wait_d0i3c_done(sdev);
 388        if (ret < 0) {
 389                dev_err(bus->dev, "CIP timeout after D0I3C update!\n");
 390                return ret;
 391        }
 392
 393        dev_vdbg(bus->dev, "D0I3C updated, register = 0x%x\n",
 394                 snd_hdac_chip_readb(bus, VS_D0I3C));
 395
 396        return 0;
 397}
 398
 399static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev,
 400                                const struct sof_dsp_power_state *target_state)
 401{
 402        u32 flags = 0;
 403        int ret;
 404        u8 value = 0;
 405
 406        /*
 407         * Sanity check for illegal state transitions
 408         * The only allowed transitions are:
 409         * 1. D3 -> D0I0
 410         * 2. D0I0 -> D0I3
 411         * 3. D0I3 -> D0I0
 412         */
 413        switch (sdev->dsp_power_state.state) {
 414        case SOF_DSP_PM_D0:
 415                /* Follow the sequence below for D0 substate transitions */
 416                break;
 417        case SOF_DSP_PM_D3:
 418                /* Follow regular flow for D3 -> D0 transition */
 419                return 0;
 420        default:
 421                dev_err(sdev->dev, "error: transition from %d to %d not allowed\n",
 422                        sdev->dsp_power_state.state, target_state->state);
 423                return -EINVAL;
 424        }
 425
 426        /* Set flags and register value for D0 target substate */
 427        if (target_state->substate == SOF_HDA_DSP_PM_D0I3) {
 428                value = SOF_HDA_VS_D0I3C_I3;
 429
 430                /*
 431                 * Trace DMA need to be disabled when the DSP enters
 432                 * D0I3 for S0Ix suspend, but it can be kept enabled
 433                 * when the DSP enters D0I3 while the system is in S0
 434                 * for debug purpose.
 435                 */
 436                if (!sdev->dtrace_is_supported ||
 437                    !hda_enable_trace_D0I3_S0 ||
 438                    sdev->system_suspend_target != SOF_SUSPEND_NONE)
 439                        flags = HDA_PM_NO_DMA_TRACE;
 440        } else {
 441                /* prevent power gating in D0I0 */
 442                flags = HDA_PM_PPG;
 443        }
 444
 445        /* update D0I3C register */
 446        ret = hda_dsp_update_d0i3c_register(sdev, value);
 447        if (ret < 0)
 448                return ret;
 449
 450        /*
 451         * Notify the DSP of the state change.
 452         * If this IPC fails, revert the D0I3C register update in order
 453         * to prevent partial state change.
 454         */
 455        ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
 456        if (ret < 0) {
 457                dev_err(sdev->dev,
 458                        "error: PM_GATE ipc error %d\n", ret);
 459                goto revert;
 460        }
 461
 462        return ret;
 463
 464revert:
 465        /* fallback to the previous register value */
 466        value = value ? 0 : SOF_HDA_VS_D0I3C_I3;
 467
 468        /*
 469         * This can fail but return the IPC error to signal that
 470         * the state change failed.
 471         */
 472        hda_dsp_update_d0i3c_register(sdev, value);
 473
 474        return ret;
 475}
 476
 477/* helper to log DSP state */
 478static void hda_dsp_state_log(struct snd_sof_dev *sdev)
 479{
 480        switch (sdev->dsp_power_state.state) {
 481        case SOF_DSP_PM_D0:
 482                switch (sdev->dsp_power_state.substate) {
 483                case SOF_HDA_DSP_PM_D0I0:
 484                        dev_dbg(sdev->dev, "Current DSP power state: D0I0\n");
 485                        break;
 486                case SOF_HDA_DSP_PM_D0I3:
 487                        dev_dbg(sdev->dev, "Current DSP power state: D0I3\n");
 488                        break;
 489                default:
 490                        dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n",
 491                                sdev->dsp_power_state.substate);
 492                        break;
 493                }
 494                break;
 495        case SOF_DSP_PM_D1:
 496                dev_dbg(sdev->dev, "Current DSP power state: D1\n");
 497                break;
 498        case SOF_DSP_PM_D2:
 499                dev_dbg(sdev->dev, "Current DSP power state: D2\n");
 500                break;
 501        case SOF_DSP_PM_D3:
 502                dev_dbg(sdev->dev, "Current DSP power state: D3\n");
 503                break;
 504        default:
 505                dev_dbg(sdev->dev, "Unknown DSP power state: %d\n",
 506                        sdev->dsp_power_state.state);
 507                break;
 508        }
 509}
 510
 511/*
 512 * All DSP power state transitions are initiated by the driver.
 513 * If the requested state change fails, the error is simply returned.
 514 * Further state transitions are attempted only when the set_power_save() op
 515 * is called again either because of a new IPC sent to the DSP or
 516 * during system suspend/resume.
 517 */
 518int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
 519                            const struct sof_dsp_power_state *target_state)
 520{
 521        int ret = 0;
 522
 523        /*
 524         * When the DSP is already in D0I3 and the target state is D0I3,
 525         * it could be the case that the DSP is in D0I3 during S0
 526         * and the system is suspending to S0Ix. Therefore,
 527         * hda_dsp_set_D0_state() must be called to disable trace DMA
 528         * by sending the PM_GATE IPC to the FW.
 529         */
 530        if (target_state->substate == SOF_HDA_DSP_PM_D0I3 &&
 531            sdev->system_suspend_target == SOF_SUSPEND_S0IX)
 532                goto set_state;
 533
 534        /*
 535         * For all other cases, return without doing anything if
 536         * the DSP is already in the target state.
 537         */
 538        if (target_state->state == sdev->dsp_power_state.state &&
 539            target_state->substate == sdev->dsp_power_state.substate)
 540                return 0;
 541
 542set_state:
 543        switch (target_state->state) {
 544        case SOF_DSP_PM_D0:
 545                ret = hda_dsp_set_D0_state(sdev, target_state);
 546                break;
 547        case SOF_DSP_PM_D3:
 548                /* The only allowed transition is: D0I0 -> D3 */
 549                if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 &&
 550                    sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0)
 551                        break;
 552
 553                dev_err(sdev->dev,
 554                        "error: transition from %d to %d not allowed\n",
 555                        sdev->dsp_power_state.state, target_state->state);
 556                return -EINVAL;
 557        default:
 558                dev_err(sdev->dev, "error: target state unsupported %d\n",
 559                        target_state->state);
 560                return -EINVAL;
 561        }
 562        if (ret < 0) {
 563                dev_err(sdev->dev,
 564                        "failed to set requested target DSP state %d substate %d\n",
 565                        target_state->state, target_state->substate);
 566                return ret;
 567        }
 568
 569        sdev->dsp_power_state = *target_state;
 570        hda_dsp_state_log(sdev);
 571        return ret;
 572}
 573
 574/*
 575 * Audio DSP states may transform as below:-
 576 *
 577 *                                         Opportunistic D0I3 in S0
 578 *     Runtime    +---------------------+  Delayed D0i3 work timeout
 579 *     suspend    |                     +--------------------+
 580 *   +------------+       D0I0(active)  |                    |
 581 *   |            |                     <---------------+    |
 582 *   |   +-------->                     |    New IPC    |    |
 583 *   |   |Runtime +--^--+---------^--+--+ (via mailbox) |    |
 584 *   |   |resume     |  |         |  |                  |    |
 585 *   |   |           |  |         |  |                  |    |
 586 *   |   |     System|  |         |  |                  |    |
 587 *   |   |     resume|  | S3/S0IX |  |                  |    |
 588 *   |   |           |  | suspend |  | S0IX             |    |
 589 *   |   |           |  |         |  |suspend           |    |
 590 *   |   |           |  |         |  |                  |    |
 591 *   |   |           |  |         |  |                  |    |
 592 * +-v---+-----------+--v-------+ |  |           +------+----v----+
 593 * |                            | |  +----------->                |
 594 * |       D3 (suspended)       | |              |      D0I3      |
 595 * |                            | +--------------+                |
 596 * |                            |  System resume |                |
 597 * +----------------------------+                +----------------+
 598 *
 599 * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams
 600 *               ignored the suspend trigger. Otherwise the DSP
 601 *               is in D3.
 602 */
 603
 604static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
 605{
 606        struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
 607        const struct sof_intel_dsp_desc *chip = hda->desc;
 608#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 609        struct hdac_bus *bus = sof_to_bus(sdev);
 610#endif
 611        int ret, j;
 612
 613        hda_sdw_int_enable(sdev, false);
 614
 615        /* disable IPC interrupts */
 616        hda_dsp_ipc_int_disable(sdev);
 617
 618#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 619        hda_codec_jack_wake_enable(sdev, runtime_suspend);
 620
 621        /* power down all hda link */
 622        snd_hdac_ext_bus_link_power_down_all(bus);
 623#endif
 624
 625        /* power down DSP */
 626        ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
 627        if (ret < 0) {
 628                dev_err(sdev->dev,
 629                        "error: failed to power down core during suspend\n");
 630                return ret;
 631        }
 632
 633        /* reset ref counts for all cores */
 634        for (j = 0; j < chip->cores_num; j++)
 635                sdev->dsp_core_ref_count[j] = 0;
 636
 637        /* disable ppcap interrupt */
 638        hda_dsp_ctrl_ppcap_enable(sdev, false);
 639        hda_dsp_ctrl_ppcap_int_enable(sdev, false);
 640
 641        /* disable hda bus irq and streams */
 642        hda_dsp_ctrl_stop_chip(sdev);
 643
 644        /* disable LP retention mode */
 645        snd_sof_pci_update_bits(sdev, PCI_PGCTL,
 646                                PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
 647
 648        /* reset controller */
 649        ret = hda_dsp_ctrl_link_reset(sdev, true);
 650        if (ret < 0) {
 651                dev_err(sdev->dev,
 652                        "error: failed to reset controller during suspend\n");
 653                return ret;
 654        }
 655
 656        /* display codec can powered off after link reset */
 657        hda_codec_i915_display_power(sdev, false);
 658
 659        return 0;
 660}
 661
 662static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
 663{
 664#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 665        struct hdac_bus *bus = sof_to_bus(sdev);
 666        struct hdac_ext_link *hlink = NULL;
 667#endif
 668        int ret;
 669
 670        /* display codec must be powered before link reset */
 671        hda_codec_i915_display_power(sdev, true);
 672
 673        /*
 674         * clear TCSEL to clear playback on some HD Audio
 675         * codecs. PCI TCSEL is defined in the Intel manuals.
 676         */
 677        snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
 678
 679        /* reset and start hda controller */
 680        ret = hda_dsp_ctrl_init_chip(sdev, true);
 681        if (ret < 0) {
 682                dev_err(sdev->dev,
 683                        "error: failed to start controller after resume\n");
 684                goto cleanup;
 685        }
 686
 687#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 688        /* check jack status */
 689        if (runtime_resume) {
 690                hda_codec_jack_wake_enable(sdev, false);
 691                if (sdev->system_suspend_target == SOF_SUSPEND_NONE)
 692                        hda_codec_jack_check(sdev);
 693        }
 694
 695        /* turn off the links that were off before suspend */
 696        list_for_each_entry(hlink, &bus->hlink_list, list) {
 697                if (!hlink->ref_count)
 698                        snd_hdac_ext_bus_link_power_down(hlink);
 699        }
 700
 701        /* check dma status and clean up CORB/RIRB buffers */
 702        if (!bus->cmd_dma_state)
 703                snd_hdac_bus_stop_cmd_io(bus);
 704#endif
 705
 706        /* enable ppcap interrupt */
 707        hda_dsp_ctrl_ppcap_enable(sdev, true);
 708        hda_dsp_ctrl_ppcap_int_enable(sdev, true);
 709
 710cleanup:
 711        /* display codec can powered off after controller init */
 712        hda_codec_i915_display_power(sdev, false);
 713
 714        return 0;
 715}
 716
 717int hda_dsp_resume(struct snd_sof_dev *sdev)
 718{
 719        struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
 720        struct pci_dev *pci = to_pci_dev(sdev->dev);
 721        const struct sof_dsp_power_state target_state = {
 722                .state = SOF_DSP_PM_D0,
 723                .substate = SOF_HDA_DSP_PM_D0I0,
 724        };
 725#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 726        struct hdac_bus *bus = sof_to_bus(sdev);
 727        struct hdac_ext_link *hlink = NULL;
 728#endif
 729        int ret;
 730
 731        /* resume from D0I3 */
 732        if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) {
 733#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 734                /* power up links that were active before suspend */
 735                list_for_each_entry(hlink, &bus->hlink_list, list) {
 736                        if (hlink->ref_count) {
 737                                ret = snd_hdac_ext_bus_link_power_up(hlink);
 738                                if (ret < 0) {
 739                                        dev_dbg(sdev->dev,
 740                                                "error %d in %s: failed to power up links",
 741                                                ret, __func__);
 742                                        return ret;
 743                                }
 744                        }
 745                }
 746
 747                /* set up CORB/RIRB buffers if was on before suspend */
 748                if (bus->cmd_dma_state)
 749                        snd_hdac_bus_init_cmd_io(bus);
 750#endif
 751
 752                /* Set DSP power state */
 753                ret = snd_sof_dsp_set_power_state(sdev, &target_state);
 754                if (ret < 0) {
 755                        dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
 756                                target_state.state, target_state.substate);
 757                        return ret;
 758                }
 759
 760                /* restore L1SEN bit */
 761                if (hda->l1_support_changed)
 762                        snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
 763                                                HDA_VS_INTEL_EM2,
 764                                                HDA_VS_INTEL_EM2_L1SEN, 0);
 765
 766                /* restore and disable the system wakeup */
 767                pci_restore_state(pci);
 768                disable_irq_wake(pci->irq);
 769                return 0;
 770        }
 771
 772        /* init hda controller. DSP cores will be powered up during fw boot */
 773        ret = hda_resume(sdev, false);
 774        if (ret < 0)
 775                return ret;
 776
 777        return snd_sof_dsp_set_power_state(sdev, &target_state);
 778}
 779
 780int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
 781{
 782        const struct sof_dsp_power_state target_state = {
 783                .state = SOF_DSP_PM_D0,
 784        };
 785        int ret;
 786
 787        /* init hda controller. DSP cores will be powered up during fw boot */
 788        ret = hda_resume(sdev, true);
 789        if (ret < 0)
 790                return ret;
 791
 792        return snd_sof_dsp_set_power_state(sdev, &target_state);
 793}
 794
 795int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
 796{
 797        struct hdac_bus *hbus = sof_to_bus(sdev);
 798
 799        if (hbus->codec_powered) {
 800                dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
 801                        (unsigned int)hbus->codec_powered);
 802                return -EBUSY;
 803        }
 804
 805        return 0;
 806}
 807
 808int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
 809{
 810        struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
 811        const struct sof_dsp_power_state target_state = {
 812                .state = SOF_DSP_PM_D3,
 813        };
 814        int ret;
 815
 816        /* cancel any attempt for DSP D0I3 */
 817        cancel_delayed_work_sync(&hda->d0i3_work);
 818
 819        /* stop hda controller and power dsp off */
 820        ret = hda_suspend(sdev, true);
 821        if (ret < 0)
 822                return ret;
 823
 824        return snd_sof_dsp_set_power_state(sdev, &target_state);
 825}
 826
 827int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
 828{
 829        struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
 830        struct hdac_bus *bus = sof_to_bus(sdev);
 831        struct pci_dev *pci = to_pci_dev(sdev->dev);
 832        const struct sof_dsp_power_state target_dsp_state = {
 833                .state = target_state,
 834                .substate = target_state == SOF_DSP_PM_D0 ?
 835                                SOF_HDA_DSP_PM_D0I3 : 0,
 836        };
 837        int ret;
 838
 839        /* cancel any attempt for DSP D0I3 */
 840        cancel_delayed_work_sync(&hda->d0i3_work);
 841
 842        if (target_state == SOF_DSP_PM_D0) {
 843                /* Set DSP power state */
 844                ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
 845                if (ret < 0) {
 846                        dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
 847                                target_dsp_state.state,
 848                                target_dsp_state.substate);
 849                        return ret;
 850                }
 851
 852                /* enable L1SEN to make sure the system can enter S0Ix */
 853                hda->l1_support_changed =
 854                        snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
 855                                                HDA_VS_INTEL_EM2,
 856                                                HDA_VS_INTEL_EM2_L1SEN,
 857                                                HDA_VS_INTEL_EM2_L1SEN);
 858
 859#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 860                /* stop the CORB/RIRB DMA if it is On */
 861                if (bus->cmd_dma_state)
 862                        snd_hdac_bus_stop_cmd_io(bus);
 863
 864                /* no link can be powered in s0ix state */
 865                ret = snd_hdac_ext_bus_link_power_down_all(bus);
 866                if (ret < 0) {
 867                        dev_dbg(sdev->dev,
 868                                "error %d in %s: failed to power down links",
 869                                ret, __func__);
 870                        return ret;
 871                }
 872#endif
 873
 874                /* enable the system waking up via IPC IRQ */
 875                enable_irq_wake(pci->irq);
 876                pci_save_state(pci);
 877                return 0;
 878        }
 879
 880        /* stop hda controller and power dsp off */
 881        ret = hda_suspend(sdev, false);
 882        if (ret < 0) {
 883                dev_err(bus->dev, "error: suspending dsp\n");
 884                return ret;
 885        }
 886
 887        return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
 888}
 889
 890int hda_dsp_shutdown(struct snd_sof_dev *sdev)
 891{
 892        sdev->system_suspend_target = SOF_SUSPEND_S3;
 893        return snd_sof_suspend(sdev->dev);
 894}
 895
 896int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
 897{
 898#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 899        struct hdac_bus *bus = sof_to_bus(sdev);
 900        struct snd_soc_pcm_runtime *rtd;
 901        struct hdac_ext_stream *hext_stream;
 902        struct hdac_ext_link *link;
 903        struct hdac_stream *s;
 904        const char *name;
 905        int stream_tag;
 906
 907        /* set internal flag for BE */
 908        list_for_each_entry(s, &bus->stream_list, list) {
 909                hext_stream = stream_to_hdac_ext_stream(s);
 910
 911                /*
 912                 * clear stream. This should already be taken care for running
 913                 * streams when the SUSPEND trigger is called. But paused
 914                 * streams do not get suspended, so this needs to be done
 915                 * explicitly during suspend.
 916                 */
 917                if (hext_stream->link_substream) {
 918                        rtd = asoc_substream_to_rtd(hext_stream->link_substream);
 919                        name = asoc_rtd_to_codec(rtd, 0)->component->name;
 920                        link = snd_hdac_ext_bus_get_link(bus, name);
 921                        if (!link)
 922                                return -EINVAL;
 923
 924                        hext_stream->link_prepared = 0;
 925
 926                        if (hdac_stream(hext_stream)->direction ==
 927                                SNDRV_PCM_STREAM_CAPTURE)
 928                                continue;
 929
 930                        stream_tag = hdac_stream(hext_stream)->stream_tag;
 931                        snd_hdac_ext_link_clear_stream_id(link, stream_tag);
 932                }
 933        }
 934#endif
 935        return 0;
 936}
 937
 938void hda_dsp_d0i3_work(struct work_struct *work)
 939{
 940        struct sof_intel_hda_dev *hdev = container_of(work,
 941                                                      struct sof_intel_hda_dev,
 942                                                      d0i3_work.work);
 943        struct hdac_bus *bus = &hdev->hbus.core;
 944        struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev);
 945        struct sof_dsp_power_state target_state = {
 946                .state = SOF_DSP_PM_D0,
 947                .substate = SOF_HDA_DSP_PM_D0I3,
 948        };
 949        int ret;
 950
 951        /* DSP can enter D0I3 iff only D0I3-compatible streams are active */
 952        if (!snd_sof_dsp_only_d0i3_compatible_stream_active(sdev))
 953                /* remain in D0I0 */
 954                return;
 955
 956        /* This can fail but error cannot be propagated */
 957        ret = snd_sof_dsp_set_power_state(sdev, &target_state);
 958        if (ret < 0)
 959                dev_err_ratelimited(sdev->dev,
 960                                    "error: failed to set DSP state %d substate %d\n",
 961                                    target_state.state, target_state.substate);
 962}
 963
 964int hda_dsp_core_get(struct snd_sof_dev *sdev, int core)
 965{
 966        struct sof_ipc_pm_core_config pm_core_config = {
 967                .hdr = {
 968                        .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE,
 969                        .size = sizeof(pm_core_config),
 970                },
 971                .enable_mask = sdev->enabled_cores_mask | BIT(core),
 972        };
 973        int ret, ret1;
 974
 975        /* power up core */
 976        ret = hda_dsp_enable_core(sdev, BIT(core));
 977        if (ret < 0) {
 978                dev_err(sdev->dev, "failed to power up core %d with err: %d\n",
 979                        core, ret);
 980                return ret;
 981        }
 982
 983        /* No need to send IPC for primary core or if FW boot is not complete */
 984        if (sdev->fw_state != SOF_FW_BOOT_COMPLETE || core == SOF_DSP_PRIMARY_CORE)
 985                return 0;
 986
 987        /* Now notify DSP for secondary cores */
 988        ret = sof_ipc_tx_message(sdev->ipc, pm_core_config.hdr.cmd,
 989                                 &pm_core_config, sizeof(pm_core_config),
 990                                 &pm_core_config, sizeof(pm_core_config));
 991        if (ret < 0) {
 992                dev_err(sdev->dev, "failed to enable secondary core '%d' failed with %d\n",
 993                        core, ret);
 994                goto power_down;
 995        }
 996
 997        return ret;
 998
 999power_down:
1000        /* power down core if it is host managed and return the original error if this fails too */

1001        ret1 = hda_dsp_core_reset_power_down(sdev, BIT(core));
1002        if (ret1 < 0)
1003                dev_err(sdev->dev, "failed to power down core: %d with err: %d\n", core, ret1);
1004
1005        return ret;
1006}
1007