1
2
3
4
5
6
7
8
9
10
11
12
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/slab.h>
16#include <linux/mbus.h>
17#include <video/vga.h>
18#include <asm/irq.h>
19#include <asm/mach/pci.h>
20#include <plat/pcie.h>
21#include <plat/addr-map.h>
22#include "common.h"
23#include "orion5x.h"
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41#define PCIE_BASE (ORION5X_PCIE_VIRT_BASE)
42
43void __init orion5x_pcie_id(u32 *dev, u32 *rev)
44{
45 *dev = orion_pcie_dev_id(PCIE_BASE);
46 *rev = orion_pcie_rev(PCIE_BASE);
47}
48
49static int pcie_valid_config(int bus, int dev)
50{
51
52
53
54
55
56 if (bus == 0 && dev == 0)
57 return 1;
58
59 if (!orion_pcie_link_up(PCIE_BASE))
60 return 0;
61
62 if (bus == 0 && dev != 1)
63 return 0;
64
65 return 1;
66}
67
68
69
70
71
72
73
74static DEFINE_SPINLOCK(orion5x_pcie_lock);
75
76static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
77 int size, u32 *val)
78{
79 unsigned long flags;
80 int ret;
81
82 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
83 *val = 0xffffffff;
84 return PCIBIOS_DEVICE_NOT_FOUND;
85 }
86
87 spin_lock_irqsave(&orion5x_pcie_lock, flags);
88 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
89 spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
90
91 return ret;
92}
93
94static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
95 int where, int size, u32 *val)
96{
97 int ret;
98
99 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
100 *val = 0xffffffff;
101 return PCIBIOS_DEVICE_NOT_FOUND;
102 }
103
104
105
106
107
108
109 if (where >= 0x100) {
110 *val = 0xffffffff;
111 return PCIBIOS_DEVICE_NOT_FOUND;
112 }
113
114 ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
115 bus, devfn, where, size, val);
116
117 return ret;
118}
119
120static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
121 int where, int size, u32 val)
122{
123 unsigned long flags;
124 int ret;
125
126 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
127 return PCIBIOS_DEVICE_NOT_FOUND;
128
129 spin_lock_irqsave(&orion5x_pcie_lock, flags);
130 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
131 spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
132
133 return ret;
134}
135
136static struct pci_ops pcie_ops = {
137 .read = pcie_rd_conf,
138 .write = pcie_wr_conf,
139};
140
141
142static int __init pcie_setup(struct pci_sys_data *sys)
143{
144 struct resource *res;
145 struct resource realio;
146 int dev;
147
148
149
150
151 orion_pcie_setup(PCIE_BASE);
152
153
154
155
156
157 dev = orion_pcie_dev_id(PCIE_BASE);
158 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
159 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
160 "read transaction workaround\n");
161 mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
162 ORION_MBUS_PCIE_WA_ATTR,
163 ORION5X_PCIE_WA_PHYS_BASE,
164 ORION5X_PCIE_WA_SIZE);
165 pcie_ops.read = pcie_rd_conf_wa;
166 }
167
168 realio.start = sys->busnr * SZ_64K;
169 realio.end = realio.start + SZ_64K - 1;
170 pci_remap_iospace(&realio, ORION5X_PCIE_IO_PHYS_BASE);
171
172
173
174
175 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
176 if (!res)
177 panic("pcie_setup unable to alloc resources");
178
179
180
181
182 res->name = "PCIe Memory Space";
183 res->flags = IORESOURCE_MEM;
184 res->start = ORION5X_PCIE_MEM_PHYS_BASE;
185 res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
186 if (request_resource(&iomem_resource, res))
187 panic("Request PCIe Memory resource failed\n");
188 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
189
190 return 1;
191}
192
193
194
195
196#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x))
197#define PCI_MODE ORION5X_PCI_REG(0xd00)
198#define PCI_CMD ORION5X_PCI_REG(0xc00)
199#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
200#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
201#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
202
203
204
205
206#define PCI_MODE_64BIT (1 << 2)
207#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
208
209
210
211
212#define PCI_CMD_HOST_REORDER (1 << 29)
213
214
215
216
217#define PCI_P2P_BUS_OFFS 16
218#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
219#define PCI_P2P_DEV_OFFS 24
220#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
221
222
223
224
225#define PCI_CONF_REG(reg) ((reg) & 0xfc)
226#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
227#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
228#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
229#define PCI_CONF_ADDR_EN (1 << 31)
230
231
232
233
234#define PCI_CONF_FUNC_STAT_CMD 0
235#define PCI_CONF_REG_STAT_CMD 4
236#define PCIX_STAT 0x64
237#define PCIX_STAT_BUS_OFFS 8
238#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
239
240
241
242
243#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
244 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
245 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
246 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL)
247#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
248 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
249 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
250 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL)
251#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
252#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
253
254
255
256
257#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
258#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
259#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
260
261
262
263
264
265
266static DEFINE_SPINLOCK(orion5x_pci_lock);
267
268static int orion5x_pci_cardbus_mode;
269
270static int orion5x_pci_local_bus_nr(void)
271{
272 u32 conf = readl(PCI_P2P_CONF);
273 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
274}
275
276static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
277 u32 where, u32 size, u32 *val)
278{
279 unsigned long flags;
280 spin_lock_irqsave(&orion5x_pci_lock, flags);
281
282 writel(PCI_CONF_BUS(bus) |
283 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
284 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
285
286 *val = readl(PCI_CONF_DATA);
287
288 if (size == 1)
289 *val = (*val >> (8*(where & 0x3))) & 0xff;
290 else if (size == 2)
291 *val = (*val >> (8*(where & 0x3))) & 0xffff;
292
293 spin_unlock_irqrestore(&orion5x_pci_lock, flags);
294
295 return PCIBIOS_SUCCESSFUL;
296}
297
298static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
299 u32 where, u32 size, u32 val)
300{
301 unsigned long flags;
302 int ret = PCIBIOS_SUCCESSFUL;
303
304 spin_lock_irqsave(&orion5x_pci_lock, flags);
305
306 writel(PCI_CONF_BUS(bus) |
307 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
308 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
309
310 if (size == 4) {
311 __raw_writel(val, PCI_CONF_DATA);
312 } else if (size == 2) {
313 __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
314 } else if (size == 1) {
315 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
316 } else {
317 ret = PCIBIOS_BAD_REGISTER_NUMBER;
318 }
319
320 spin_unlock_irqrestore(&orion5x_pci_lock, flags);
321
322 return ret;
323}
324
325static int orion5x_pci_valid_config(int bus, u32 devfn)
326{
327 if (bus == orion5x_pci_local_bus_nr()) {
328
329
330
331 if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
332 return 0;
333
334
335
336
337
338 if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
339 return 0;
340 }
341
342 return 1;
343}
344
345static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
346 int where, int size, u32 *val)
347{
348 if (!orion5x_pci_valid_config(bus->number, devfn)) {
349 *val = 0xffffffff;
350 return PCIBIOS_DEVICE_NOT_FOUND;
351 }
352
353 return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
354 PCI_FUNC(devfn), where, size, val);
355}
356
357static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
358 int where, int size, u32 val)
359{
360 if (!orion5x_pci_valid_config(bus->number, devfn))
361 return PCIBIOS_DEVICE_NOT_FOUND;
362
363 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
364 PCI_FUNC(devfn), where, size, val);
365}
366
367static struct pci_ops pci_ops = {
368 .read = orion5x_pci_rd_conf,
369 .write = orion5x_pci_wr_conf,
370};
371
372static void __init orion5x_pci_set_bus_nr(int nr)
373{
374 u32 p2p = readl(PCI_P2P_CONF);
375
376 if (readl(PCI_MODE) & PCI_MODE_PCIX) {
377
378
379
380 u32 pcix_status, bus, dev;
381 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
382 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
383 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
384 pcix_status &= ~PCIX_STAT_BUS_MASK;
385 pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
386 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
387 } else {
388
389
390
391 p2p &= ~PCI_P2P_BUS_MASK;
392 p2p |= (nr << PCI_P2P_BUS_OFFS);
393 writel(p2p, PCI_P2P_CONF);
394 }
395}
396
397static void __init orion5x_pci_master_slave_enable(void)
398{
399 int bus_nr, func, reg;
400 u32 val;
401
402 bus_nr = orion5x_pci_local_bus_nr();
403 func = PCI_CONF_FUNC_STAT_CMD;
404 reg = PCI_CONF_REG_STAT_CMD;
405 orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
406 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
407 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
408}
409
410static void __init orion5x_setup_pci_wins(void)
411{
412 const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
413 u32 win_enable;
414 int bus;
415 int i;
416
417
418
419
420 win_enable = 0xffffffff;
421 writel(win_enable, PCI_BAR_ENABLE);
422
423
424
425
426 bus = orion5x_pci_local_bus_nr();
427
428 for (i = 0; i < dram->num_cs; i++) {
429 const struct mbus_dram_window *cs = dram->cs + i;
430 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
431 u32 reg;
432 u32 val;
433
434
435
436
437 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
438 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
439 val = (cs->base & 0xfffff000) | (val & 0xfff);
440 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
441
442
443
444
445 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
446 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
447 writel((cs->size - 1) & 0xfffff000,
448 PCI_BAR_SIZE_DDR_CS(cs->cs_index));
449 writel(cs->base & 0xfffff000,
450 PCI_BAR_REMAP_DDR_CS(cs->cs_index));
451
452
453
454
455 win_enable &= ~(1 << cs->cs_index);
456 }
457
458
459
460
461 writel(win_enable, PCI_BAR_ENABLE);
462
463
464
465
466 orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
467}
468
469static int __init pci_setup(struct pci_sys_data *sys)
470{
471 struct resource *res;
472 struct resource realio;
473
474
475
476
477 orion5x_setup_pci_wins();
478
479
480
481
482 orion5x_pci_master_slave_enable();
483
484
485
486
487 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
488
489 realio.start = sys->busnr * SZ_64K;
490 realio.end = realio.start + SZ_64K - 1;
491 pci_remap_iospace(&realio, ORION5X_PCI_IO_PHYS_BASE);
492
493
494
495
496 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
497 if (!res)
498 panic("pci_setup unable to alloc resources");
499
500
501
502
503 res->name = "PCI Memory Space";
504 res->flags = IORESOURCE_MEM;
505 res->start = ORION5X_PCI_MEM_PHYS_BASE;
506 res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
507 if (request_resource(&iomem_resource, res))
508 panic("Request PCI Memory resource failed\n");
509 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
510
511 return 1;
512}
513
514
515
516
517
518static void rc_pci_fixup(struct pci_dev *dev)
519{
520
521
522
523 if (dev->bus->parent == NULL && dev->devfn == 0) {
524 int i;
525
526 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
527 dev->resource[i].start = 0;
528 dev->resource[i].end = 0;
529 dev->resource[i].flags = 0;
530 }
531 }
532}
533DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
534
535static int orion5x_pci_disabled __initdata;
536
537void __init orion5x_pci_disable(void)
538{
539 orion5x_pci_disabled = 1;
540}
541
542void __init orion5x_pci_set_cardbus_mode(void)
543{
544 orion5x_pci_cardbus_mode = 1;
545}
546
547int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
548{
549 vga_base = ORION5X_PCIE_MEM_PHYS_BASE;
550
551 if (nr == 0) {
552 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
553 return pcie_setup(sys);
554 }
555
556 if (nr == 1 && !orion5x_pci_disabled) {
557 orion5x_pci_set_bus_nr(sys->busnr);
558 return pci_setup(sys);
559 }
560
561 return 0;
562}
563
564int __init orion5x_pci_sys_scan_bus(int nr, struct pci_host_bridge *bridge)
565{
566 struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
567
568 list_splice_init(&sys->resources, &bridge->windows);
569 bridge->dev.parent = NULL;
570 bridge->sysdata = sys;
571 bridge->busnr = sys->busnr;
572
573 if (nr == 0) {
574 bridge->ops = &pcie_ops;
575 return pci_scan_root_bus_bridge(bridge);
576 }
577
578 if (nr == 1 && !orion5x_pci_disabled) {
579 bridge->ops = &pci_ops;
580 return pci_scan_root_bus_bridge(bridge);
581 }
582
583 BUG();
584 return -ENODEV;
585}
586
587int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
588{
589 int bus = dev->bus->number;
590
591
592
593
594 if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
595 return IRQ_ORION5X_PCIE0_INT;
596
597 return -1;
598}
599