LXR linux/arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * IP30/Octane cpu-features overrides.
   4 *
   5 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
   6 *               2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
   7 *               2009 Johannes Dickgreber <tanzy@gmx.de>
   8 *               2015 Joshua Kinard <kumba@gentoo.org>
   9 *
  10 */
  11#ifndef __ASM_MACH_IP30_CPU_FEATURE_OVERRIDES_H
  12#define __ASM_MACH_IP30_CPU_FEATURE_OVERRIDES_H
  13
  14#include <asm/cpu.h>
  15
  16/*
  17 * IP30 only supports R1[024]000 processors, all using the same config
  18 */
  19#define cpu_has_tlb                     1
  20#define cpu_has_tlbinv                  0
  21#define cpu_has_segments                0
  22#define cpu_has_eva                     0
  23#define cpu_has_htw                     0
  24#define cpu_has_rixiex                  0
  25#define cpu_has_maar                    0
  26#define cpu_has_rw_llb                  0
  27#define cpu_has_3kex                    0
  28#define cpu_has_4kex                    1
  29#define cpu_has_3k_cache                0
  30#define cpu_has_4k_cache                1
  31#define cpu_has_nofpuex                 0
  32#define cpu_has_32fpr                   1
  33#define cpu_has_counter                 1
  34#define cpu_has_watch                   1
  35#define cpu_has_64bits                  1
  36#define cpu_has_divec                   0
  37#define cpu_has_vce                     0
  38#define cpu_has_cache_cdex_p            0
  39#define cpu_has_cache_cdex_s            0
  40#define cpu_has_prefetch                1
  41#define cpu_has_mcheck                  0
  42#define cpu_has_ejtag                   0
  43#define cpu_has_llsc                    1
  44#define cpu_has_mips16                  0
  45#define cpu_has_mdmx                    0
  46#define cpu_has_mips3d                  0
  47#define cpu_has_smartmips               0
  48#define cpu_has_rixi                    0
  49#define cpu_has_xpa                     0
  50#define cpu_has_vtag_icache             0
  51#define cpu_has_dc_aliases              0
  52#define cpu_has_ic_fills_f_dc           0
  53
  54#define cpu_icache_snoops_remote_store  1
  55
  56#define cpu_has_mips32r1                0
  57#define cpu_has_mips32r2                0
  58#define cpu_has_mips64r1                0
  59#define cpu_has_mips64r2                0
  60#define cpu_has_mips32r6                0
  61#define cpu_has_mips64r6                0
  62
  63#define cpu_has_dsp                     0
  64#define cpu_has_dsp2                    0
  65#define cpu_has_mipsmt                  0
  66#define cpu_has_userlocal               0
  67#define cpu_has_inclusive_pcaches       1
  68#define cpu_has_perf_cntr_intr_bit      0
  69#define cpu_has_vz                      0
  70#define cpu_has_fre                     0
  71#define cpu_has_cdmm                    0
  72
  73#define cpu_dcache_line_size()          32
  74#define cpu_icache_line_size()          64
  75#define cpu_scache_line_size()          128
  76
  77#endif /* __ASM_MACH_IP30_CPU_FEATURE_OVERRIDES_H */
  78
  79