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6
7#include <linux/slab.h>
8#include <linux/perf_event.h>
9#include <asm/cpu_mf.h>
10
11
12
13
14CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000);
15CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001);
16CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002);
17CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003);
18CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020);
19CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
20CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
21CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
22CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
23CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
24CPUMF_EVENT_ATTR(cf_fvn1, L1D_DIR_WRITES, 0x0004);
25CPUMF_EVENT_ATTR(cf_fvn1, L1D_PENALTY_CYCLES, 0x0005);
26CPUMF_EVENT_ATTR(cf_fvn3, CPU_CYCLES, 0x0000);
27CPUMF_EVENT_ATTR(cf_fvn3, INSTRUCTIONS, 0x0001);
28CPUMF_EVENT_ATTR(cf_fvn3, L1I_DIR_WRITES, 0x0002);
29CPUMF_EVENT_ATTR(cf_fvn3, L1I_PENALTY_CYCLES, 0x0003);
30CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES, 0x0020);
31CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
32CPUMF_EVENT_ATTR(cf_fvn3, L1D_DIR_WRITES, 0x0004);
33CPUMF_EVENT_ATTR(cf_fvn3, L1D_PENALTY_CYCLES, 0x0005);
34CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_FUNCTIONS, 0x0040);
35CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_CYCLES, 0x0041);
36CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS, 0x0042);
37CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_CYCLES, 0x0043);
38CPUMF_EVENT_ATTR(cf_svn_12345, SHA_FUNCTIONS, 0x0044);
39CPUMF_EVENT_ATTR(cf_svn_12345, SHA_CYCLES, 0x0045);
40CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS, 0x0046);
41CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_CYCLES, 0x0047);
42CPUMF_EVENT_ATTR(cf_svn_12345, DEA_FUNCTIONS, 0x0048);
43CPUMF_EVENT_ATTR(cf_svn_12345, DEA_CYCLES, 0x0049);
44CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS, 0x004a);
45CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_CYCLES, 0x004b);
46CPUMF_EVENT_ATTR(cf_svn_12345, AES_FUNCTIONS, 0x004c);
47CPUMF_EVENT_ATTR(cf_svn_12345, AES_CYCLES, 0x004d);
48CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS, 0x004e);
49CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_CYCLES, 0x004f);
50CPUMF_EVENT_ATTR(cf_svn_6, ECC_FUNCTION_COUNT, 0x0050);
51CPUMF_EVENT_ATTR(cf_svn_6, ECC_CYCLES_COUNT, 0x0051);
52CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT, 0x0052);
53CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT, 0x0053);
54CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080);
55CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081);
56CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082);
57CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083);
58CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084);
59CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085);
60CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086);
61CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087);
62CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088);
63CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089);
64CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a);
65CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b);
66CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c);
67CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d);
68CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
69CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091);
70CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092);
71CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093);
72CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080);
73CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081);
74CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082);
75CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083);
76CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085);
77CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086);
78CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087);
79CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088);
80CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089);
81CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a);
82CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b);
83CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c);
84CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d);
85CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e);
86CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f);
87CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090);
88CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091);
89CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092);
90CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093);
91CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094);
92CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096);
93CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098);
94CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
95CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b);
96CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080);
97CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081);
98CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082);
99CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083);
100CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084);
101CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085);
102CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087);
103CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089);
104CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a);
105CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b);
106CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c);
107CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d);
108CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
109CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f);
110CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
111CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091);
112CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092);
113CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093);
114CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094);
115CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095);
116CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096);
117CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097);
118CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098);
119CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
120CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a);
121CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b);
122CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c);
123CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d);
124CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e);
125CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f);
126CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0);
127CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1);
128CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1);
129CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2);
130CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3);
131CPUMF_EVENT_ATTR(cf_z13, L1D_RO_EXCL_WRITES, 0x0080);
132CPUMF_EVENT_ATTR(cf_z13, DTLB1_WRITES, 0x0081);
133CPUMF_EVENT_ATTR(cf_z13, DTLB1_MISSES, 0x0082);
134CPUMF_EVENT_ATTR(cf_z13, DTLB1_HPAGE_WRITES, 0x0083);
135CPUMF_EVENT_ATTR(cf_z13, DTLB1_GPAGE_WRITES, 0x0084);
136CPUMF_EVENT_ATTR(cf_z13, L1D_L2D_SOURCED_WRITES, 0x0085);
137CPUMF_EVENT_ATTR(cf_z13, ITLB1_WRITES, 0x0086);
138CPUMF_EVENT_ATTR(cf_z13, ITLB1_MISSES, 0x0087);
139CPUMF_EVENT_ATTR(cf_z13, L1I_L2I_SOURCED_WRITES, 0x0088);
140CPUMF_EVENT_ATTR(cf_z13, TLB2_PTE_WRITES, 0x0089);
141CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES, 0x008a);
142CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_WRITES, 0x008b);
143CPUMF_EVENT_ATTR(cf_z13, TX_C_TEND, 0x008c);
144CPUMF_EVENT_ATTR(cf_z13, TX_NC_TEND, 0x008d);
145CPUMF_EVENT_ATTR(cf_z13, L1C_TLB1_MISSES, 0x008f);
146CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
147CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0091);
148CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES, 0x0092);
149CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV, 0x0093);
150CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES, 0x0094);
151CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x0095);
152CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV, 0x0096);
153CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES, 0x0097);
154CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x0098);
155CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x0099);
156CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x009a);
157CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x009b);
158CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x009c);
159CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x009d);
160CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES, 0x009e);
161CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES, 0x009f);
162CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES, 0x00a0);
163CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES, 0x00a1);
164CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
165CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a3);
166CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES, 0x00a4);
167CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV, 0x00a5);
168CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES, 0x00a6);
169CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00a7);
170CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV, 0x00a8);
171CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES, 0x00a9);
172CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x00aa);
173CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x00ab);
174CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x00ac);
175CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x00ad);
176CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x00ae);
177CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x00af);
178CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES, 0x00b0);
179CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES, 0x00b1);
180CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES, 0x00b2);
181CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES, 0x00b3);
182CPUMF_EVENT_ATTR(cf_z13, TX_NC_TABORT, 0x00da);
183CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db);
184CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc);
185CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
186CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
187CPUMF_EVENT_ATTR(cf_z14, L1D_RO_EXCL_WRITES, 0x0080);
188CPUMF_EVENT_ATTR(cf_z14, DTLB2_WRITES, 0x0081);
189CPUMF_EVENT_ATTR(cf_z14, DTLB2_MISSES, 0x0082);
190CPUMF_EVENT_ATTR(cf_z14, DTLB2_HPAGE_WRITES, 0x0083);
191CPUMF_EVENT_ATTR(cf_z14, DTLB2_GPAGE_WRITES, 0x0084);
192CPUMF_EVENT_ATTR(cf_z14, L1D_L2D_SOURCED_WRITES, 0x0085);
193CPUMF_EVENT_ATTR(cf_z14, ITLB2_WRITES, 0x0086);
194CPUMF_EVENT_ATTR(cf_z14, ITLB2_MISSES, 0x0087);
195CPUMF_EVENT_ATTR(cf_z14, L1I_L2I_SOURCED_WRITES, 0x0088);
196CPUMF_EVENT_ATTR(cf_z14, TLB2_PTE_WRITES, 0x0089);
197CPUMF_EVENT_ATTR(cf_z14, TLB2_CRSTE_WRITES, 0x008a);
198CPUMF_EVENT_ATTR(cf_z14, TLB2_ENGINES_BUSY, 0x008b);
199CPUMF_EVENT_ATTR(cf_z14, TX_C_TEND, 0x008c);
200CPUMF_EVENT_ATTR(cf_z14, TX_NC_TEND, 0x008d);
201CPUMF_EVENT_ATTR(cf_z14, L1C_TLB2_MISSES, 0x008f);
202CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
203CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
204CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
205CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
206CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
207CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
208CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
209CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
210CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
211CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
212CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
213CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
214CPUMF_EVENT_ATTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
215CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
216CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
217CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
218CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
219CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
220CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
221CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
222CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
223CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
224CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
225CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
226CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
227CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
228CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
229CPUMF_EVENT_ATTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
230CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
231CPUMF_EVENT_ATTR(cf_z14, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
232CPUMF_EVENT_ATTR(cf_z14, VX_BCD_EXECUTION_SLOTS, 0x00e1);
233CPUMF_EVENT_ATTR(cf_z14, DECIMAL_INSTRUCTIONS, 0x00e2);
234CPUMF_EVENT_ATTR(cf_z14, LAST_HOST_TRANSLATIONS, 0x00e8);
235CPUMF_EVENT_ATTR(cf_z14, TX_NC_TABORT, 0x00f3);
236CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4);
237CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
238CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
239CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
240
241CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080);
242CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081);
243CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082);
244CPUMF_EVENT_ATTR(cf_z15, DTLB2_HPAGE_WRITES, 0x0083);
245CPUMF_EVENT_ATTR(cf_z15, DTLB2_GPAGE_WRITES, 0x0084);
246CPUMF_EVENT_ATTR(cf_z15, L1D_L2D_SOURCED_WRITES, 0x0085);
247CPUMF_EVENT_ATTR(cf_z15, ITLB2_WRITES, 0x0086);
248CPUMF_EVENT_ATTR(cf_z15, ITLB2_MISSES, 0x0087);
249CPUMF_EVENT_ATTR(cf_z15, L1I_L2I_SOURCED_WRITES, 0x0088);
250CPUMF_EVENT_ATTR(cf_z15, TLB2_PTE_WRITES, 0x0089);
251CPUMF_EVENT_ATTR(cf_z15, TLB2_CRSTE_WRITES, 0x008a);
252CPUMF_EVENT_ATTR(cf_z15, TLB2_ENGINES_BUSY, 0x008b);
253CPUMF_EVENT_ATTR(cf_z15, TX_C_TEND, 0x008c);
254CPUMF_EVENT_ATTR(cf_z15, TX_NC_TEND, 0x008d);
255CPUMF_EVENT_ATTR(cf_z15, L1C_TLB2_MISSES, 0x008f);
256CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
257CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
258CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
259CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
260CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
261CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
262CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
263CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
264CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
265CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
266CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
267CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
268CPUMF_EVENT_ATTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
269CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
270CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
271CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
272CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
273CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
274CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
275CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
276CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
277CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
278CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
279CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
280CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
281CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
282CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
283CPUMF_EVENT_ATTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
284CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
285CPUMF_EVENT_ATTR(cf_z15, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
286CPUMF_EVENT_ATTR(cf_z15, VX_BCD_EXECUTION_SLOTS, 0x00e1);
287CPUMF_EVENT_ATTR(cf_z15, DECIMAL_INSTRUCTIONS, 0x00e2);
288CPUMF_EVENT_ATTR(cf_z15, LAST_HOST_TRANSLATIONS, 0x00e8);
289CPUMF_EVENT_ATTR(cf_z15, TX_NC_TABORT, 0x00f3);
290CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_NO_SPECIAL, 0x00f4);
291CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_SPECIAL, 0x00f5);
292CPUMF_EVENT_ATTR(cf_z15, DFLT_ACCESS, 0x00f7);
293CPUMF_EVENT_ATTR(cf_z15, DFLT_CYCLES, 0x00fc);
294CPUMF_EVENT_ATTR(cf_z15, DFLT_CC, 0x00108);
295CPUMF_EVENT_ATTR(cf_z15, DFLT_CCFINISH, 0x00109);
296CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
297CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
298CPUMF_EVENT_ATTR(cf_z16, L1D_RO_EXCL_WRITES, 0x0080);
299CPUMF_EVENT_ATTR(cf_z16, DTLB2_WRITES, 0x0081);
300CPUMF_EVENT_ATTR(cf_z16, DTLB2_MISSES, 0x0082);
301CPUMF_EVENT_ATTR(cf_z16, CRSTE_1MB_WRITES, 0x0083);
302CPUMF_EVENT_ATTR(cf_z16, DTLB2_GPAGE_WRITES, 0x0084);
303CPUMF_EVENT_ATTR(cf_z16, ITLB2_WRITES, 0x0086);
304CPUMF_EVENT_ATTR(cf_z16, ITLB2_MISSES, 0x0087);
305CPUMF_EVENT_ATTR(cf_z16, TLB2_PTE_WRITES, 0x0089);
306CPUMF_EVENT_ATTR(cf_z16, TLB2_CRSTE_WRITES, 0x008a);
307CPUMF_EVENT_ATTR(cf_z16, TLB2_ENGINES_BUSY, 0x008b);
308CPUMF_EVENT_ATTR(cf_z16, TX_C_TEND, 0x008c);
309CPUMF_EVENT_ATTR(cf_z16, TX_NC_TEND, 0x008d);
310CPUMF_EVENT_ATTR(cf_z16, L1C_TLB2_MISSES, 0x008f);
311CPUMF_EVENT_ATTR(cf_z16, DCW_REQ, 0x0091);
312CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_IV, 0x0092);
313CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_CHIP_HIT, 0x0093);
314CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_DRAWER_HIT, 0x0094);
315CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP, 0x0095);
316CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_IV, 0x0096);
317CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_CHIP_HIT, 0x0097);
318CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_DRAWER_HIT, 0x0098);
319CPUMF_EVENT_ATTR(cf_z16, DCW_ON_MODULE, 0x0099);
320CPUMF_EVENT_ATTR(cf_z16, DCW_ON_DRAWER, 0x009a);
321CPUMF_EVENT_ATTR(cf_z16, DCW_OFF_DRAWER, 0x009b);
322CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_MEMORY, 0x009c);
323CPUMF_EVENT_ATTR(cf_z16, DCW_ON_MODULE_MEMORY, 0x009d);
324CPUMF_EVENT_ATTR(cf_z16, DCW_ON_DRAWER_MEMORY, 0x009e);
325CPUMF_EVENT_ATTR(cf_z16, DCW_OFF_DRAWER_MEMORY, 0x009f);
326CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_IV, 0x00a0);
327CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_CHIP_HIT, 0x00a1);
328CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_DRAWER_HIT, 0x00a2);
329CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_IV, 0x00a3);
330CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_CHIP_HIT, 0x00a4);
331CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_DRAWER_HIT, 0x00a5);
332CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_IV, 0x00a6);
333CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_CHIP_HIT, 0x00a7);
334CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_DRAWER_HIT, 0x00a8);
335CPUMF_EVENT_ATTR(cf_z16, ICW_REQ, 0x00a9);
336CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_IV, 0x00aa);
337CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_CHIP_HIT, 0x00ab);
338CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_DRAWER_HIT, 0x00ac);
339CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP, 0x00ad);
340CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_IV, 0x00ae);
341CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_CHIP_HIT, 0x00af);
342CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_DRAWER_HIT, 0x00b0);
343CPUMF_EVENT_ATTR(cf_z16, ICW_ON_MODULE, 0x00b1);
344CPUMF_EVENT_ATTR(cf_z16, ICW_ON_DRAWER, 0x00b2);
345CPUMF_EVENT_ATTR(cf_z16, ICW_OFF_DRAWER, 0x00b3);
346CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_MEMORY, 0x00b4);
347CPUMF_EVENT_ATTR(cf_z16, ICW_ON_MODULE_MEMORY, 0x00b5);
348CPUMF_EVENT_ATTR(cf_z16, ICW_ON_DRAWER_MEMORY, 0x00b6);
349CPUMF_EVENT_ATTR(cf_z16, ICW_OFF_DRAWER_MEMORY, 0x00b7);
350CPUMF_EVENT_ATTR(cf_z16, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
351CPUMF_EVENT_ATTR(cf_z16, VX_BCD_EXECUTION_SLOTS, 0x00e1);
352CPUMF_EVENT_ATTR(cf_z16, DECIMAL_INSTRUCTIONS, 0x00e2);
353CPUMF_EVENT_ATTR(cf_z16, LAST_HOST_TRANSLATIONS, 0x00e8);
354CPUMF_EVENT_ATTR(cf_z16, TX_NC_TABORT, 0x00f4);
355CPUMF_EVENT_ATTR(cf_z16, TX_C_TABORT_NO_SPECIAL, 0x00f5);
356CPUMF_EVENT_ATTR(cf_z16, TX_C_TABORT_SPECIAL, 0x00f6);
357CPUMF_EVENT_ATTR(cf_z16, DFLT_ACCESS, 0x00f8);
358CPUMF_EVENT_ATTR(cf_z16, DFLT_CYCLES, 0x00fd);
359CPUMF_EVENT_ATTR(cf_z16, SORTL, 0x0100);
360CPUMF_EVENT_ATTR(cf_z16, DFLT_CC, 0x0109);
361CPUMF_EVENT_ATTR(cf_z16, DFLT_CCFINISH, 0x010a);
362CPUMF_EVENT_ATTR(cf_z16, NNPA_INVOCATIONS, 0x010b);
363CPUMF_EVENT_ATTR(cf_z16, NNPA_COMPLETIONS, 0x010c);
364CPUMF_EVENT_ATTR(cf_z16, NNPA_WAIT_LOCK, 0x010d);
365CPUMF_EVENT_ATTR(cf_z16, NNPA_HOLD_LOCK, 0x010e);
366CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
367CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
368
369static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
370 CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
371 CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
372 CPUMF_EVENT_PTR(cf_fvn1, L1I_DIR_WRITES),
373 CPUMF_EVENT_PTR(cf_fvn1, L1I_PENALTY_CYCLES),
374 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES),
375 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS),
376 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES),
377 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES),
378 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES),
379 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES),
380 CPUMF_EVENT_PTR(cf_fvn1, L1D_DIR_WRITES),
381 CPUMF_EVENT_PTR(cf_fvn1, L1D_PENALTY_CYCLES),
382 NULL,
383};
384
385static struct attribute *cpumcf_fvn3_pmu_event_attr[] __initdata = {
386 CPUMF_EVENT_PTR(cf_fvn3, CPU_CYCLES),
387 CPUMF_EVENT_PTR(cf_fvn3, INSTRUCTIONS),
388 CPUMF_EVENT_PTR(cf_fvn3, L1I_DIR_WRITES),
389 CPUMF_EVENT_PTR(cf_fvn3, L1I_PENALTY_CYCLES),
390 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES),
391 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS),
392 CPUMF_EVENT_PTR(cf_fvn3, L1D_DIR_WRITES),
393 CPUMF_EVENT_PTR(cf_fvn3, L1D_PENALTY_CYCLES),
394 NULL,
395};
396
397static struct attribute *cpumcf_svn_12345_pmu_event_attr[] __initdata = {
398 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
399 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
400 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
401 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES),
402 CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS),
403 CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES),
404 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS),
405 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES),
406 CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS),
407 CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES),
408 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS),
409 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES),
410 CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS),
411 CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES),
412 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS),
413 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES),
414 NULL,
415};
416
417static struct attribute *cpumcf_svn_67_pmu_event_attr[] __initdata = {
418 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
419 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
420 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
421 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES),
422 CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS),
423 CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES),
424 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS),
425 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES),
426 CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS),
427 CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES),
428 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS),
429 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES),
430 CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS),
431 CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES),
432 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS),
433 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES),
434 CPUMF_EVENT_PTR(cf_svn_6, ECC_FUNCTION_COUNT),
435 CPUMF_EVENT_PTR(cf_svn_6, ECC_CYCLES_COUNT),
436 CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT),
437 CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT),
438 NULL,
439};
440
441static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = {
442 CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES),
443 CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES),
444 CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES),
445 CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES),
446 CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES),
447 CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES),
448 CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES),
449 CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES),
450 CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES),
451 CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES),
452 CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES),
453 CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES),
454 CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES),
455 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES),
456 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES),
457 CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES),
458 CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES),
459 CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT),
460 NULL,
461};
462
463static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = {
464 CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES),
465 CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES),
466 CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES),
467 CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES),
468 CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT),
469 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES),
470 CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES),
471 CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES),
472 CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES),
473 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES),
474 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES),
475 CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES),
476 CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES),
477 CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES),
478 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES),
479 CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES),
480 CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES),
481 CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES),
482 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES),
483 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES),
484 CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES),
485 CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES),
486 CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES),
487 CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES),
488 NULL,
489};
490
491static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = {
492 CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES),
493 CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES),
494 CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES),
495 CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES),
496 CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES),
497 CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES),
498 CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES),
499 CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES),
500 CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES),
501 CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES),
502 CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES),
503 CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES),
504 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES),
505 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES),
506 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES),
507 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES),
508 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES),
509 CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES),
510 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES),
511 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND),
512 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
513 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV),
514 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV),
515 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES),
516 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES),
517 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES),
518 CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES),
519 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES),
520 CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND),
521 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
522 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV),
523 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV),
524 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT),
525 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL),
526 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL),
527 NULL,
528};
529
530static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = {
531 CPUMF_EVENT_PTR(cf_z13, L1D_RO_EXCL_WRITES),
532 CPUMF_EVENT_PTR(cf_z13, DTLB1_WRITES),
533 CPUMF_EVENT_PTR(cf_z13, DTLB1_MISSES),
534 CPUMF_EVENT_PTR(cf_z13, DTLB1_HPAGE_WRITES),
535 CPUMF_EVENT_PTR(cf_z13, DTLB1_GPAGE_WRITES),
536 CPUMF_EVENT_PTR(cf_z13, L1D_L2D_SOURCED_WRITES),
537 CPUMF_EVENT_PTR(cf_z13, ITLB1_WRITES),
538 CPUMF_EVENT_PTR(cf_z13, ITLB1_MISSES),
539 CPUMF_EVENT_PTR(cf_z13, L1I_L2I_SOURCED_WRITES),
540 CPUMF_EVENT_PTR(cf_z13, TLB2_PTE_WRITES),
541 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES),
542 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_WRITES),
543 CPUMF_EVENT_PTR(cf_z13, TX_C_TEND),
544 CPUMF_EVENT_PTR(cf_z13, TX_NC_TEND),
545 CPUMF_EVENT_PTR(cf_z13, L1C_TLB1_MISSES),
546 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES),
547 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
548 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES),
549 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV),
550 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES),
551 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES),
552 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV),
553 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES),
554 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
555 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
556 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
557 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
558 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
559 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
560 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES),
561 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES),
562 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES),
563 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES),
564 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES),
565 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
566 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES),
567 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV),
568 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES),
569 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES),
570 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV),
571 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES),
572 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
573 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
574 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
575 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
576 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
577 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
578 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES),
579 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES),
580 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES),
581 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES),
582 CPUMF_EVENT_PTR(cf_z13, TX_NC_TABORT),
583 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_NO_SPECIAL),
584 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_SPECIAL),
585 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
586 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
587 NULL,
588};
589
590static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = {
591 CPUMF_EVENT_PTR(cf_z14, L1D_RO_EXCL_WRITES),
592 CPUMF_EVENT_PTR(cf_z14, DTLB2_WRITES),
593 CPUMF_EVENT_PTR(cf_z14, DTLB2_MISSES),
594 CPUMF_EVENT_PTR(cf_z14, DTLB2_HPAGE_WRITES),
595 CPUMF_EVENT_PTR(cf_z14, DTLB2_GPAGE_WRITES),
596 CPUMF_EVENT_PTR(cf_z14, L1D_L2D_SOURCED_WRITES),
597 CPUMF_EVENT_PTR(cf_z14, ITLB2_WRITES),
598 CPUMF_EVENT_PTR(cf_z14, ITLB2_MISSES),
599 CPUMF_EVENT_PTR(cf_z14, L1I_L2I_SOURCED_WRITES),
600 CPUMF_EVENT_PTR(cf_z14, TLB2_PTE_WRITES),
601 CPUMF_EVENT_PTR(cf_z14, TLB2_CRSTE_WRITES),
602 CPUMF_EVENT_PTR(cf_z14, TLB2_ENGINES_BUSY),
603 CPUMF_EVENT_PTR(cf_z14, TX_C_TEND),
604 CPUMF_EVENT_PTR(cf_z14, TX_NC_TEND),
605 CPUMF_EVENT_PTR(cf_z14, L1C_TLB2_MISSES),
606 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES),
607 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
608 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
609 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES),
610 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
611 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
612 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
613 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
614 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
615 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES),
616 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
617 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
618 CPUMF_EVENT_PTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES),
619 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES),
620 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
621 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES),
622 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
623 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
624 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES),
625 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
626 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
627 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
628 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
629 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
630 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES),
631 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
632 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
633 CPUMF_EVENT_PTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES),
634 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES),
635 CPUMF_EVENT_PTR(cf_z14, BCD_DFP_EXECUTION_SLOTS),
636 CPUMF_EVENT_PTR(cf_z14, VX_BCD_EXECUTION_SLOTS),
637 CPUMF_EVENT_PTR(cf_z14, DECIMAL_INSTRUCTIONS),
638 CPUMF_EVENT_PTR(cf_z14, LAST_HOST_TRANSLATIONS),
639 CPUMF_EVENT_PTR(cf_z14, TX_NC_TABORT),
640 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_NO_SPECIAL),
641 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_SPECIAL),
642 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
643 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
644 NULL,
645};
646
647static struct attribute *cpumcf_z15_pmu_event_attr[] __initdata = {
648 CPUMF_EVENT_PTR(cf_z15, L1D_RO_EXCL_WRITES),
649 CPUMF_EVENT_PTR(cf_z15, DTLB2_WRITES),
650 CPUMF_EVENT_PTR(cf_z15, DTLB2_MISSES),
651 CPUMF_EVENT_PTR(cf_z15, DTLB2_HPAGE_WRITES),
652 CPUMF_EVENT_PTR(cf_z15, DTLB2_GPAGE_WRITES),
653 CPUMF_EVENT_PTR(cf_z15, L1D_L2D_SOURCED_WRITES),
654 CPUMF_EVENT_PTR(cf_z15, ITLB2_WRITES),
655 CPUMF_EVENT_PTR(cf_z15, ITLB2_MISSES),
656 CPUMF_EVENT_PTR(cf_z15, L1I_L2I_SOURCED_WRITES),
657 CPUMF_EVENT_PTR(cf_z15, TLB2_PTE_WRITES),
658 CPUMF_EVENT_PTR(cf_z15, TLB2_CRSTE_WRITES),
659 CPUMF_EVENT_PTR(cf_z15, TLB2_ENGINES_BUSY),
660 CPUMF_EVENT_PTR(cf_z15, TX_C_TEND),
661 CPUMF_EVENT_PTR(cf_z15, TX_NC_TEND),
662 CPUMF_EVENT_PTR(cf_z15, L1C_TLB2_MISSES),
663 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES),
664 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
665 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
666 CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES),
667 CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
668 CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
669 CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
670 CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
671 CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
672 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES),
673 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
674 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
675 CPUMF_EVENT_PTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES),
676 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES),
677 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
678 CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES),
679 CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
680 CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
681 CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES),
682 CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
683 CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
684 CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
685 CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
686 CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
687 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES),
688 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
689 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
690 CPUMF_EVENT_PTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES),
691 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES),
692 CPUMF_EVENT_PTR(cf_z15, BCD_DFP_EXECUTION_SLOTS),
693 CPUMF_EVENT_PTR(cf_z15, VX_BCD_EXECUTION_SLOTS),
694 CPUMF_EVENT_PTR(cf_z15, DECIMAL_INSTRUCTIONS),
695 CPUMF_EVENT_PTR(cf_z15, LAST_HOST_TRANSLATIONS),
696 CPUMF_EVENT_PTR(cf_z15, TX_NC_TABORT),
697 CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_NO_SPECIAL),
698 CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_SPECIAL),
699 CPUMF_EVENT_PTR(cf_z15, DFLT_ACCESS),
700 CPUMF_EVENT_PTR(cf_z15, DFLT_CYCLES),
701 CPUMF_EVENT_PTR(cf_z15, DFLT_CC),
702 CPUMF_EVENT_PTR(cf_z15, DFLT_CCFINISH),
703 CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
704 CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
705 NULL,
706};
707
708static struct attribute *cpumcf_z16_pmu_event_attr[] __initdata = {
709 CPUMF_EVENT_PTR(cf_z16, L1D_RO_EXCL_WRITES),
710 CPUMF_EVENT_PTR(cf_z16, DTLB2_WRITES),
711 CPUMF_EVENT_PTR(cf_z16, DTLB2_MISSES),
712 CPUMF_EVENT_PTR(cf_z16, CRSTE_1MB_WRITES),
713 CPUMF_EVENT_PTR(cf_z16, DTLB2_GPAGE_WRITES),
714 CPUMF_EVENT_PTR(cf_z16, ITLB2_WRITES),
715 CPUMF_EVENT_PTR(cf_z16, ITLB2_MISSES),
716 CPUMF_EVENT_PTR(cf_z16, TLB2_PTE_WRITES),
717 CPUMF_EVENT_PTR(cf_z16, TLB2_CRSTE_WRITES),
718 CPUMF_EVENT_PTR(cf_z16, TLB2_ENGINES_BUSY),
719 CPUMF_EVENT_PTR(cf_z16, TX_C_TEND),
720 CPUMF_EVENT_PTR(cf_z16, TX_NC_TEND),
721 CPUMF_EVENT_PTR(cf_z16, L1C_TLB2_MISSES),
722 CPUMF_EVENT_PTR(cf_z16, DCW_REQ),
723 CPUMF_EVENT_PTR(cf_z16, DCW_REQ_IV),
724 CPUMF_EVENT_PTR(cf_z16, DCW_REQ_CHIP_HIT),
725 CPUMF_EVENT_PTR(cf_z16, DCW_REQ_DRAWER_HIT),
726 CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP),
727 CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_IV),
728 CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_CHIP_HIT),
729 CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_DRAWER_HIT),
730 CPUMF_EVENT_PTR(cf_z16, DCW_ON_MODULE),
731 CPUMF_EVENT_PTR(cf_z16, DCW_ON_DRAWER),
732 CPUMF_EVENT_PTR(cf_z16, DCW_OFF_DRAWER),
733 CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_MEMORY),
734 CPUMF_EVENT_PTR(cf_z16, DCW_ON_MODULE_MEMORY),
735 CPUMF_EVENT_PTR(cf_z16, DCW_ON_DRAWER_MEMORY),
736 CPUMF_EVENT_PTR(cf_z16, DCW_OFF_DRAWER_MEMORY),
737 CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_IV),
738 CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_CHIP_HIT),
739 CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_DRAWER_HIT),
740 CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_IV),
741 CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_CHIP_HIT),
742 CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_DRAWER_HIT),
743 CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_IV),
744 CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_CHIP_HIT),
745 CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_DRAWER_HIT),
746 CPUMF_EVENT_PTR(cf_z16, ICW_REQ),
747 CPUMF_EVENT_PTR(cf_z16, ICW_REQ_IV),
748 CPUMF_EVENT_PTR(cf_z16, ICW_REQ_CHIP_HIT),
749 CPUMF_EVENT_PTR(cf_z16, ICW_REQ_DRAWER_HIT),
750 CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP),
751 CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_IV),
752 CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_CHIP_HIT),
753 CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_DRAWER_HIT),
754 CPUMF_EVENT_PTR(cf_z16, ICW_ON_MODULE),
755 CPUMF_EVENT_PTR(cf_z16, ICW_ON_DRAWER),
756 CPUMF_EVENT_PTR(cf_z16, ICW_OFF_DRAWER),
757 CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_MEMORY),
758 CPUMF_EVENT_PTR(cf_z16, ICW_ON_MODULE_MEMORY),
759 CPUMF_EVENT_PTR(cf_z16, ICW_ON_DRAWER_MEMORY),
760 CPUMF_EVENT_PTR(cf_z16, ICW_OFF_DRAWER_MEMORY),
761 CPUMF_EVENT_PTR(cf_z16, BCD_DFP_EXECUTION_SLOTS),
762 CPUMF_EVENT_PTR(cf_z16, VX_BCD_EXECUTION_SLOTS),
763 CPUMF_EVENT_PTR(cf_z16, DECIMAL_INSTRUCTIONS),
764 CPUMF_EVENT_PTR(cf_z16, LAST_HOST_TRANSLATIONS),
765 CPUMF_EVENT_PTR(cf_z16, TX_NC_TABORT),
766 CPUMF_EVENT_PTR(cf_z16, TX_C_TABORT_NO_SPECIAL),
767 CPUMF_EVENT_PTR(cf_z16, TX_C_TABORT_SPECIAL),
768 CPUMF_EVENT_PTR(cf_z16, DFLT_ACCESS),
769 CPUMF_EVENT_PTR(cf_z16, DFLT_CYCLES),
770 CPUMF_EVENT_PTR(cf_z16, SORTL),
771 CPUMF_EVENT_PTR(cf_z16, DFLT_CC),
772 CPUMF_EVENT_PTR(cf_z16, DFLT_CCFINISH),
773 CPUMF_EVENT_PTR(cf_z16, NNPA_INVOCATIONS),
774 CPUMF_EVENT_PTR(cf_z16, NNPA_COMPLETIONS),
775 CPUMF_EVENT_PTR(cf_z16, NNPA_WAIT_LOCK),
776 CPUMF_EVENT_PTR(cf_z16, NNPA_HOLD_LOCK),
777 CPUMF_EVENT_PTR(cf_z16, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
778 CPUMF_EVENT_PTR(cf_z16, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
779 NULL,
780};
781
782
783
784static struct attribute_group cpumcf_pmu_events_group = {
785 .name = "events",
786};
787
788PMU_FORMAT_ATTR(event, "config:0-63");
789
790static struct attribute *cpumcf_pmu_format_attr[] = {
791 &format_attr_event.attr,
792 NULL,
793};
794
795static struct attribute_group cpumcf_pmu_format_group = {
796 .name = "format",
797 .attrs = cpumcf_pmu_format_attr,
798};
799
800static const struct attribute_group *cpumcf_pmu_attr_groups[] = {
801 &cpumcf_pmu_events_group,
802 &cpumcf_pmu_format_group,
803 NULL,
804};
805
806
807static __init struct attribute **merge_attr(struct attribute **a,
808 struct attribute **b,
809 struct attribute **c)
810{
811 struct attribute **new;
812 int j, i;
813
814 for (j = 0; a[j]; j++)
815 ;
816 for (i = 0; b[i]; i++)
817 j++;
818 for (i = 0; c[i]; i++)
819 j++;
820 j++;
821
822 new = kmalloc_array(j, sizeof(struct attribute *), GFP_KERNEL);
823 if (!new)
824 return NULL;
825 j = 0;
826 for (i = 0; a[i]; i++)
827 new[j++] = a[i];
828 for (i = 0; b[i]; i++)
829 new[j++] = b[i];
830 for (i = 0; c[i]; i++)
831 new[j++] = c[i];
832 new[j] = NULL;
833
834 return new;
835}
836
837__init const struct attribute_group **cpumf_cf_event_group(void)
838{
839 struct attribute **combined, **model, **cfvn, **csvn;
840 struct attribute *none[] = { NULL };
841 struct cpumf_ctr_info ci;
842 struct cpuid cpu_id;
843
844
845 qctri(&ci);
846 switch (ci.cfvn) {
847 case 1:
848 cfvn = cpumcf_fvn1_pmu_event_attr;
849 break;
850 case 3:
851 cfvn = cpumcf_fvn3_pmu_event_attr;
852 break;
853 default:
854 cfvn = none;
855 }
856
857
858 switch (ci.csvn) {
859 case 1 ... 5:
860 csvn = cpumcf_svn_12345_pmu_event_attr;
861 break;
862 case 6 ... 7:
863 csvn = cpumcf_svn_67_pmu_event_attr;
864 break;
865 default:
866 csvn = none;
867 }
868
869
870 get_cpu_id(&cpu_id);
871 switch (cpu_id.machine) {
872 case 0x2097:
873 case 0x2098:
874 model = cpumcf_z10_pmu_event_attr;
875 break;
876 case 0x2817:
877 case 0x2818:
878 model = cpumcf_z196_pmu_event_attr;
879 break;
880 case 0x2827:
881 case 0x2828:
882 model = cpumcf_zec12_pmu_event_attr;
883 break;
884 case 0x2964:
885 case 0x2965:
886 model = cpumcf_z13_pmu_event_attr;
887 break;
888 case 0x3906:
889 case 0x3907:
890 model = cpumcf_z14_pmu_event_attr;
891 break;
892 case 0x8561:
893 case 0x8562:
894 model = cpumcf_z15_pmu_event_attr;
895 break;
896 case 0x3931:
897 case 0x3932:
898 model = cpumcf_z16_pmu_event_attr;
899 break;
900 default:
901 model = none;
902 break;
903 }
904
905 combined = merge_attr(cfvn, csvn, model);
906 if (combined)
907 cpumcf_pmu_events_group.attrs = combined;
908 return cpumcf_pmu_attr_groups;
909}
910
