LXR linux/arch/sparc/include/asm/dma.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef _ASM_SPARC_DMA_H
   3#define _ASM_SPARC_DMA_H
   4
   5/* These are irrelevant for Sparc DMA, but we leave it in so that
   6 * things can compile.
   7 */
   8#define MAX_DMA_CHANNELS 8
   9#define DMA_MODE_READ    1
  10#define DMA_MODE_WRITE   2
  11#define MAX_DMA_ADDRESS  (~0UL)
  12
  13/* Useful constants */
  14#define SIZE_16MB      (16*1024*1024)
  15#define SIZE_64K       (64*1024)
  16
  17/* SBUS DMA controller reg offsets */
  18#define DMA_CSR         0x00UL          /* rw  DMA control/status register    0x00   */
  19#define DMA_ADDR        0x04UL          /* rw  DMA transfer address register  0x04   */
  20#define DMA_COUNT       0x08UL          /* rw  DMA transfer count register    0x08   */
  21#define DMA_TEST        0x0cUL          /* rw  DMA test/debug register        0x0c   */
  22
  23/* Fields in the cond_reg register */
  24/* First, the version identification bits */
  25#define DMA_DEVICE_ID    0xf0000000        /* Device identification bits */
  26#define DMA_VERS0        0x00000000        /* Sunray DMA version */
  27#define DMA_ESCV1        0x40000000        /* DMA ESC Version 1 */
  28#define DMA_VERS1        0x80000000        /* DMA rev 1 */
  29#define DMA_VERS2        0xa0000000        /* DMA rev 2 */
  30#define DMA_VERHME       0xb0000000        /* DMA hme gate array */
  31#define DMA_VERSPLUS     0x90000000        /* DMA rev 1 PLUS */
  32
  33#define DMA_HNDL_INTR    0x00000001        /* An IRQ needs to be handled */
  34#define DMA_HNDL_ERROR   0x00000002        /* We need to take an error */
  35#define DMA_FIFO_ISDRAIN 0x0000000c        /* The DMA FIFO is draining */
  36#define DMA_INT_ENAB     0x00000010        /* Turn on interrupts */
  37#define DMA_FIFO_INV     0x00000020        /* Invalidate the FIFO */
  38#define DMA_ACC_SZ_ERR   0x00000040        /* The access size was bad */
  39#define DMA_FIFO_STDRAIN 0x00000040        /* DMA_VERS1 Drain the FIFO */
  40#define DMA_RST_SCSI     0x00000080        /* Reset the SCSI controller */
  41#define DMA_RST_ENET     DMA_RST_SCSI      /* Reset the ENET controller */
  42#define DMA_ST_WRITE     0x00000100        /* write from device to memory */
  43#define DMA_ENABLE       0x00000200        /* Fire up DMA, handle requests */
  44#define DMA_PEND_READ    0x00000400        /* DMA_VERS1/0/PLUS Pending Read */
  45#define DMA_ESC_BURST    0x00000800        /* 1=16byte 0=32byte */
  46#define DMA_READ_AHEAD   0x00001800        /* DMA read ahead partial longword */
  47#define DMA_DSBL_RD_DRN  0x00001000        /* No EC drain on slave reads */
  48#define DMA_BCNT_ENAB    0x00002000        /* If on, use the byte counter */
  49#define DMA_TERM_CNTR    0x00004000        /* Terminal counter */
  50#define DMA_SCSI_SBUS64  0x00008000        /* HME: Enable 64-bit SBUS mode. */
  51#define DMA_CSR_DISAB    0x00010000        /* No FIFO drains during csr */
  52#define DMA_SCSI_DISAB   0x00020000        /* No FIFO drains during reg */
  53#define DMA_DSBL_WR_INV  0x00020000        /* No EC inval. on slave writes */
  54#define DMA_ADD_ENABLE   0x00040000        /* Special ESC DVMA optimization */
  55#define DMA_E_BURSTS     0x000c0000        /* ENET: SBUS r/w burst mask */
  56#define DMA_E_BURST32    0x00040000        /* ENET: SBUS 32 byte r/w burst */
  57#define DMA_E_BURST16    0x00000000        /* ENET: SBUS 16 byte r/w burst */
  58#define DMA_BRST_SZ      0x000c0000        /* SCSI: SBUS r/w burst size */
  59#define DMA_BRST64       0x000c0000        /* SCSI: 64byte bursts (HME on UltraSparc only) */
  60#define DMA_BRST32       0x00040000        /* SCSI: 32byte bursts */
  61#define DMA_BRST16       0x00000000        /* SCSI: 16byte bursts */
  62#define DMA_BRST0        0x00080000        /* SCSI: no bursts (non-HME gate arrays) */
  63#define DMA_ADDR_DISAB   0x00100000        /* No FIFO drains during addr */
  64#define DMA_2CLKS        0x00200000        /* Each transfer = 2 clock ticks */
  65#define DMA_3CLKS        0x00400000        /* Each transfer = 3 clock ticks */
  66#define DMA_EN_ENETAUI   DMA_3CLKS         /* Put lance into AUI-cable mode */
  67#define DMA_CNTR_DISAB   0x00800000        /* No IRQ when DMA_TERM_CNTR set */
  68#define DMA_AUTO_NADDR   0x01000000        /* Use "auto nxt addr" feature */
  69#define DMA_SCSI_ON      0x02000000        /* Enable SCSI dma */
  70#define DMA_PARITY_OFF   0x02000000        /* HME: disable parity checking */
  71#define DMA_LOADED_ADDR  0x04000000        /* Address has been loaded */
  72#define DMA_LOADED_NADDR 0x08000000        /* Next address has been loaded */
  73#define DMA_RESET_FAS366 0x08000000        /* HME: Assert RESET to FAS366 */
  74
  75/* Values describing the burst-size property from the PROM */
  76#define DMA_BURST1       0x01
  77#define DMA_BURST2       0x02
  78#define DMA_BURST4       0x04
  79#define DMA_BURST8       0x08
  80#define DMA_BURST16      0x10
  81#define DMA_BURST32      0x20
  82#define DMA_BURST64      0x40
  83#define DMA_BURSTBITS    0x7f
  84
  85/* From PCI */
  86
  87#ifdef CONFIG_PCI
  88extern int isa_dma_bridge_buggy;
  89#else
  90#define isa_dma_bridge_buggy    (0)
  91#endif
  92
  93#ifdef CONFIG_SPARC32
  94struct device;
  95
  96unsigned long sparc_dma_alloc_resource(struct device *dev, size_t len);
  97bool sparc_dma_free_resource(void *cpu_addr, size_t size);
  98#endif
  99
 100#endif /* !(_ASM_SPARC_DMA_H) */
 101