LXR linux/drivers/char/tpm/tpm_tis

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2005, 2006 IBM Corporation
   4 * Copyright (C) 2014, 2015 Intel Corporation
   5 *
   6 * Authors:
   7 * Leendert van Doorn <leendert@watson.ibm.com>
   8 * Kylene Hall <kjhall@us.ibm.com>
   9 *
  10 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
  11 *
  12 * Device driver for TCG/TCPA TPM (trusted platform module).
  13 * Specifications at www.trustedcomputinggroup.org
  14 *
  15 * This device driver implements the TPM interface as defined in
  16 * the TCG TPM Interface Spec version 1.2, revision 1.0.
  17 */
  18
  19#ifndef __TPM_TIS_CORE_H__
  20#define __TPM_TIS_CORE_H__
  21
  22#include "tpm.h"
  23
  24enum tis_access {
  25        TPM_ACCESS_VALID = 0x80,
  26        TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
  27        TPM_ACCESS_REQUEST_PENDING = 0x04,
  28        TPM_ACCESS_REQUEST_USE = 0x02,
  29};
  30
  31enum tis_status {
  32        TPM_STS_VALID = 0x80,
  33        TPM_STS_COMMAND_READY = 0x40,
  34        TPM_STS_GO = 0x20,
  35        TPM_STS_DATA_AVAIL = 0x10,
  36        TPM_STS_DATA_EXPECT = 0x08,
  37        TPM_STS_READ_ZERO = 0x23, /* bits that must be zero on read */
  38};
  39
  40enum tis_int_flags {
  41        TPM_GLOBAL_INT_ENABLE = 0x80000000,
  42        TPM_INTF_BURST_COUNT_STATIC = 0x100,
  43        TPM_INTF_CMD_READY_INT = 0x080,
  44        TPM_INTF_INT_EDGE_FALLING = 0x040,
  45        TPM_INTF_INT_EDGE_RISING = 0x020,
  46        TPM_INTF_INT_LEVEL_LOW = 0x010,
  47        TPM_INTF_INT_LEVEL_HIGH = 0x008,
  48        TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
  49        TPM_INTF_STS_VALID_INT = 0x002,
  50        TPM_INTF_DATA_AVAIL_INT = 0x001,
  51};
  52
  53enum tis_defaults {
  54        TIS_MEM_LEN = 0x5000,
  55        TIS_SHORT_TIMEOUT = 750,        /* ms */
  56        TIS_LONG_TIMEOUT = 2000,        /* 2 sec */
  57        TIS_TIMEOUT_MIN_ATML = 14700,   /* usecs */
  58        TIS_TIMEOUT_MAX_ATML = 15000,   /* usecs */
  59};
  60
  61/* Some timeout values are needed before it is known whether the chip is
  62 * TPM 1.0 or TPM 2.0.
  63 */
  64#define TIS_TIMEOUT_A_MAX       max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A)
  65#define TIS_TIMEOUT_B_MAX       max_t(int, TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B)
  66#define TIS_TIMEOUT_C_MAX       max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C)
  67#define TIS_TIMEOUT_D_MAX       max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D)
  68
  69#define TPM_ACCESS(l)                   (0x0000 | ((l) << 12))
  70#define TPM_INT_ENABLE(l)               (0x0008 | ((l) << 12))
  71#define TPM_INT_VECTOR(l)               (0x000C | ((l) << 12))
  72#define TPM_INT_STATUS(l)               (0x0010 | ((l) << 12))
  73#define TPM_INTF_CAPS(l)                (0x0014 | ((l) << 12))
  74#define TPM_STS(l)                      (0x0018 | ((l) << 12))
  75#define TPM_STS3(l)                     (0x001b | ((l) << 12))
  76#define TPM_DATA_FIFO(l)                (0x0024 | ((l) << 12))
  77
  78#define TPM_DID_VID(l)                  (0x0F00 | ((l) << 12))
  79#define TPM_RID(l)                      (0x0F04 | ((l) << 12))
  80
  81#define LPC_CNTRL_OFFSET                0x84
  82#define LPC_CLKRUN_EN                   (1 << 2)
  83#define INTEL_LEGACY_BLK_BASE_ADDR      0xFED08000
  84#define ILB_REMAP_SIZE                  0x100
  85
  86enum tpm_tis_flags {
  87        TPM_TIS_ITPM_WORKAROUND         = BIT(0),
  88        TPM_TIS_INVALID_STATUS          = BIT(1),
  89};
  90
  91struct tpm_tis_data {
  92        u16 manufacturer_id;
  93        int locality;
  94        int irq;
  95        bool irq_tested;
  96        unsigned long flags;
  97        void __iomem *ilb_base_addr;
  98        u16 clkrun_enabled;
  99        wait_queue_head_t int_queue;
 100        wait_queue_head_t read_queue;
 101        const struct tpm_tis_phy_ops *phy_ops;
 102        unsigned short rng_quality;
 103        unsigned int timeout_min; /* usecs */
 104        unsigned int timeout_max; /* usecs */
 105};
 106
 107/*
 108 * IO modes to indicate how many bytes should be read/written at once in the
 109 * tpm_tis_phy_ops read_bytes/write_bytes calls. Use TPM_TIS_PHYS_8 to
 110 * receive/transmit byte-wise, TPM_TIS_PHYS_16 for two bytes etc.
 111 */
 112enum tpm_tis_io_mode {
 113        TPM_TIS_PHYS_8,
 114        TPM_TIS_PHYS_16,
 115        TPM_TIS_PHYS_32,
 116};
 117
 118struct tpm_tis_phy_ops {
 119        /* data is passed in little endian */
 120        int (*read_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
 121                          u8 *result, enum tpm_tis_io_mode mode);
 122        int (*write_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
 123                           const u8 *value, enum tpm_tis_io_mode mode);
 124};
 125
 126static inline int tpm_tis_read_bytes(struct tpm_tis_data *data, u32 addr,
 127                                     u16 len, u8 *result)
 128{
 129        return data->phy_ops->read_bytes(data, addr, len, result,
 130                                         TPM_TIS_PHYS_8);
 131}
 132
 133static inline int tpm_tis_read8(struct tpm_tis_data *data, u32 addr, u8 *result)
 134{
 135        return data->phy_ops->read_bytes(data, addr, 1, result, TPM_TIS_PHYS_8);
 136}
 137
 138static inline int tpm_tis_read16(struct tpm_tis_data *data, u32 addr,
 139                                 u16 *result)
 140{
 141        __le16 result_le;
 142        int rc;
 143
 144        rc = data->phy_ops->read_bytes(data, addr, sizeof(u16),
 145                                       (u8 *)&result_le, TPM_TIS_PHYS_16);
 146        if (!rc)
 147                *result = le16_to_cpu(result_le);
 148
 149        return rc;
 150}
 151
 152static inline int tpm_tis_read32(struct tpm_tis_data *data, u32 addr,
 153                                 u32 *result)
 154{
 155        __le32 result_le;
 156        int rc;
 157
 158        rc = data->phy_ops->read_bytes(data, addr, sizeof(u32),
 159                                       (u8 *)&result_le, TPM_TIS_PHYS_32);
 160        if (!rc)
 161                *result = le32_to_cpu(result_le);
 162
 163        return rc;
 164}
 165
 166static inline int tpm_tis_write_bytes(struct tpm_tis_data *data, u32 addr,
 167                                      u16 len, const u8 *value)
 168{
 169        return data->phy_ops->write_bytes(data, addr, len, value,
 170                                          TPM_TIS_PHYS_8);
 171}
 172
 173static inline int tpm_tis_write8(struct tpm_tis_data *data, u32 addr, u8 value)
 174{
 175        return data->phy_ops->write_bytes(data, addr, 1, &value,
 176                                          TPM_TIS_PHYS_8);
 177}
 178
 179static inline int tpm_tis_write32(struct tpm_tis_data *data, u32 addr,
 180                                  u32 value)
 181{
 182        __le32 value_le;
 183        int rc;
 184
 185        value_le = cpu_to_le32(value);
 186        rc =  data->phy_ops->write_bytes(data, addr, sizeof(u32),
 187                                         (u8 *)&value_le, TPM_TIS_PHYS_32);
 188        return rc;
 189}
 190
 191static inline bool is_bsw(void)
 192{
 193#ifdef CONFIG_X86
 194        return ((boot_cpu_data.x86_model == INTEL_FAM6_ATOM_AIRMONT) ? 1 : 0);
 195#else
 196        return false;
 197#endif
 198}
 199
 200void tpm_tis_remove(struct tpm_chip *chip);
 201int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
 202                      const struct tpm_tis_phy_ops *phy_ops,
 203                      acpi_handle acpi_dev_handle);
 204
 205#ifdef CONFIG_PM_SLEEP
 206int tpm_tis_resume(struct device *dev);
 207#endif
 208
 209#endif
 210