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9#include <linux/kernel.h>
10#include <linux/errno.h>
11#include <linux/clk.h>
12#include <linux/io.h>
13#include <linux/bitops.h>
14#include <linux/clk/ti.h>
15
16#include "clock.h"
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23
24#define OMAP4_DPLL_LP_FINT_MAX 1000000
25#define OMAP4_DPLL_LP_FOUT_MAX 100000000
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29
30#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BIT(8)
31#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BIT(10)
32#define OMAP4430_DPLL_REGM4XEN_MASK BIT(11)
33
34
35#define OMAP4430_REGM4XEN_MULT 4
36
37static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
38{
39 u32 v;
40 u32 mask;
41
42 if (!clk)
43 return;
44
45 mask = clk->flags & CLOCK_CLKOUTX2 ?
46 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
47 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
48
49 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
50
51 v &= ~mask;
52 ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
53}
54
55static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
56{
57 u32 v;
58 u32 mask;
59
60 if (!clk)
61 return;
62
63 mask = clk->flags & CLOCK_CLKOUTX2 ?
64 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
65 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
66
67 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
68
69 v |= mask;
70 ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
71}
72
73const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
74 .allow_idle = omap4_dpllmx_allow_gatectrl,
75 .deny_idle = omap4_dpllmx_deny_gatectrl,
76};
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90static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
91{
92 long fint, fout;
93
94 fint = clk_hw_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);
95 fout = fint * dd->last_rounded_m;
96
97 if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX))
98 dd->last_rounded_lpmode = 1;
99 else
100 dd->last_rounded_lpmode = 0;
101}
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112
113unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
114 unsigned long parent_rate)
115{
116 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
117 u32 v;
118 unsigned long rate;
119 struct dpll_data *dd;
120
121 if (!clk || !clk->dpll_data)
122 return 0;
123
124 dd = clk->dpll_data;
125
126 rate = omap2_get_dpll_rate(clk);
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129 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
130 if (v & OMAP4430_DPLL_REGM4XEN_MASK)
131 rate *= OMAP4430_REGM4XEN_MULT;
132
133 return rate;
134}
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149long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
150 unsigned long target_rate,
151 unsigned long *parent_rate)
152{
153 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
154 struct dpll_data *dd;
155 long r;
156
157 if (!clk || !clk->dpll_data)
158 return -EINVAL;
159
160 dd = clk->dpll_data;
161
162 dd->last_rounded_m4xen = 0;
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168 r = omap2_dpll_round_rate(hw, target_rate, NULL);
169 if (r != ~0)
170 goto out;
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177 r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT,
178 NULL);
179 if (r == ~0)
180 return r;
181
182 dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
183 dd->last_rounded_m4xen = 1;
184
185out:
186 omap4_dpll_lpmode_recalc(dd);
187
188 return dd->last_rounded_rate;
189}
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201int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
202 struct clk_rate_request *req)
203{
204 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
205 struct dpll_data *dd;
206
207 if (!req->rate)
208 return -EINVAL;
209
210 dd = clk->dpll_data;
211 if (!dd)
212 return -EINVAL;
213
214 if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&
215 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
216 req->best_parent_hw = dd->clk_bypass;
217 } else {
218 req->rate = omap4_dpll_regm4xen_round_rate(hw, req->rate,
219 &req->best_parent_rate);
220 req->best_parent_hw = dd->clk_ref;
221 }
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223 req->best_parent_rate = req->rate;
224
225 return 0;
226}
227