LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2021 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#ifndef __AMDGPU_RESET_H__
  25#define __AMDGPU_RESET_H__
  26
  27#include "amdgpu.h"
  28
  29enum AMDGPU_RESET_FLAGS {
  30
  31        AMDGPU_NEED_FULL_RESET = 0,
  32        AMDGPU_SKIP_HW_RESET = 1,
  33};
  34
  35struct amdgpu_reset_context {
  36        enum amd_reset_method method;
  37        struct amdgpu_device *reset_req_dev;
  38        struct amdgpu_job *job;
  39        struct amdgpu_hive_info *hive;
  40        unsigned long flags;
  41};
  42
  43struct amdgpu_reset_handler {
  44        enum amd_reset_method reset_method;
  45        struct list_head handler_list;
  46        int (*prepare_env)(struct amdgpu_reset_control *reset_ctl,
  47                           struct amdgpu_reset_context *context);
  48        int (*prepare_hwcontext)(struct amdgpu_reset_control *reset_ctl,
  49                                 struct amdgpu_reset_context *context);
  50        int (*perform_reset)(struct amdgpu_reset_control *reset_ctl,
  51                             struct amdgpu_reset_context *context);
  52        int (*restore_hwcontext)(struct amdgpu_reset_control *reset_ctl,
  53                                 struct amdgpu_reset_context *context);
  54        int (*restore_env)(struct amdgpu_reset_control *reset_ctl,
  55                           struct amdgpu_reset_context *context);
  56
  57        int (*do_reset)(struct amdgpu_device *adev);
  58};
  59
  60struct amdgpu_reset_control {
  61        void *handle;
  62        struct work_struct reset_work;
  63        struct mutex reset_lock;
  64        struct list_head reset_handlers;
  65        atomic_t in_reset;
  66        enum amd_reset_method active_reset;
  67        struct amdgpu_reset_handler *(*get_reset_handler)(
  68                struct amdgpu_reset_control *reset_ctl,
  69                struct amdgpu_reset_context *context);
  70        void (*async_reset)(struct work_struct *work);
  71};
  72
  73
  74enum amdgpu_reset_domain_type {
  75        SINGLE_DEVICE,
  76        XGMI_HIVE
  77};
  78
  79struct amdgpu_reset_domain {
  80        struct kref refcount;
  81        struct workqueue_struct *wq;
  82        enum amdgpu_reset_domain_type type;
  83        struct rw_semaphore sem;
  84        atomic_t in_gpu_reset;
  85};
  86
  87
  88int amdgpu_reset_init(struct amdgpu_device *adev);
  89int amdgpu_reset_fini(struct amdgpu_device *adev);
  90
  91int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
  92                                   struct amdgpu_reset_context *reset_context);
  93
  94int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
  95                               struct amdgpu_reset_context *reset_context);
  96
  97int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
  98                             struct amdgpu_reset_handler *handler);
  99
 100struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
 101                                                             char *wq_name);
 102
 103void amdgpu_reset_destroy_reset_domain(struct kref *ref);
 104
 105static inline bool amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain *domain)
 106{
 107        return kref_get_unless_zero(&domain->refcount) != 0;
 108}
 109
 110static inline void amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain *domain)
 111{
 112        kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain);
 113}
 114
 115static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *domain,
 116                                                struct work_struct *work)
 117{
 118        return queue_work(domain->wq, work);
 119}
 120
 121void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain);
 122
 123void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain);
 124
 125#endif
 126