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27#include <linux/pci.h>
28
29#include <drm/drm_crtc_helper.h>
30#include <drm/amdgpu_drm.h>
31#include "amdgpu.h"
32#include "amdgpu_connectors.h"
33#include "amdgpu_display.h"
34#include "atom.h"
35#include "atombios_encoders.h"
36#include "atombios_dp.h"
37#include <linux/backlight.h>
38#include "bif/bif_4_1_d.h"
39
40u8
41amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev)
42{
43 u8 backlight_level;
44 u32 bios_2_scratch;
45
46 bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
47
48 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
49 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
50
51 return backlight_level;
52}
53
54void
55amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev,
56 u8 backlight_level)
57{
58 u32 bios_2_scratch;
59
60 bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
61
62 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
63 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
64 ATOM_S2_CURRENT_BL_LEVEL_MASK);
65
66 WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);
67}
68
69u8
70amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
71{
72 struct drm_device *dev = amdgpu_encoder->base.dev;
73 struct amdgpu_device *adev = drm_to_adev(dev);
74
75 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
76 return 0;
77
78 return amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
79}
80
81void
82amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
83 u8 level)
84{
85 struct drm_encoder *encoder = &amdgpu_encoder->base;
86 struct drm_device *dev = amdgpu_encoder->base.dev;
87 struct amdgpu_device *adev = drm_to_adev(dev);
88 struct amdgpu_encoder_atom_dig *dig;
89
90 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
91 return;
92
93 if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
94 amdgpu_encoder->enc_priv) {
95 dig = amdgpu_encoder->enc_priv;
96 dig->backlight_level = level;
97 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, dig->backlight_level);
98
99 switch (amdgpu_encoder->encoder_id) {
100 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
101 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
102 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
103 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
104 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
105 if (dig->backlight_level == 0)
106 amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
107 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
108 else {
109 amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
110 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
111 amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
112 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
113 }
114 break;
115 default:
116 break;
117 }
118 }
119}
120
121#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
122
123static u8 amdgpu_atombios_encoder_backlight_level(struct backlight_device *bd)
124{
125 u8 level;
126
127
128 if (bd->props.brightness < 0)
129 level = 0;
130 else if (bd->props.brightness > AMDGPU_MAX_BL_LEVEL)
131 level = AMDGPU_MAX_BL_LEVEL;
132 else
133 level = bd->props.brightness;
134
135 return level;
136}
137
138static int amdgpu_atombios_encoder_update_backlight_status(struct backlight_device *bd)
139{
140 struct amdgpu_backlight_privdata *pdata = bl_get_data(bd);
141 struct amdgpu_encoder *amdgpu_encoder = pdata->encoder;
142
143 amdgpu_atombios_encoder_set_backlight_level(amdgpu_encoder,
144 amdgpu_atombios_encoder_backlight_level(bd));
145
146 return 0;
147}
148
149static int
150amdgpu_atombios_encoder_get_backlight_brightness(struct backlight_device *bd)
151{
152 struct amdgpu_backlight_privdata *pdata = bl_get_data(bd);
153 struct amdgpu_encoder *amdgpu_encoder = pdata->encoder;
154 struct drm_device *dev = amdgpu_encoder->base.dev;
155 struct amdgpu_device *adev = drm_to_adev(dev);
156
157 return amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
158}
159
160static const struct backlight_ops amdgpu_atombios_encoder_backlight_ops = {
161 .get_brightness = amdgpu_atombios_encoder_get_backlight_brightness,
162 .update_status = amdgpu_atombios_encoder_update_backlight_status,
163};
164
165void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encoder,
166 struct drm_connector *drm_connector)
167{
168 struct drm_device *dev = amdgpu_encoder->base.dev;
169 struct amdgpu_device *adev = drm_to_adev(dev);
170 struct backlight_device *bd;
171 struct backlight_properties props;
172 struct amdgpu_backlight_privdata *pdata;
173 struct amdgpu_encoder_atom_dig *dig;
174 char bl_name[16];
175
176
177
178
179 if ((adev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
180 (adev->pdev->device == 0x6741))
181 return;
182
183 if (!amdgpu_encoder->enc_priv)
184 return;
185
186 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
187 return;
188
189 pdata = kmalloc(sizeof(struct amdgpu_backlight_privdata), GFP_KERNEL);
190 if (!pdata) {
191 DRM_ERROR("Memory allocation failed\n");
192 goto error;
193 }
194
195 memset(&props, 0, sizeof(props));
196 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
197 props.type = BACKLIGHT_RAW;
198 snprintf(bl_name, sizeof(bl_name),
199 "amdgpu_bl%d", dev->primary->index);
200 bd = backlight_device_register(bl_name, drm_connector->kdev,
201 pdata, &amdgpu_atombios_encoder_backlight_ops, &props);
202 if (IS_ERR(bd)) {
203 DRM_ERROR("Backlight registration failed\n");
204 goto error;
205 }
206
207 pdata->encoder = amdgpu_encoder;
208
209 dig = amdgpu_encoder->enc_priv;
210 dig->bl_dev = bd;
211
212 bd->props.brightness = amdgpu_atombios_encoder_get_backlight_brightness(bd);
213 bd->props.power = FB_BLANK_UNBLANK;
214 backlight_update_status(bd);
215
216 DRM_INFO("amdgpu atom DIG backlight initialized\n");
217
218 return;
219
220error:
221 kfree(pdata);
222 return;
223}
224
225void
226amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *amdgpu_encoder)
227{
228 struct drm_device *dev = amdgpu_encoder->base.dev;
229 struct amdgpu_device *adev = drm_to_adev(dev);
230 struct backlight_device *bd = NULL;
231 struct amdgpu_encoder_atom_dig *dig;
232
233 if (!amdgpu_encoder->enc_priv)
234 return;
235
236 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
237 return;
238
239 dig = amdgpu_encoder->enc_priv;
240 bd = dig->bl_dev;
241 dig->bl_dev = NULL;
242
243 if (bd) {
244 struct amdgpu_legacy_backlight_privdata *pdata;
245
246 pdata = bl_get_data(bd);
247 backlight_device_unregister(bd);
248 kfree(pdata);
249
250 DRM_INFO("amdgpu atom LVDS backlight unloaded\n");
251 }
252}
253
254#else
255
256void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *encoder)
257{
258}
259
260void amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *encoder)
261{
262}
263
264#endif
265
266bool amdgpu_atombios_encoder_is_digital(struct drm_encoder *encoder)
267{
268 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
269 switch (amdgpu_encoder->encoder_id) {
270 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
271 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
272 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
273 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
274 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
275 return true;
276 default:
277 return false;
278 }
279}
280
281bool amdgpu_atombios_encoder_mode_fixup(struct drm_encoder *encoder,
282 const struct drm_display_mode *mode,
283 struct drm_display_mode *adjusted_mode)
284{
285 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
286
287
288 amdgpu_encoder_set_active_device(encoder);
289 drm_mode_set_crtcinfo(adjusted_mode, 0);
290
291
292 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
293 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
294 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
295
296
297 if (mode->crtc_vsync_start == mode->crtc_vdisplay)
298 adjusted_mode->crtc_vsync_start++;
299
300
301 if (amdgpu_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
302 amdgpu_panel_mode_fixup(encoder, adjusted_mode);
303 else if (amdgpu_encoder->rmx_type != RMX_OFF)
304 amdgpu_panel_mode_fixup(encoder, adjusted_mode);
305
306 if ((amdgpu_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
307 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
308 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
309 amdgpu_atombios_dp_set_link_config(connector, adjusted_mode);
310 }
311
312 return true;
313}
314
315static void
316amdgpu_atombios_encoder_setup_dac(struct drm_encoder *encoder, int action)
317{
318 struct drm_device *dev = encoder->dev;
319 struct amdgpu_device *adev = drm_to_adev(dev);
320 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
321 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
322 int index = 0;
323
324 memset(&args, 0, sizeof(args));
325
326 switch (amdgpu_encoder->encoder_id) {
327 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
328 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
329 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
330 break;
331 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
332 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
333 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
334 break;
335 }
336
337 args.ucAction = action;
338 args.ucDacStandard = ATOM_DAC1_PS2;
339 args.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
340
341 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
342
343}
344
345static u8 amdgpu_atombios_encoder_get_bpc(struct drm_encoder *encoder)
346{
347 int bpc = 8;
348
349 if (encoder->crtc) {
350 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
351 bpc = amdgpu_crtc->bpc;
352 }
353
354 switch (bpc) {
355 case 0:
356 return PANEL_BPC_UNDEFINE;
357 case 6:
358 return PANEL_6BIT_PER_COLOR;
359 case 8:
360 default:
361 return PANEL_8BIT_PER_COLOR;
362 case 10:
363 return PANEL_10BIT_PER_COLOR;
364 case 12:
365 return PANEL_12BIT_PER_COLOR;
366 case 16:
367 return PANEL_16BIT_PER_COLOR;
368 }
369}
370
371union dvo_encoder_control {
372 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
373 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
374 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
375 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
376};
377
378static void
379amdgpu_atombios_encoder_setup_dvo(struct drm_encoder *encoder, int action)
380{
381 struct drm_device *dev = encoder->dev;
382 struct amdgpu_device *adev = drm_to_adev(dev);
383 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
384 union dvo_encoder_control args;
385 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
386 uint8_t frev, crev;
387
388 memset(&args, 0, sizeof(args));
389
390 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
391 return;
392
393 switch (frev) {
394 case 1:
395 switch (crev) {
396 case 1:
397
398 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
399
400 if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
401 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
402
403 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
404 break;
405 case 2:
406
407 args.dvo.sDVOEncoder.ucAction = action;
408 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
409
410 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
411
412 if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
413 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
414 break;
415 case 3:
416
417 args.dvo_v3.ucAction = action;
418 args.dvo_v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
419 args.dvo_v3.ucDVOConfig = 0;
420 break;
421 case 4:
422
423 args.dvo_v4.ucAction = action;
424 args.dvo_v4.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
425 args.dvo_v4.ucDVOConfig = 0;
426 args.dvo_v4.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder);
427 break;
428 default:
429 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
430 break;
431 }
432 break;
433 default:
434 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
435 break;
436 }
437
438 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
439}
440
441int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder)
442{
443 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
444 struct drm_connector *connector;
445 struct amdgpu_connector *amdgpu_connector;
446 struct amdgpu_connector_atom_dig *dig_connector;
447
448
449 if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
450 return ATOM_ENCODER_MODE_DP;
451
452
453 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
454 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
455 return ATOM_ENCODER_MODE_DVO;
456
457 connector = amdgpu_get_connector_for_encoder(encoder);
458
459
460
461 if (!connector)
462 connector = amdgpu_get_connector_for_encoder_init(encoder);
463 amdgpu_connector = to_amdgpu_connector(connector);
464
465 switch (connector->connector_type) {
466 case DRM_MODE_CONNECTOR_DVII:
467 case DRM_MODE_CONNECTOR_HDMIB:
468 if (amdgpu_audio != 0) {
469 if (amdgpu_connector->use_digital &&
470 (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE))
471 return ATOM_ENCODER_MODE_HDMI;
472 else if (connector->display_info.is_hdmi &&
473 (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO))
474 return ATOM_ENCODER_MODE_HDMI;
475 else if (amdgpu_connector->use_digital)
476 return ATOM_ENCODER_MODE_DVI;
477 else
478 return ATOM_ENCODER_MODE_CRT;
479 } else if (amdgpu_connector->use_digital) {
480 return ATOM_ENCODER_MODE_DVI;
481 } else {
482 return ATOM_ENCODER_MODE_CRT;
483 }
484 break;
485 case DRM_MODE_CONNECTOR_DVID:
486 case DRM_MODE_CONNECTOR_HDMIA:
487 default:
488 if (amdgpu_audio != 0) {
489 if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE)
490 return ATOM_ENCODER_MODE_HDMI;
491 else if (connector->display_info.is_hdmi &&
492 (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO))
493 return ATOM_ENCODER_MODE_HDMI;
494 else
495 return ATOM_ENCODER_MODE_DVI;
496 } else {
497 return ATOM_ENCODER_MODE_DVI;
498 }
499 case DRM_MODE_CONNECTOR_LVDS:
500 return ATOM_ENCODER_MODE_LVDS;
501 case DRM_MODE_CONNECTOR_DisplayPort:
502 dig_connector = amdgpu_connector->con_priv;
503 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
504 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
505 return ATOM_ENCODER_MODE_DP;
506 } else if (amdgpu_audio != 0) {
507 if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE)
508 return ATOM_ENCODER_MODE_HDMI;
509 else if (connector->display_info.is_hdmi &&
510 (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO))
511 return ATOM_ENCODER_MODE_HDMI;
512 else
513 return ATOM_ENCODER_MODE_DVI;
514 } else {
515 return ATOM_ENCODER_MODE_DVI;
516 }
517 case DRM_MODE_CONNECTOR_eDP:
518 return ATOM_ENCODER_MODE_DP;
519 case DRM_MODE_CONNECTOR_DVIA:
520 case DRM_MODE_CONNECTOR_VGA:
521 return ATOM_ENCODER_MODE_CRT;
522 case DRM_MODE_CONNECTOR_Composite:
523 case DRM_MODE_CONNECTOR_SVIDEO:
524 case DRM_MODE_CONNECTOR_9PinDIN:
525
526 return ATOM_ENCODER_MODE_TV;
527 }
528}
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554union dig_encoder_control {
555 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
556 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
557 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
558 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
559 DIG_ENCODER_CONTROL_PARAMETERS_V5 v5;
560};
561
562void
563amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder,
564 int action, int panel_mode)
565{
566 struct drm_device *dev = encoder->dev;
567 struct amdgpu_device *adev = drm_to_adev(dev);
568 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
569 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
570 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
571 union dig_encoder_control args;
572 int index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
573 uint8_t frev, crev;
574 int dp_clock = 0;
575 int dp_lane_count = 0;
576 int hpd_id = AMDGPU_HPD_NONE;
577
578 if (connector) {
579 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
580 struct amdgpu_connector_atom_dig *dig_connector =
581 amdgpu_connector->con_priv;
582
583 dp_clock = dig_connector->dp_clock;
584 dp_lane_count = dig_connector->dp_lane_count;
585 hpd_id = amdgpu_connector->hpd.hpd;
586 }
587
588
589 if (dig->dig_encoder == -1)
590 return;
591
592 memset(&args, 0, sizeof(args));
593
594 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
595 return;
596
597 switch (frev) {
598 case 1:
599 switch (crev) {
600 case 1:
601 args.v1.ucAction = action;
602 args.v1.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
603 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
604 args.v3.ucPanelMode = panel_mode;
605 else
606 args.v1.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
607
608 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
609 args.v1.ucLaneNum = dp_lane_count;
610 else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
611 args.v1.ucLaneNum = 8;
612 else
613 args.v1.ucLaneNum = 4;
614
615 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
616 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
617 switch (amdgpu_encoder->encoder_id) {
618 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
619 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
620 break;
621 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
622 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
623 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
624 break;
625 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
626 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
627 break;
628 }
629 if (dig->linkb)
630 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
631 else
632 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
633 break;
634 case 2:
635 case 3:
636 args.v3.ucAction = action;
637 args.v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
638 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
639 args.v3.ucPanelMode = panel_mode;
640 else
641 args.v3.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
642
643 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
644 args.v3.ucLaneNum = dp_lane_count;
645 else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
646 args.v3.ucLaneNum = 8;
647 else
648 args.v3.ucLaneNum = 4;
649
650 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
651 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
652 args.v3.acConfig.ucDigSel = dig->dig_encoder;
653 args.v3.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder);
654 break;
655 case 4:
656 args.v4.ucAction = action;
657 args.v4.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
658 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
659 args.v4.ucPanelMode = panel_mode;
660 else
661 args.v4.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
662
663 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
664 args.v4.ucLaneNum = dp_lane_count;
665 else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
666 args.v4.ucLaneNum = 8;
667 else
668 args.v4.ucLaneNum = 4;
669
670 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
671 if (dp_clock == 540000)
672 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
673 else if (dp_clock == 324000)
674 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
675 else if (dp_clock == 270000)
676 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
677 else
678 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
679 }
680 args.v4.acConfig.ucDigSel = dig->dig_encoder;
681 args.v4.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder);
682 if (hpd_id == AMDGPU_HPD_NONE)
683 args.v4.ucHPD_ID = 0;
684 else
685 args.v4.ucHPD_ID = hpd_id + 1;
686 break;
687 case 5:
688 switch (action) {
689 case ATOM_ENCODER_CMD_SETUP_PANEL_MODE:
690 args.v5.asDPPanelModeParam.ucAction = action;
691 args.v5.asDPPanelModeParam.ucPanelMode = panel_mode;
692 args.v5.asDPPanelModeParam.ucDigId = dig->dig_encoder;
693 break;
694 case ATOM_ENCODER_CMD_STREAM_SETUP:
695 args.v5.asStreamParam.ucAction = action;
696 args.v5.asStreamParam.ucDigId = dig->dig_encoder;
697 args.v5.asStreamParam.ucDigMode =
698 amdgpu_atombios_encoder_get_encoder_mode(encoder);
699 if (ENCODER_MODE_IS_DP(args.v5.asStreamParam.ucDigMode))
700 args.v5.asStreamParam.ucLaneNum = dp_lane_count;
701 else if (amdgpu_dig_monitor_is_duallink(encoder,
702 amdgpu_encoder->pixel_clock))
703 args.v5.asStreamParam.ucLaneNum = 8;
704 else
705 args.v5.asStreamParam.ucLaneNum = 4;
706 args.v5.asStreamParam.ulPixelClock =
707 cpu_to_le32(amdgpu_encoder->pixel_clock / 10);
708 args.v5.asStreamParam.ucBitPerColor =
709 amdgpu_atombios_encoder_get_bpc(encoder);
710 args.v5.asStreamParam.ucLinkRateIn270Mhz = dp_clock / 27000;
711 break;
712 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_START:
713 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1:
714 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2:
715 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3:
716 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4:
717 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE:
718 case ATOM_ENCODER_CMD_DP_VIDEO_OFF:
719 case ATOM_ENCODER_CMD_DP_VIDEO_ON:
720 args.v5.asCmdParam.ucAction = action;
721 args.v5.asCmdParam.ucDigId = dig->dig_encoder;
722 break;
723 default:
724 DRM_ERROR("Unsupported action 0x%x\n", action);
725 break;
726 }
727 break;
728 default:
729 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
730 break;
731 }
732 break;
733 default:
734 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
735 break;
736 }
737
738 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
739
740}
741
742union dig_transmitter_control {
743 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
744 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
745 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
746 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
747 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
748 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 v6;
749};
750
751void
752amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int action,
753 uint8_t lane_num, uint8_t lane_set)
754{
755 struct drm_device *dev = encoder->dev;
756 struct amdgpu_device *adev = drm_to_adev(dev);
757 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
758 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
759 struct drm_connector *connector;
760 union dig_transmitter_control args;
761 int index = 0;
762 uint8_t frev, crev;
763 bool is_dp = false;
764 int pll_id = 0;
765 int dp_clock = 0;
766 int dp_lane_count = 0;
767 int connector_object_id = 0;
768 int dig_encoder = dig->dig_encoder;
769 int hpd_id = AMDGPU_HPD_NONE;
770
771 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
772 connector = amdgpu_get_connector_for_encoder_init(encoder);
773
774
775
776 dig_encoder = 0;
777 } else
778 connector = amdgpu_get_connector_for_encoder(encoder);
779
780 if (connector) {
781 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
782 struct amdgpu_connector_atom_dig *dig_connector =
783 amdgpu_connector->con_priv;
784
785 hpd_id = amdgpu_connector->hpd.hpd;
786 dp_clock = dig_connector->dp_clock;
787 dp_lane_count = dig_connector->dp_lane_count;
788 connector_object_id =
789 (amdgpu_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
790 }
791
792 if (encoder->crtc) {
793 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
794 pll_id = amdgpu_crtc->pll_id;
795 }
796
797
798 if (dig_encoder == -1)
799 return;
800
801 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)))
802 is_dp = true;
803
804 memset(&args, 0, sizeof(args));
805
806 switch (amdgpu_encoder->encoder_id) {
807 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
808 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
809 break;
810 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
811 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
812 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
813 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
814 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
815 break;
816 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
817 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
818 break;
819 }
820
821 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
822 return;
823
824 switch (frev) {
825 case 1:
826 switch (crev) {
827 case 1:
828 args.v1.ucAction = action;
829 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
830 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
831 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
832 args.v1.asMode.ucLaneSel = lane_num;
833 args.v1.asMode.ucLaneSet = lane_set;
834 } else {
835 if (is_dp)
836 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
837 else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
838 args.v1.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10);
839 else
840 args.v1.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
841 }
842
843 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
844
845 if (dig_encoder)
846 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
847 else
848 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
849
850 if (dig->linkb)
851 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
852 else
853 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
854
855 if (is_dp)
856 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
857 else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
858 if (dig->coherent_mode)
859 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
860 if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
861 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
862 }
863 break;
864 case 2:
865 args.v2.ucAction = action;
866 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
867 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
868 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
869 args.v2.asMode.ucLaneSel = lane_num;
870 args.v2.asMode.ucLaneSet = lane_set;
871 } else {
872 if (is_dp)
873 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
874 else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
875 args.v2.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10);
876 else
877 args.v2.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
878 }
879
880 args.v2.acConfig.ucEncoderSel = dig_encoder;
881 if (dig->linkb)
882 args.v2.acConfig.ucLinkSel = 1;
883
884 switch (amdgpu_encoder->encoder_id) {
885 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
886 args.v2.acConfig.ucTransmitterSel = 0;
887 break;
888 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
889 args.v2.acConfig.ucTransmitterSel = 1;
890 break;
891 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
892 args.v2.acConfig.ucTransmitterSel = 2;
893 break;
894 }
895
896 if (is_dp) {
897 args.v2.acConfig.fCoherentMode = 1;
898 args.v2.acConfig.fDPConnector = 1;
899 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
900 if (dig->coherent_mode)
901 args.v2.acConfig.fCoherentMode = 1;
902 if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
903 args.v2.acConfig.fDualLinkConnector = 1;
904 }
905 break;
906 case 3:
907 args.v3.ucAction = action;
908 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
909 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
910 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
911 args.v3.asMode.ucLaneSel = lane_num;
912 args.v3.asMode.ucLaneSet = lane_set;
913 } else {
914 if (is_dp)
915 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
916 else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
917 args.v3.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10);
918 else
919 args.v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
920 }
921
922 if (is_dp)
923 args.v3.ucLaneNum = dp_lane_count;
924 else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
925 args.v3.ucLaneNum = 8;
926 else
927 args.v3.ucLaneNum = 4;
928
929 if (dig->linkb)
930 args.v3.acConfig.ucLinkSel = 1;
931 if (dig_encoder & 1)
932 args.v3.acConfig.ucEncoderSel = 1;
933
934
935
936
937
938
939 if (is_dp && adev->clock.dp_extclk)
940 args.v3.acConfig.ucRefClkSource = 2;
941 else
942 args.v3.acConfig.ucRefClkSource = pll_id;
943
944 switch (amdgpu_encoder->encoder_id) {
945 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
946 args.v3.acConfig.ucTransmitterSel = 0;
947 break;
948 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
949 args.v3.acConfig.ucTransmitterSel = 1;
950 break;
951 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
952 args.v3.acConfig.ucTransmitterSel = 2;
953 break;
954 }
955
956 if (is_dp)
957 args.v3.acConfig.fCoherentMode = 1;
958 else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
959 if (dig->coherent_mode)
960 args.v3.acConfig.fCoherentMode = 1;
961 if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
962 args.v3.acConfig.fDualLinkConnector = 1;
963 }
964 break;
965 case 4:
966 args.v4.ucAction = action;
967 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
968 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
969 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
970 args.v4.asMode.ucLaneSel = lane_num;
971 args.v4.asMode.ucLaneSet = lane_set;
972 } else {
973 if (is_dp)
974 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
975 else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
976 args.v4.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10);
977 else
978 args.v4.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
979 }
980
981 if (is_dp)
982 args.v4.ucLaneNum = dp_lane_count;
983 else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
984 args.v4.ucLaneNum = 8;
985 else
986 args.v4.ucLaneNum = 4;
987
988 if (dig->linkb)
989 args.v4.acConfig.ucLinkSel = 1;
990 if (dig_encoder & 1)
991 args.v4.acConfig.ucEncoderSel = 1;
992
993
994
995
996
997
998 if (is_dp) {
999 if (adev->clock.dp_extclk)
1000 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1001 else
1002 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1003 } else
1004 args.v4.acConfig.ucRefClkSource = pll_id;
1005
1006 switch (amdgpu_encoder->encoder_id) {
1007 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1008 args.v4.acConfig.ucTransmitterSel = 0;
1009 break;
1010 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1011 args.v4.acConfig.ucTransmitterSel = 1;
1012 break;
1013 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1014 args.v4.acConfig.ucTransmitterSel = 2;
1015 break;
1016 }
1017
1018 if (is_dp)
1019 args.v4.acConfig.fCoherentMode = 1;
1020 else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1021 if (dig->coherent_mode)
1022 args.v4.acConfig.fCoherentMode = 1;
1023 if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
1024 args.v4.acConfig.fDualLinkConnector = 1;
1025 }
1026 break;
1027 case 5:
1028 args.v5.ucAction = action;
1029 if (is_dp)
1030 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1031 else
1032 args.v5.usSymClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
1033
1034 switch (amdgpu_encoder->encoder_id) {
1035 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1036 if (dig->linkb)
1037 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1038 else
1039 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1040 break;
1041 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1042 if (dig->linkb)
1043 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1044 else
1045 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1046 break;
1047 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1048 if (dig->linkb)
1049 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1050 else
1051 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1052 break;
1053 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1054 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1055 break;
1056 }
1057 if (is_dp)
1058 args.v5.ucLaneNum = dp_lane_count;
1059 else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
1060 args.v5.ucLaneNum = 8;
1061 else
1062 args.v5.ucLaneNum = 4;
1063 args.v5.ucConnObjId = connector_object_id;
1064 args.v5.ucDigMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1065
1066 if (is_dp && adev->clock.dp_extclk)
1067 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1068 else
1069 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1070
1071 if (is_dp)
1072 args.v5.asConfig.ucCoherentMode = 1;
1073 else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1074 if (dig->coherent_mode)
1075 args.v5.asConfig.ucCoherentMode = 1;
1076 }
1077 if (hpd_id == AMDGPU_HPD_NONE)
1078 args.v5.asConfig.ucHPDSel = 0;
1079 else
1080 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1081 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1082 args.v5.ucDPLaneSet = lane_set;
1083 break;
1084 case 6:
1085 args.v6.ucAction = action;
1086 if (is_dp)
1087 args.v6.ulSymClock = cpu_to_le32(dp_clock / 10);
1088 else
1089 args.v6.ulSymClock = cpu_to_le32(amdgpu_encoder->pixel_clock / 10);
1090
1091 switch (amdgpu_encoder->encoder_id) {
1092 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1093 if (dig->linkb)
1094 args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1095 else
1096 args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1097 break;
1098 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1099 if (dig->linkb)
1100 args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1101 else
1102 args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1103 break;
1104 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1105 if (dig->linkb)
1106 args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1107 else
1108 args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1109 break;
1110 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1111 args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1112 break;
1113 }
1114 if (is_dp)
1115 args.v6.ucLaneNum = dp_lane_count;
1116 else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
1117 args.v6.ucLaneNum = 8;
1118 else
1119 args.v6.ucLaneNum = 4;
1120 args.v6.ucConnObjId = connector_object_id;
1121 if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH)
1122 args.v6.ucDPLaneSet = lane_set;
1123 else
1124 args.v6.ucDigMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1125
1126 if (hpd_id == AMDGPU_HPD_NONE)
1127 args.v6.ucHPDSel = 0;
1128 else
1129 args.v6.ucHPDSel = hpd_id + 1;
1130 args.v6.ucDigEncoderSel = 1 << dig_encoder;
1131 break;
1132 default:
1133 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1134 break;
1135 }
1136 break;
1137 default:
1138 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1139 break;
1140 }
1141
1142 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1143}
1144
1145bool
1146amdgpu_atombios_encoder_set_edp_panel_power(struct drm_connector *connector,
1147 int action)
1148{
1149 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1150 struct drm_device *dev = amdgpu_connector->base.dev;
1151 struct amdgpu_device *adev = drm_to_adev(dev);
1152 union dig_transmitter_control args;
1153 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1154 uint8_t frev, crev;
1155
1156 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1157 goto done;
1158
1159 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1160 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1161 goto done;
1162
1163 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1164 goto done;
1165
1166 memset(&args, 0, sizeof(args));
1167
1168 args.v1.ucAction = action;
1169
1170 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1171
1172
1173 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1174 int i;
1175
1176 for (i = 0; i < 300; i++) {
1177 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
1178 return true;
1179 mdelay(1);
1180 }
1181 return false;
1182 }
1183done:
1184 return true;
1185}
1186
1187union external_encoder_control {
1188 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1189 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1190};
1191
1192static void
1193amdgpu_atombios_encoder_setup_external_encoder(struct drm_encoder *encoder,
1194 struct drm_encoder *ext_encoder,
1195 int action)
1196{
1197 struct drm_device *dev = encoder->dev;
1198 struct amdgpu_device *adev = drm_to_adev(dev);
1199 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1200 struct amdgpu_encoder *ext_amdgpu_encoder = to_amdgpu_encoder(ext_encoder);
1201 union external_encoder_control args;
1202 struct drm_connector *connector;
1203 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1204 u8 frev, crev;
1205 int dp_clock = 0;
1206 int dp_lane_count = 0;
1207 int connector_object_id = 0;
1208 u32 ext_enum = (ext_amdgpu_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1209
1210 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1211 connector = amdgpu_get_connector_for_encoder_init(encoder);
1212 else
1213 connector = amdgpu_get_connector_for_encoder(encoder);
1214
1215 if (connector) {
1216 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1217 struct amdgpu_connector_atom_dig *dig_connector =
1218 amdgpu_connector->con_priv;
1219
1220 dp_clock = dig_connector->dp_clock;
1221 dp_lane_count = dig_connector->dp_lane_count;
1222 connector_object_id =
1223 (amdgpu_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1224 }
1225
1226 memset(&args, 0, sizeof(args));
1227
1228 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1229 return;
1230
1231 switch (frev) {
1232 case 1:
1233
1234 break;
1235 case 2:
1236 switch (crev) {
1237 case 1:
1238 case 2:
1239 args.v1.sDigEncoder.ucAction = action;
1240 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
1241 args.v1.sDigEncoder.ucEncoderMode =
1242 amdgpu_atombios_encoder_get_encoder_mode(encoder);
1243
1244 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1245 if (dp_clock == 270000)
1246 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1247 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1248 } else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
1249 args.v1.sDigEncoder.ucLaneNum = 8;
1250 else
1251 args.v1.sDigEncoder.ucLaneNum = 4;
1252 break;
1253 case 3:
1254 args.v3.sExtEncoder.ucAction = action;
1255 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1256 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1257 else
1258 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
1259 args.v3.sExtEncoder.ucEncoderMode =
1260 amdgpu_atombios_encoder_get_encoder_mode(encoder);
1261
1262 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1263 if (dp_clock == 270000)
1264 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1265 else if (dp_clock == 540000)
1266 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1267 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1268 } else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
1269 args.v3.sExtEncoder.ucLaneNum = 8;
1270 else
1271 args.v3.sExtEncoder.ucLaneNum = 4;
1272 switch (ext_enum) {
1273 case GRAPH_OBJECT_ENUM_ID1:
1274 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1275 break;
1276 case GRAPH_OBJECT_ENUM_ID2:
1277 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1278 break;
1279 case GRAPH_OBJECT_ENUM_ID3:
1280 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1281 break;
1282 }
1283 args.v3.sExtEncoder.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder);
1284 break;
1285 default:
1286 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1287 return;
1288 }
1289 break;
1290 default:
1291 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1292 return;
1293 }
1294 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1295}
1296
1297static void
1298amdgpu_atombios_encoder_setup_dig(struct drm_encoder *encoder, int action)
1299{
1300 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1301 struct drm_encoder *ext_encoder = amdgpu_get_external_encoder(encoder);
1302 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1303 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1304 struct amdgpu_connector *amdgpu_connector = NULL;
1305 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = NULL;
1306
1307 if (connector) {
1308 amdgpu_connector = to_amdgpu_connector(connector);
1309 amdgpu_dig_connector = amdgpu_connector->con_priv;
1310 }
1311
1312 if (action == ATOM_ENABLE) {
1313 if (!connector)
1314 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1315 else
1316 dig->panel_mode = amdgpu_atombios_dp_get_panel_mode(encoder, connector);
1317
1318
1319 amdgpu_atombios_encoder_setup_dig_encoder(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1320 amdgpu_atombios_encoder_setup_dig_encoder(encoder,
1321 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1322 dig->panel_mode);
1323 if (ext_encoder)
1324 amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder,
1325 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1326 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) &&
1327 connector) {
1328 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1329 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1330 ATOM_TRANSMITTER_ACTION_POWER_ON);
1331 amdgpu_dig_connector->edp_on = true;
1332 }
1333 }
1334
1335 amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
1336 ATOM_TRANSMITTER_ACTION_ENABLE,
1337 0, 0);
1338 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) &&
1339 connector) {
1340
1341 amdgpu_atombios_dp_link_train(encoder, connector);
1342 amdgpu_atombios_encoder_setup_dig_encoder(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1343 }
1344 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1345 amdgpu_atombios_encoder_set_backlight_level(amdgpu_encoder, dig->backlight_level);
1346 if (ext_encoder)
1347 amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder, ATOM_ENABLE);
1348 } else {
1349 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) &&
1350 connector)
1351 amdgpu_atombios_encoder_setup_dig_encoder(encoder,
1352 ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1353 if (ext_encoder)
1354 amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder, ATOM_DISABLE);
1355 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1356 amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
1357 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1358
1359 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) &&
1360 connector)
1361 amdgpu_atombios_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1362
1363 amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
1364 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1365 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) &&
1366 connector) {
1367 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1368 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1369 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1370 amdgpu_dig_connector->edp_on = false;
1371 }
1372 }
1373 }
1374}
1375
1376void
1377amdgpu_atombios_encoder_dpms(struct drm_encoder *encoder, int mode)
1378{
1379 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1380
1381 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1382 amdgpu_encoder->encoder_id, mode, amdgpu_encoder->devices,
1383 amdgpu_encoder->active_device);
1384 switch (amdgpu_encoder->encoder_id) {
1385 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1386 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1387 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1388 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1389 switch (mode) {
1390 case DRM_MODE_DPMS_ON:
1391 amdgpu_atombios_encoder_setup_dig(encoder, ATOM_ENABLE);
1392 break;
1393 case DRM_MODE_DPMS_STANDBY:
1394 case DRM_MODE_DPMS_SUSPEND:
1395 case DRM_MODE_DPMS_OFF:
1396 amdgpu_atombios_encoder_setup_dig(encoder, ATOM_DISABLE);
1397 break;
1398 }
1399 break;
1400 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1401 switch (mode) {
1402 case DRM_MODE_DPMS_ON:
1403 amdgpu_atombios_encoder_setup_dvo(encoder, ATOM_ENABLE);
1404 break;
1405 case DRM_MODE_DPMS_STANDBY:
1406 case DRM_MODE_DPMS_SUSPEND:
1407 case DRM_MODE_DPMS_OFF:
1408 amdgpu_atombios_encoder_setup_dvo(encoder, ATOM_DISABLE);
1409 break;
1410 }
1411 break;
1412 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1413 switch (mode) {
1414 case DRM_MODE_DPMS_ON:
1415 amdgpu_atombios_encoder_setup_dac(encoder, ATOM_ENABLE);
1416 break;
1417 case DRM_MODE_DPMS_STANDBY:
1418 case DRM_MODE_DPMS_SUSPEND:
1419 case DRM_MODE_DPMS_OFF:
1420 amdgpu_atombios_encoder_setup_dac(encoder, ATOM_DISABLE);
1421 break;
1422 }
1423 break;
1424 default:
1425 return;
1426 }
1427}
1428
1429union crtc_source_param {
1430 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1431 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1432 SELECT_CRTC_SOURCE_PARAMETERS_V3 v3;
1433};
1434
1435void
1436amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
1437{
1438 struct drm_device *dev = encoder->dev;
1439 struct amdgpu_device *adev = drm_to_adev(dev);
1440 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1441 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1442 union crtc_source_param args;
1443 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1444 uint8_t frev, crev;
1445 struct amdgpu_encoder_atom_dig *dig;
1446
1447 memset(&args, 0, sizeof(args));
1448
1449 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1450 return;
1451
1452 switch (frev) {
1453 case 1:
1454 switch (crev) {
1455 case 1:
1456 default:
1457 args.v1.ucCRTC = amdgpu_crtc->crtc_id;
1458 switch (amdgpu_encoder->encoder_id) {
1459 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1460 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1461 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1462 break;
1463 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1464 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1465 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1466 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1467 else
1468 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1469 break;
1470 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1471 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1472 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1473 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1474 break;
1475 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1476 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1477 if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1478 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1479 else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1480 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1481 else
1482 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1483 break;
1484 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1485 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1486 if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1487 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1488 else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1489 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1490 else
1491 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1492 break;
1493 }
1494 break;
1495 case 2:
1496 args.v2.ucCRTC = amdgpu_crtc->crtc_id;
1497 if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1498 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1499
1500 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1501 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1502 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1503 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1504 else
1505 args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1506 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1507 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1508 } else {
1509 args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1510 }
1511 switch (amdgpu_encoder->encoder_id) {
1512 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1513 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1514 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1515 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1516 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1517 dig = amdgpu_encoder->enc_priv;
1518 switch (dig->dig_encoder) {
1519 case 0:
1520 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1521 break;
1522 case 1:
1523 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1524 break;
1525 case 2:
1526 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1527 break;
1528 case 3:
1529 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1530 break;
1531 case 4:
1532 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1533 break;
1534 case 5:
1535 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1536 break;
1537 case 6:
1538 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1539 break;
1540 }
1541 break;
1542 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1543 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1544 break;
1545 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1546 if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1547 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1548 else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1549 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1550 else
1551 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1552 break;
1553 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1554 if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1555 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1556 else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1557 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1558 else
1559 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1560 break;
1561 }
1562 break;
1563 case 3:
1564 args.v3.ucCRTC = amdgpu_crtc->crtc_id;
1565 if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1566 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1567
1568 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1569 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1570 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1571 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1572 else
1573 args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1574 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1575 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1576 } else {
1577 args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1578 }
1579 args.v3.ucDstBpc = amdgpu_atombios_encoder_get_bpc(encoder);
1580 switch (amdgpu_encoder->encoder_id) {
1581 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1582 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1583 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1584 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1585 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1586 dig = amdgpu_encoder->enc_priv;
1587 switch (dig->dig_encoder) {
1588 case 0:
1589 args.v3.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1590 break;
1591 case 1:
1592 args.v3.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1593 break;
1594 case 2:
1595 args.v3.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1596 break;
1597 case 3:
1598 args.v3.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1599 break;
1600 case 4:
1601 args.v3.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1602 break;
1603 case 5:
1604 args.v3.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1605 break;
1606 case 6:
1607 args.v3.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1608 break;
1609 }
1610 break;
1611 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1612 args.v3.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1613 break;
1614 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1615 if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1616 args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1617 else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1618 args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1619 else
1620 args.v3.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1621 break;
1622 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1623 if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1624 args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1625 else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1626 args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1627 else
1628 args.v3.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1629 break;
1630 }
1631 break;
1632 }
1633 break;
1634 default:
1635 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1636 return;
1637 }
1638
1639 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1640}
1641
1642
1643void
1644amdgpu_atombios_encoder_init_dig(struct amdgpu_device *adev)
1645{
1646 struct drm_device *dev = adev_to_drm(adev);
1647 struct drm_encoder *encoder;
1648
1649 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1650 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1651 struct drm_encoder *ext_encoder = amdgpu_get_external_encoder(encoder);
1652
1653 switch (amdgpu_encoder->encoder_id) {
1654 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1655 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1656 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1657 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1658 amdgpu_atombios_encoder_setup_dig_transmitter(encoder, ATOM_TRANSMITTER_ACTION_INIT,
1659 0, 0);
1660 break;
1661 }
1662
1663 if (ext_encoder)
1664 amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder,
1665 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1666 }
1667}
1668
1669static bool
1670amdgpu_atombios_encoder_dac_load_detect(struct drm_encoder *encoder,
1671 struct drm_connector *connector)
1672{
1673 struct drm_device *dev = encoder->dev;
1674 struct amdgpu_device *adev = drm_to_adev(dev);
1675 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1676 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1677
1678 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1679 ATOM_DEVICE_CV_SUPPORT |
1680 ATOM_DEVICE_CRT_SUPPORT)) {
1681 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1682 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1683 uint8_t frev, crev;
1684
1685 memset(&args, 0, sizeof(args));
1686
1687 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1688 return false;
1689
1690 args.sDacload.ucMisc = 0;
1691
1692 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1693 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1694 args.sDacload.ucDacType = ATOM_DAC_A;
1695 else
1696 args.sDacload.ucDacType = ATOM_DAC_B;
1697
1698 if (amdgpu_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1699 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1700 else if (amdgpu_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1701 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1702 else if (amdgpu_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1703 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1704 if (crev >= 3)
1705 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1706 } else if (amdgpu_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1707 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1708 if (crev >= 3)
1709 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1710 }
1711
1712 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1713
1714 return true;
1715 } else
1716 return false;
1717}
1718
1719enum drm_connector_status
1720amdgpu_atombios_encoder_dac_detect(struct drm_encoder *encoder,
1721 struct drm_connector *connector)
1722{
1723 struct drm_device *dev = encoder->dev;
1724 struct amdgpu_device *adev = drm_to_adev(dev);
1725 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1726 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1727 uint32_t bios_0_scratch;
1728
1729 if (!amdgpu_atombios_encoder_dac_load_detect(encoder, connector)) {
1730 DRM_DEBUG_KMS("detect returned false \n");
1731 return connector_status_unknown;
1732 }
1733
1734 bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);
1735
1736 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, amdgpu_encoder->devices);
1737 if (amdgpu_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1738 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1739 return connector_status_connected;
1740 }
1741 if (amdgpu_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1742 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1743 return connector_status_connected;
1744 }
1745 if (amdgpu_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1746 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1747 return connector_status_connected;
1748 }
1749 if (amdgpu_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1750 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1751 return connector_status_connected;
1752 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1753 return connector_status_connected;
1754 }
1755 return connector_status_disconnected;
1756}
1757
1758enum drm_connector_status
1759amdgpu_atombios_encoder_dig_detect(struct drm_encoder *encoder,
1760 struct drm_connector *connector)
1761{
1762 struct drm_device *dev = encoder->dev;
1763 struct amdgpu_device *adev = drm_to_adev(dev);
1764 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1765 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1766 struct drm_encoder *ext_encoder = amdgpu_get_external_encoder(encoder);
1767 u32 bios_0_scratch;
1768
1769 if (!ext_encoder)
1770 return connector_status_unknown;
1771
1772 if ((amdgpu_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
1773 return connector_status_unknown;
1774
1775
1776 amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder,
1777 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
1778
1779 bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);
1780
1781 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, amdgpu_encoder->devices);
1782 if (amdgpu_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1783 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1784 return connector_status_connected;
1785 }
1786 if (amdgpu_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1787 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1788 return connector_status_connected;
1789 }
1790 if (amdgpu_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1791 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1792 return connector_status_connected;
1793 }
1794 if (amdgpu_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1795 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1796 return connector_status_connected;
1797 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1798 return connector_status_connected;
1799 }
1800 return connector_status_disconnected;
1801}
1802
1803void
1804amdgpu_atombios_encoder_setup_ext_encoder_ddc(struct drm_encoder *encoder)
1805{
1806 struct drm_encoder *ext_encoder = amdgpu_get_external_encoder(encoder);
1807
1808 if (ext_encoder)
1809
1810 amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder,
1811 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
1812
1813}
1814
1815void
1816amdgpu_atombios_encoder_set_bios_scratch_regs(struct drm_connector *connector,
1817 struct drm_encoder *encoder,
1818 bool connected)
1819{
1820 struct drm_device *dev = connector->dev;
1821 struct amdgpu_device *adev = drm_to_adev(dev);
1822 struct amdgpu_connector *amdgpu_connector =
1823 to_amdgpu_connector(connector);
1824 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1825 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1826
1827 bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);
1828 bios_3_scratch = RREG32(mmBIOS_SCRATCH_3);
1829 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1830
1831 if ((amdgpu_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1832 (amdgpu_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1833 if (connected) {
1834 DRM_DEBUG_KMS("LCD1 connected\n");
1835 bios_0_scratch |= ATOM_S0_LCD1;
1836 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1837 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1838 } else {
1839 DRM_DEBUG_KMS("LCD1 disconnected\n");
1840 bios_0_scratch &= ~ATOM_S0_LCD1;
1841 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1842 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1843 }
1844 }
1845 if ((amdgpu_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1846 (amdgpu_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1847 if (connected) {
1848 DRM_DEBUG_KMS("CRT1 connected\n");
1849 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1850 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1851 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1852 } else {
1853 DRM_DEBUG_KMS("CRT1 disconnected\n");
1854 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1855 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1856 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1857 }
1858 }
1859 if ((amdgpu_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1860 (amdgpu_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1861 if (connected) {
1862 DRM_DEBUG_KMS("CRT2 connected\n");
1863 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1864 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1865 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1866 } else {
1867 DRM_DEBUG_KMS("CRT2 disconnected\n");
1868 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1869 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1870 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1871 }
1872 }
1873 if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1874 (amdgpu_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1875 if (connected) {
1876 DRM_DEBUG_KMS("DFP1 connected\n");
1877 bios_0_scratch |= ATOM_S0_DFP1;
1878 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1879 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1880 } else {
1881 DRM_DEBUG_KMS("DFP1 disconnected\n");
1882 bios_0_scratch &= ~ATOM_S0_DFP1;
1883 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1884 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1885 }
1886 }
1887 if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1888 (amdgpu_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1889 if (connected) {
1890 DRM_DEBUG_KMS("DFP2 connected\n");
1891 bios_0_scratch |= ATOM_S0_DFP2;
1892 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1893 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1894 } else {
1895 DRM_DEBUG_KMS("DFP2 disconnected\n");
1896 bios_0_scratch &= ~ATOM_S0_DFP2;
1897 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1898 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1899 }
1900 }
1901 if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1902 (amdgpu_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1903 if (connected) {
1904 DRM_DEBUG_KMS("DFP3 connected\n");
1905 bios_0_scratch |= ATOM_S0_DFP3;
1906 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1907 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1908 } else {
1909 DRM_DEBUG_KMS("DFP3 disconnected\n");
1910 bios_0_scratch &= ~ATOM_S0_DFP3;
1911 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1912 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1913 }
1914 }
1915 if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1916 (amdgpu_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1917 if (connected) {
1918 DRM_DEBUG_KMS("DFP4 connected\n");
1919 bios_0_scratch |= ATOM_S0_DFP4;
1920 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1921 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1922 } else {
1923 DRM_DEBUG_KMS("DFP4 disconnected\n");
1924 bios_0_scratch &= ~ATOM_S0_DFP4;
1925 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1926 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1927 }
1928 }
1929 if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1930 (amdgpu_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1931 if (connected) {
1932 DRM_DEBUG_KMS("DFP5 connected\n");
1933 bios_0_scratch |= ATOM_S0_DFP5;
1934 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1935 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1936 } else {
1937 DRM_DEBUG_KMS("DFP5 disconnected\n");
1938 bios_0_scratch &= ~ATOM_S0_DFP5;
1939 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1940 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1941 }
1942 }
1943 if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
1944 (amdgpu_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
1945 if (connected) {
1946 DRM_DEBUG_KMS("DFP6 connected\n");
1947 bios_0_scratch |= ATOM_S0_DFP6;
1948 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
1949 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
1950 } else {
1951 DRM_DEBUG_KMS("DFP6 disconnected\n");
1952 bios_0_scratch &= ~ATOM_S0_DFP6;
1953 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
1954 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
1955 }
1956 }
1957
1958 WREG32(mmBIOS_SCRATCH_0, bios_0_scratch);
1959 WREG32(mmBIOS_SCRATCH_3, bios_3_scratch);
1960 WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1961}
1962
1963union lvds_info {
1964 struct _ATOM_LVDS_INFO info;
1965 struct _ATOM_LVDS_INFO_V12 info_12;
1966};
1967
1968struct amdgpu_encoder_atom_dig *
1969amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder)
1970{
1971 struct drm_device *dev = encoder->base.dev;
1972 struct amdgpu_device *adev = drm_to_adev(dev);
1973 struct amdgpu_mode_info *mode_info = &adev->mode_info;
1974 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1975 uint16_t data_offset, misc;
1976 union lvds_info *lvds_info;
1977 uint8_t frev, crev;
1978 struct amdgpu_encoder_atom_dig *lvds = NULL;
1979 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1980
1981 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
1982 &frev, &crev, &data_offset)) {
1983 lvds_info =
1984 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1985 lvds =
1986 kzalloc(sizeof(struct amdgpu_encoder_atom_dig), GFP_KERNEL);
1987
1988 if (!lvds)
1989 return NULL;
1990
1991 lvds->native_mode.clock =
1992 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1993 lvds->native_mode.hdisplay =
1994 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1995 lvds->native_mode.vdisplay =
1996 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1997 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1998 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1999 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
2000 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
2001 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
2002 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
2003 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
2004 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
2005 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
2006 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
2007 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
2008 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
2009 lvds->panel_pwr_delay =
2010 le16_to_cpu(lvds_info->info.usOffDelayInMs);
2011 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
2012
2013 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
2014 if (misc & ATOM_VSYNC_POLARITY)
2015 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2016 if (misc & ATOM_HSYNC_POLARITY)
2017 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2018 if (misc & ATOM_COMPOSITESYNC)
2019 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
2020 if (misc & ATOM_INTERLACE)
2021 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
2022 if (misc & ATOM_DOUBLE_CLOCK_MODE)
2023 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
2024
2025 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
2026 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
2027
2028
2029 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
2030
2031 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
2032
2033 encoder->native_mode = lvds->native_mode;
2034
2035 if (encoder_enum == 2)
2036 lvds->linkb = true;
2037 else
2038 lvds->linkb = false;
2039
2040
2041 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
2042 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
2043 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
2044 bool bad_record = false;
2045 u8 *record;
2046
2047 if ((frev == 1) && (crev < 2))
2048
2049 record = (u8 *)(mode_info->atom_context->bios +
2050 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
2051 else
2052
2053 record = (u8 *)(mode_info->atom_context->bios +
2054 data_offset +
2055 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
2056 while (*record != ATOM_RECORD_END_TYPE) {
2057 switch (*record) {
2058 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
2059 record += sizeof(ATOM_PATCH_RECORD_MODE);
2060 break;
2061 case LCD_RTS_RECORD_TYPE:
2062 record += sizeof(ATOM_LCD_RTS_RECORD);
2063 break;
2064 case LCD_CAP_RECORD_TYPE:
2065 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
2066 break;
2067 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
2068 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
2069 if (fake_edid_record->ucFakeEDIDLength) {
2070 struct edid *edid;
2071 int edid_size =
2072 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
2073 edid = kmalloc(edid_size, GFP_KERNEL);
2074 if (edid) {
2075 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
2076 fake_edid_record->ucFakeEDIDLength);
2077
2078 if (drm_edid_is_valid(edid)) {
2079 adev->mode_info.bios_hardcoded_edid = edid;
2080 adev->mode_info.bios_hardcoded_edid_size = edid_size;
2081 } else
2082 kfree(edid);
2083 }
2084 }
2085 record += fake_edid_record->ucFakeEDIDLength ?
2086 fake_edid_record->ucFakeEDIDLength + 2 :
2087 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
2088 break;
2089 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
2090 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
2091 lvds->native_mode.width_mm = panel_res_record->usHSize;
2092 lvds->native_mode.height_mm = panel_res_record->usVSize;
2093 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
2094 break;
2095 default:
2096 DRM_ERROR("Bad LCD record %d\n", *record);
2097 bad_record = true;
2098 break;
2099 }
2100 if (bad_record)
2101 break;
2102 }
2103 }
2104 }
2105 return lvds;
2106}
2107
2108struct amdgpu_encoder_atom_dig *
2109amdgpu_atombios_encoder_get_dig_info(struct amdgpu_encoder *amdgpu_encoder)
2110{
2111 int encoder_enum = (amdgpu_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2112 struct amdgpu_encoder_atom_dig *dig = kzalloc(sizeof(struct amdgpu_encoder_atom_dig), GFP_KERNEL);
2113
2114 if (!dig)
2115 return NULL;
2116
2117
2118 dig->coherent_mode = true;
2119 dig->dig_encoder = -1;
2120
2121 if (encoder_enum == 2)
2122 dig->linkb = true;
2123 else
2124 dig->linkb = false;
2125
2126 return dig;
2127}
2128
2129
