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23#include "amdgpu.h"
24#include "smuio_v11_0.h"
25#include "smuio/smuio_11_0_0_offset.h"
26#include "smuio/smuio_11_0_0_sh_mask.h"
27
28static u32 smuio_v11_0_get_rom_index_offset(struct amdgpu_device *adev)
29{
30 return SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
31}
32
33static u32 smuio_v11_0_get_rom_data_offset(struct amdgpu_device *adev)
34{
35 return SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
36}
37
38static void smuio_v11_0_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
39{
40 u32 def, data;
41
42
43 if (adev->flags & AMD_IS_APU)
44 return;
45
46 if (!(adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
47 return;
48
49 def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
50
51 if (enable)
52 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
53 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
54 else
55 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
56 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
57
58 if (def != data)
59 WREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0, data);
60}
61
62static void smuio_v11_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags)
63{
64 u32 data;
65
66
67 if (adev->flags & AMD_IS_APU)
68 return;
69
70 data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
71 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
72 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
73}
74
75const struct amdgpu_smuio_funcs smuio_v11_0_funcs = {
76 .get_rom_index_offset = smuio_v11_0_get_rom_index_offset,
77 .get_rom_data_offset = smuio_v11_0_get_rom_data_offset,
78 .update_rom_clock_gating = smuio_v11_0_update_rom_clock_gating,
79 .get_clock_gating_state = smuio_v11_0_get_clock_gating_state,
80};
81