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26#ifndef DC_DP_TYPES_H
27#define DC_DP_TYPES_H
28
29#include "os_types.h"
30
31enum dc_lane_count {
32 LANE_COUNT_UNKNOWN = 0,
33 LANE_COUNT_ONE = 1,
34 LANE_COUNT_TWO = 2,
35 LANE_COUNT_FOUR = 4,
36 LANE_COUNT_EIGHT = 8,
37 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
38};
39
40
41
42
43
44
45
46
47enum dc_link_rate {
48 LINK_RATE_UNKNOWN = 0,
49 LINK_RATE_LOW = 0x06,
50 LINK_RATE_RATE_2 = 0x08,
51 LINK_RATE_RATE_3 = 0x09,
52 LINK_RATE_HIGH = 0x0A,
53 LINK_RATE_RBR2 = 0x0C,
54 LINK_RATE_RATE_6 = 0x10,
55 LINK_RATE_HIGH2 = 0x14,
56 LINK_RATE_HIGH3 = 0x1E,
57
58
59
60 LINK_RATE_UHBR10 = 1000,
61 LINK_RATE_UHBR13_5 = 1350,
62 LINK_RATE_UHBR20 = 2000,
63};
64
65enum dc_link_spread {
66 LINK_SPREAD_DISABLED = 0x00,
67
68 LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
69
70 LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
71};
72
73enum dc_voltage_swing {
74 VOLTAGE_SWING_LEVEL0 = 0,
75 VOLTAGE_SWING_LEVEL1,
76 VOLTAGE_SWING_LEVEL2,
77 VOLTAGE_SWING_LEVEL3,
78 VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
79};
80
81enum dc_pre_emphasis {
82 PRE_EMPHASIS_DISABLED = 0,
83 PRE_EMPHASIS_LEVEL1,
84 PRE_EMPHASIS_LEVEL2,
85 PRE_EMPHASIS_LEVEL3,
86 PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
87};
88
89
90
91enum dc_post_cursor2 {
92 POST_CURSOR2_DISABLED = 0,
93 POST_CURSOR2_LEVEL1,
94 POST_CURSOR2_LEVEL2,
95 POST_CURSOR2_LEVEL3,
96 POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
97};
98
99enum dc_dp_ffe_preset_level {
100 DP_FFE_PRESET_LEVEL0 = 0,
101 DP_FFE_PRESET_LEVEL1,
102 DP_FFE_PRESET_LEVEL2,
103 DP_FFE_PRESET_LEVEL3,
104 DP_FFE_PRESET_LEVEL4,
105 DP_FFE_PRESET_LEVEL5,
106 DP_FFE_PRESET_LEVEL6,
107 DP_FFE_PRESET_LEVEL7,
108 DP_FFE_PRESET_LEVEL8,
109 DP_FFE_PRESET_LEVEL9,
110 DP_FFE_PRESET_LEVEL10,
111 DP_FFE_PRESET_LEVEL11,
112 DP_FFE_PRESET_LEVEL12,
113 DP_FFE_PRESET_LEVEL13,
114 DP_FFE_PRESET_LEVEL14,
115 DP_FFE_PRESET_LEVEL15,
116 DP_FFE_PRESET_MAX_LEVEL = DP_FFE_PRESET_LEVEL15,
117};
118
119enum dc_dp_training_pattern {
120 DP_TRAINING_PATTERN_SEQUENCE_1 = 0,
121 DP_TRAINING_PATTERN_SEQUENCE_2,
122 DP_TRAINING_PATTERN_SEQUENCE_3,
123 DP_TRAINING_PATTERN_SEQUENCE_4,
124 DP_TRAINING_PATTERN_VIDEOIDLE,
125 DP_128b_132b_TPS1,
126 DP_128b_132b_TPS2,
127 DP_128b_132b_TPS2_CDS,
128};
129
130enum dp_link_encoding {
131 DP_UNKNOWN_ENCODING = 0,
132 DP_8b_10b_ENCODING = 1,
133 DP_128b_132b_ENCODING = 2,
134};
135
136enum dp_test_link_rate {
137 DP_TEST_LINK_RATE_RBR = 0x06,
138 DP_TEST_LINK_RATE_HBR = 0x0A,
139 DP_TEST_LINK_RATE_HBR2 = 0x14,
140 DP_TEST_LINK_RATE_HBR3 = 0x1E,
141 DP_TEST_LINK_RATE_UHBR10 = 0x01,
142 DP_TEST_LINK_RATE_UHBR20 = 0x02,
143 DP_TEST_LINK_RATE_UHBR13_5 = 0x03,
144};
145
146struct dc_link_settings {
147 enum dc_lane_count lane_count;
148 enum dc_link_rate link_rate;
149 enum dc_link_spread link_spread;
150 bool use_link_rate_set;
151 uint8_t link_rate_set;
152 bool dpcd_source_device_specific_field_support;
153};
154
155union dc_dp_ffe_preset {
156 struct {
157 uint8_t level : 4;
158 uint8_t reserved : 1;
159 uint8_t no_preshoot : 1;
160 uint8_t no_deemphasis : 1;
161 uint8_t method2 : 1;
162 } settings;
163 uint8_t raw;
164};
165
166struct dc_lane_settings {
167 enum dc_voltage_swing VOLTAGE_SWING;
168 enum dc_pre_emphasis PRE_EMPHASIS;
169 enum dc_post_cursor2 POST_CURSOR2;
170 union dc_dp_ffe_preset FFE_PRESET;
171};
172
173struct dc_link_training_overrides {
174 enum dc_voltage_swing *voltage_swing;
175 enum dc_pre_emphasis *pre_emphasis;
176 enum dc_post_cursor2 *post_cursor2;
177 union dc_dp_ffe_preset *ffe_preset;
178
179 uint16_t *cr_pattern_time;
180 uint16_t *eq_pattern_time;
181 enum dc_dp_training_pattern *pattern_for_cr;
182 enum dc_dp_training_pattern *pattern_for_eq;
183
184 enum dc_link_spread *downspread;
185 bool *alternate_scrambler_reset;
186 bool *enhanced_framing;
187 bool *mst_enable;
188 bool *fec_enable;
189};
190
191union payload_table_update_status {
192 struct {
193 uint8_t VC_PAYLOAD_TABLE_UPDATED:1;
194 uint8_t ACT_HANDLED:1;
195 } bits;
196 uint8_t raw;
197};
198
199union dpcd_rev {
200 struct {
201 uint8_t MINOR:4;
202 uint8_t MAJOR:4;
203 } bits;
204 uint8_t raw;
205};
206
207union max_lane_count {
208 struct {
209 uint8_t MAX_LANE_COUNT:5;
210 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
211 uint8_t TPS3_SUPPORTED:1;
212 uint8_t ENHANCED_FRAME_CAP:1;
213 } bits;
214 uint8_t raw;
215};
216
217union max_down_spread {
218 struct {
219 uint8_t MAX_DOWN_SPREAD:1;
220 uint8_t RESERVED:5;
221 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
222 uint8_t TPS4_SUPPORTED:1;
223 } bits;
224 uint8_t raw;
225};
226
227union mstm_cap {
228 struct {
229 uint8_t MST_CAP:1;
230 uint8_t RESERVED:7;
231 } bits;
232 uint8_t raw;
233};
234
235union lane_count_set {
236 struct {
237 uint8_t LANE_COUNT_SET:5;
238 uint8_t POST_LT_ADJ_REQ_GRANTED:1;
239 uint8_t RESERVED:1;
240 uint8_t ENHANCED_FRAMING:1;
241 } bits;
242 uint8_t raw;
243};
244
245union lane_status {
246 struct {
247 uint8_t CR_DONE_0:1;
248 uint8_t CHANNEL_EQ_DONE_0:1;
249 uint8_t SYMBOL_LOCKED_0:1;
250 uint8_t RESERVED0:1;
251 uint8_t CR_DONE_1:1;
252 uint8_t CHANNEL_EQ_DONE_1:1;
253 uint8_t SYMBOL_LOCKED_1:1;
254 uint8_t RESERVED_1:1;
255 } bits;
256 uint8_t raw;
257};
258
259union device_service_irq {
260 struct {
261 uint8_t REMOTE_CONTROL_CMD_PENDING:1;
262 uint8_t AUTOMATED_TEST:1;
263 uint8_t CP_IRQ:1;
264 uint8_t MCCS_IRQ:1;
265 uint8_t DOWN_REP_MSG_RDY:1;
266 uint8_t UP_REQ_MSG_RDY:1;
267 uint8_t SINK_SPECIFIC:1;
268 uint8_t reserved:1;
269 } bits;
270 uint8_t raw;
271};
272
273union sink_count {
274 struct {
275 uint8_t SINK_COUNT:6;
276 uint8_t CPREADY:1;
277 uint8_t RESERVED:1;
278 } bits;
279 uint8_t raw;
280};
281
282union lane_align_status_updated {
283 struct {
284 uint8_t INTERLANE_ALIGN_DONE:1;
285 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
286 uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1;
287 uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1;
288 uint8_t LT_FAILED_128b_132b:1;
289 uint8_t RESERVED:1;
290 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
291 uint8_t LINK_STATUS_UPDATED:1;
292 } bits;
293 uint8_t raw;
294};
295
296union lane_adjust {
297 struct {
298 uint8_t VOLTAGE_SWING_LANE:2;
299 uint8_t PRE_EMPHASIS_LANE:2;
300 uint8_t RESERVED:4;
301 } bits;
302 struct {
303 uint8_t PRESET_VALUE :4;
304 uint8_t RESERVED :4;
305 } tx_ffe;
306 uint8_t raw;
307};
308
309union dpcd_training_pattern {
310 struct {
311 uint8_t TRAINING_PATTERN_SET:4;
312 uint8_t RECOVERED_CLOCK_OUT_EN:1;
313 uint8_t SCRAMBLING_DISABLE:1;
314 uint8_t SYMBOL_ERROR_COUNT_SEL:2;
315 } v1_4;
316 struct {
317 uint8_t TRAINING_PATTERN_SET:2;
318 uint8_t LINK_QUAL_PATTERN_SET:2;
319 uint8_t RESERVED:4;
320 } v1_3;
321 uint8_t raw;
322};
323
324
325
326
327union dpcd_training_lane {
328 struct {
329 uint8_t VOLTAGE_SWING_SET:2;
330 uint8_t MAX_SWING_REACHED:1;
331 uint8_t PRE_EMPHASIS_SET:2;
332 uint8_t MAX_PRE_EMPHASIS_REACHED:1;
333 uint8_t RESERVED:2;
334 } bits;
335 struct {
336 uint8_t PRESET_VALUE :4;
337 uint8_t RESERVED :4;
338 } tx_ffe;
339 uint8_t raw;
340};
341
342
343union dwnstream_port_caps_byte0 {
344 struct {
345 uint8_t DWN_STRM_PORTX_TYPE:3;
346 uint8_t DWN_STRM_PORTX_HPD:1;
347 uint8_t RESERVERD:4;
348 } bits;
349 uint8_t raw;
350};
351
352
353enum dpcd_downstream_port_detailed_type {
354 DOWN_STREAM_DETAILED_DP = 0,
355 DOWN_STREAM_DETAILED_VGA,
356 DOWN_STREAM_DETAILED_DVI,
357 DOWN_STREAM_DETAILED_HDMI,
358 DOWN_STREAM_DETAILED_NONDDC,
359 DOWN_STREAM_DETAILED_DP_PLUS_PLUS
360};
361
362union dwnstream_port_caps_byte2 {
363 struct {
364 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
365#if defined(CONFIG_DRM_AMD_DC_DCN)
366 uint8_t MAX_ENCODED_LINK_BW_SUPPORT:3;
367 uint8_t SOURCE_CONTROL_MODE_SUPPORT:1;
368 uint8_t CONCURRENT_LINK_BRING_UP_SEQ_SUPPORT:1;
369 uint8_t RESERVED:1;
370#else
371 uint8_t RESERVED:6;
372#endif
373 } bits;
374 uint8_t raw;
375};
376
377union dp_downstream_port_present {
378 uint8_t byte;
379 struct {
380 uint8_t PORT_PRESENT:1;
381 uint8_t PORT_TYPE:2;
382 uint8_t FMT_CONVERSION:1;
383 uint8_t DETAILED_CAPS:1;
384 uint8_t RESERVED:3;
385 } fields;
386};
387
388union dwnstream_port_caps_byte3_dvi {
389 struct {
390 uint8_t RESERVED1:1;
391 uint8_t DUAL_LINK:1;
392 uint8_t HIGH_COLOR_DEPTH:1;
393 uint8_t RESERVED2:5;
394 } bits;
395 uint8_t raw;
396};
397
398union dwnstream_port_caps_byte3_hdmi {
399 struct {
400 uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
401 uint8_t YCrCr422_PASS_THROUGH:1;
402 uint8_t YCrCr420_PASS_THROUGH:1;
403 uint8_t YCrCr422_CONVERSION:1;
404 uint8_t YCrCr420_CONVERSION:1;
405 uint8_t RESERVED:3;
406 } bits;
407 uint8_t raw;
408};
409
410#if defined(CONFIG_DRM_AMD_DC_DCN)
411union hdmi_sink_encoded_link_bw_support {
412 struct {
413 uint8_t HDMI_SINK_ENCODED_LINK_BW_SUPPORT:3;
414 uint8_t RESERVED:5;
415 } bits;
416 uint8_t raw;
417};
418
419union hdmi_encoded_link_bw {
420 struct {
421 uint8_t FRL_MODE:1;
422 uint8_t BW_9Gbps:1;
423 uint8_t BW_18Gbps:1;
424 uint8_t BW_24Gbps:1;
425 uint8_t BW_32Gbps:1;
426 uint8_t BW_40Gbps:1;
427 uint8_t BW_48Gbps:1;
428 uint8_t RESERVED:1;
429 } bits;
430 uint8_t raw;
431};
432#endif
433
434
435
436union dwnstream_portxcaps {
437 struct {
438 union dwnstream_port_caps_byte0 byte0;
439 unsigned char max_TMDS_clock;
440 union dwnstream_port_caps_byte2 byte2;
441
442 union {
443 union dwnstream_port_caps_byte3_dvi byteDVI;
444 union dwnstream_port_caps_byte3_hdmi byteHDMI;
445 } byte3;
446 } bytes;
447
448 unsigned char raw[4];
449};
450
451union downstream_port {
452 struct {
453 unsigned char present:1;
454 unsigned char type:2;
455 unsigned char format_conv:1;
456 unsigned char detailed_caps:1;
457 unsigned char reserved:3;
458 } bits;
459 unsigned char raw;
460};
461
462
463union sink_status {
464 struct {
465 uint8_t RX_PORT0_STATUS:1;
466 uint8_t RX_PORT1_STATUS:1;
467 uint8_t RESERVED:6;
468 } bits;
469 uint8_t raw;
470};
471
472
473
474union hpd_irq_data {
475 struct {
476 union sink_count sink_cnt;
477 union device_service_irq device_service_irq;
478 union lane_status lane01_status;
479 union lane_status lane23_status;
480 union lane_align_status_updated lane_status_updated;
481 union sink_status sink_status;
482 } bytes;
483 uint8_t raw[6];
484};
485
486union down_stream_port_count {
487 struct {
488 uint8_t DOWN_STR_PORT_COUNT:4;
489 uint8_t RESERVED:2;
490
491
492
493
494 uint8_t IGNORE_MSA_TIMING_PARAM:1;
495
496
497
498
499 uint8_t OUI_SUPPORT:1;
500 } bits;
501 uint8_t raw;
502};
503
504union down_spread_ctrl {
505 struct {
506 uint8_t RESERVED1:4;
507
508
509
510
511 uint8_t SPREAD_AMP:1;
512 uint8_t RESERVED2:2;
513
514
515
516 uint8_t IGNORE_MSA_TIMING_PARAM:1;
517 } bits;
518 uint8_t raw;
519};
520
521union dpcd_edp_config {
522 struct {
523 uint8_t PANEL_MODE_EDP:1;
524 uint8_t FRAMING_CHANGE_ENABLE:1;
525 uint8_t RESERVED:5;
526 uint8_t PANEL_SELF_TEST_ENABLE:1;
527 } bits;
528 uint8_t raw;
529};
530
531struct dp_device_vendor_id {
532 uint8_t ieee_oui[3];
533 uint8_t ieee_device_id[6];
534};
535
536struct dp_sink_hw_fw_revision {
537 uint8_t ieee_hw_rev;
538 uint8_t ieee_fw_rev[2];
539};
540
541struct dpcd_vendor_signature {
542 bool is_valid;
543
544 union dpcd_ieee_vendor_signature {
545 struct {
546 uint8_t ieee_oui[3];
547 uint8_t ieee_device_id[6];
548 uint8_t ieee_hw_rev;
549 uint8_t ieee_fw_rev[2];
550 };
551 uint8_t raw[12];
552 } data;
553};
554
555struct dpcd_amd_signature {
556 uint8_t AMD_IEEE_TxSignature_byte1;
557 uint8_t AMD_IEEE_TxSignature_byte2;
558 uint8_t AMD_IEEE_TxSignature_byte3;
559};
560
561struct dpcd_amd_device_id {
562 uint8_t device_id_byte1;
563 uint8_t device_id_byte2;
564 uint8_t zero[4];
565 uint8_t dce_version;
566 uint8_t dal_version_byte1;
567 uint8_t dal_version_byte2;
568};
569
570struct dpcd_source_backlight_set {
571 struct {
572 uint8_t byte0;
573 uint8_t byte1;
574 uint8_t byte2;
575 uint8_t byte3;
576 } backlight_level_millinits;
577
578 struct {
579 uint8_t byte0;
580 uint8_t byte1;
581 } backlight_transition_time_ms;
582};
583
584union dpcd_source_backlight_get {
585 struct {
586 uint32_t backlight_millinits_peak;
587 uint32_t backlight_millinits_avg;
588 } bytes;
589 uint8_t raw[8];
590};
591
592
593union edp_configuration_cap {
594 struct {
595 uint8_t ALT_SCRAMBLER_RESET:1;
596 uint8_t FRAMING_CHANGE:1;
597 uint8_t RESERVED:1;
598 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
599 uint8_t RESERVED2:4;
600 } bits;
601 uint8_t raw;
602};
603
604union dprx_feature {
605 struct {
606 uint8_t GTC_CAP:1;
607 uint8_t SST_SPLIT_SDP_CAP:1;
608 uint8_t AV_SYNC_CAP:1;
609 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1;
610 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1;
611 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1;
612 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1;
613 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1;
614 } bits;
615 uint8_t raw;
616};
617
618union training_aux_rd_interval {
619 struct {
620 uint8_t TRAINIG_AUX_RD_INTERVAL:7;
621 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1;
622 } bits;
623 uint8_t raw;
624};
625
626
627union test_request {
628 struct {
629 uint8_t LINK_TRAINING :1;
630 uint8_t LINK_TEST_PATTRN :1;
631 uint8_t EDID_READ :1;
632 uint8_t PHY_TEST_PATTERN :1;
633 uint8_t PHY_TEST_CHANNEL_CODING_TYPE :2;
634 uint8_t AUDIO_TEST_PATTERN :1;
635 uint8_t TEST_AUDIO_DISABLED_VIDEO :1;
636 } bits;
637 uint8_t raw;
638};
639
640union test_response {
641 struct {
642 uint8_t ACK :1;
643 uint8_t NO_ACK :1;
644 uint8_t EDID_CHECKSUM_WRITE:1;
645 uint8_t RESERVED :5;
646 } bits;
647 uint8_t raw;
648};
649
650union phy_test_pattern {
651 struct {
652
653 uint8_t PATTERN :7;
654 uint8_t RESERVED :1;
655 } bits;
656 uint8_t raw;
657};
658
659
660union compliance_test_state {
661 struct {
662 unsigned char STEREO_3D_RUNNING : 1;
663 unsigned char RESERVED : 7;
664 } bits;
665 unsigned char raw;
666};
667
668union link_test_pattern {
669 struct {
670
671 unsigned char PATTERN :2;
672 unsigned char RESERVED:6;
673 } bits;
674 unsigned char raw;
675};
676
677union test_misc {
678 struct dpcd_test_misc_bits {
679 unsigned char SYNC_CLOCK :1;
680
681 unsigned char CLR_FORMAT :2;
682
683 unsigned char DYN_RANGE :1;
684 unsigned char YCBCR_COEFS :1;
685
686 unsigned char BPC :3;
687 } bits;
688 unsigned char raw;
689};
690
691union audio_test_mode {
692 struct {
693 unsigned char sampling_rate :4;
694 unsigned char channel_count :4;
695 } bits;
696 unsigned char raw;
697};
698
699union audio_test_pattern_period {
700 struct {
701 unsigned char pattern_period :4;
702 unsigned char reserved :4;
703 } bits;
704 unsigned char raw;
705};
706
707struct audio_test_pattern_type {
708 unsigned char value;
709};
710
711struct dp_audio_test_data_flags {
712 uint8_t test_requested :1;
713 uint8_t disable_video :1;
714};
715
716struct dp_audio_test_data {
717
718 struct dp_audio_test_data_flags flags;
719 uint8_t sampling_rate;
720 uint8_t channel_count;
721 uint8_t pattern_type;
722 uint8_t pattern_period[8];
723};
724
725
726union dpcd_fec_capability {
727 struct {
728 uint8_t FEC_CAPABLE:1;
729 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
730 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
731 uint8_t BIT_ERROR_COUNT_CAPABLE:1;
732 uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1;
733 uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1;
734 uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1;
735 uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1;
736 } bits;
737 uint8_t raw;
738};
739
740
741struct dpcd_dsc_support {
742 uint8_t DSC_SUPPORT :1;
743 uint8_t DSC_PASSTHROUGH_SUPPORT :1;
744 uint8_t RESERVED :6;
745};
746
747struct dpcd_dsc_algorithm_revision {
748 uint8_t DSC_VERSION_MAJOR :4;
749 uint8_t DSC_VERSION_MINOR :4;
750};
751
752struct dpcd_dsc_rc_buffer_block_size {
753 uint8_t RC_BLOCK_BUFFER_SIZE :2;
754 uint8_t RESERVED :6;
755};
756
757struct dpcd_dsc_slice_capability1 {
758 uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1;
759 uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1;
760 uint8_t RESERVED :1;
761 uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1;
762 uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1;
763 uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1;
764 uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1;
765 uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1;
766};
767
768struct dpcd_dsc_line_buffer_bit_depth {
769 uint8_t LINE_BUFFER_BIT_DEPTH :4;
770 uint8_t RESERVED :4;
771};
772
773struct dpcd_dsc_block_prediction_support {
774 uint8_t BLOCK_PREDICTION_SUPPORT:1;
775 uint8_t RESERVED :7;
776};
777
778struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor {
779 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7;
780 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7;
781 uint8_t RESERVED :2;
782};
783
784struct dpcd_dsc_decoder_color_format_capabilities {
785 uint8_t RGB_SUPPORT :1;
786 uint8_t Y_CB_CR_444_SUPPORT :1;
787 uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1;
788 uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1;
789 uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1;
790 uint8_t RESERVED :3;
791};
792
793struct dpcd_dsc_decoder_color_depth_capabilities {
794 uint8_t RESERVED0 :1;
795 uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1;
796 uint8_t TEN_BITS_PER_COLOR_SUPPORT :1;
797 uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1;
798 uint8_t RESERVED1 :4;
799};
800
801struct dpcd_peak_dsc_throughput_dsc_sink {
802 uint8_t THROUGHPUT_MODE_0:4;
803 uint8_t THROUGHPUT_MODE_1:4;
804};
805
806struct dpcd_dsc_slice_capabilities_2 {
807 uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1;
808 uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1;
809 uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1;
810 uint8_t RESERVED :5;
811};
812
813struct dpcd_bits_per_pixel_increment{
814 uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3;
815 uint8_t RESERVED :5;
816};
817union dpcd_dsc_basic_capabilities {
818 struct {
819 struct dpcd_dsc_support dsc_support;
820 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision;
821 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size;
822 uint8_t dsc_rc_buffer_size;
823 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1;
824 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth;
825 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support;
826 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor;
827 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities;
828 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities;
829 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink;
830 uint8_t dsc_maximum_slice_width;
831 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2;
832 uint8_t reserved;
833 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment;
834 } fields;
835 uint8_t raw[16];
836};
837
838union dpcd_dsc_branch_decoder_capabilities {
839 struct {
840 uint8_t BRANCH_OVERALL_THROUGHPUT_0;
841 uint8_t BRANCH_OVERALL_THROUGHPUT_1;
842 uint8_t BRANCH_MAX_LINE_WIDTH;
843 } fields;
844 uint8_t raw[3];
845};
846
847struct dpcd_dsc_capabilities {
848 union dpcd_dsc_basic_capabilities dsc_basic_caps;
849 union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps;
850};
851
852
853struct psr_caps {
854 unsigned char psr_version;
855 unsigned int psr_rfb_setup_time;
856 bool psr_exit_link_training_required;
857 unsigned char edp_revision;
858 unsigned char support_ver;
859 bool su_granularity_required;
860 bool y_coordinate_required;
861 uint8_t su_y_granularity;
862 bool alpm_cap;
863 bool standby_support;
864 uint8_t rate_control_caps;
865 unsigned int psr_power_opt_flag;
866};
867
868
869#define DPCD_USB4_TOPOLOGY_ID_LEN 5
870
871
872union dp_tun_cap_support {
873 struct {
874 uint8_t dp_tunneling :1;
875 uint8_t rsvd :5;
876 uint8_t panel_replay_tun_opt :1;
877 uint8_t dpia_bw_alloc :1;
878 } bits;
879 uint8_t raw;
880};
881
882
883union dpia_info {
884 struct {
885 uint8_t dpia_num :5;
886 uint8_t rsvd :3;
887 } bits;
888 uint8_t raw;
889};
890
891
892struct dpcd_usb4_dp_tunneling_info {
893 union dp_tun_cap_support dp_tun_cap;
894 union dpia_info dpia_info;
895 uint8_t usb4_driver_id;
896 uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN];
897};
898
899#ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP
900#define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006
901#endif
902#ifndef DP_SINK_VIDEO_FALLBACK_FORMATS
903#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020
904#endif
905#ifndef DP_FEC_CAPABILITY_1
906#define DP_FEC_CAPABILITY_1 0x091
907#endif
908#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT
909#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
910#endif
911#ifndef DP_LINK_SQUARE_PATTERN
912#define DP_LINK_SQUARE_PATTERN 0x10F
913#endif
914#ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX
915#define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 0x110
916#endif
917#ifndef DP_DSC_CONFIGURATION
918#define DP_DSC_CONFIGURATION 0x161
919#endif
920#ifndef DP_PHY_SQUARE_PATTERN
921#define DP_PHY_SQUARE_PATTERN 0x249
922#endif
923#ifndef DP_128b_132b_SUPPORTED_LINK_RATES
924#define DP_128b_132b_SUPPORTED_LINK_RATES 0x2215
925#endif
926#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL
927#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL 0x2216
928#endif
929#ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX
930#define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 0x2217
931#endif
932#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0
933#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230
934#endif
935#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256
936#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250
937#endif
938#ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT
939#define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260
940#endif
941#ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0
942#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270
943#endif
944#ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK
945#define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
946#endif
947#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK
948#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
949#endif
950#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT
951#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
952#endif
953#ifndef DP_DSC_DECODER_COUNT_MASK
954#define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
955#endif
956#ifndef DP_DSC_DECODER_COUNT_SHIFT
957#define DP_DSC_DECODER_COUNT_SHIFT 5
958#endif
959#ifndef DP_MAIN_LINK_CHANNEL_CODING_SET
960#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
961#endif
962#ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER
963#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
964#endif
965#ifndef DP_PHY_REPEATER_128b_132b_RATES
966#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007
967#endif
968#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1
969#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022
970#endif
971#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION
972#define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
973
974#endif
975
976union dp_main_line_channel_coding_cap {
977 struct {
978 uint8_t DP_8b_10b_SUPPORTED :1;
979 uint8_t DP_128b_132b_SUPPORTED :1;
980 uint8_t RESERVED :6;
981 } bits;
982 uint8_t raw;
983};
984
985union dp_main_link_channel_coding_lttpr_cap {
986 struct {
987 uint8_t DP_128b_132b_SUPPORTED :1;
988 uint8_t RESERVED :7;
989 } bits;
990 uint8_t raw;
991};
992
993union dp_128b_132b_supported_link_rates {
994 struct {
995 uint8_t UHBR10 :1;
996 uint8_t UHBR20 :1;
997 uint8_t UHBR13_5:1;
998 uint8_t RESERVED:5;
999 } bits;
1000 uint8_t raw;
1001};
1002
1003union dp_128b_132b_supported_lttpr_link_rates {
1004 struct {
1005 uint8_t UHBR10 :1;
1006 uint8_t UHBR20 :1;
1007 uint8_t UHBR13_5:1;
1008 uint8_t RESERVED:5;
1009 } bits;
1010 uint8_t raw;
1011};
1012
1013union dp_sink_video_fallback_formats {
1014 struct {
1015 uint8_t dp_1024x768_60Hz_24bpp_support :1;
1016 uint8_t dp_1280x720_60Hz_24bpp_support :1;
1017 uint8_t dp_1920x1080_60Hz_24bpp_support :1;
1018 uint8_t RESERVED :5;
1019 } bits;
1020 uint8_t raw;
1021};
1022
1023union dp_fec_capability1 {
1024 struct {
1025 uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE :1;
1026 uint8_t RESERVED :7;
1027 } bits;
1028 uint8_t raw;
1029};
1030
1031union dp_cable_id {
1032 struct {
1033 uint8_t UHBR10_20_CAPABILITY :2;
1034 uint8_t UHBR13_5_CAPABILITY :1;
1035 uint8_t CABLE_TYPE :3;
1036 uint8_t RESERVED :2;
1037 } bits;
1038 uint8_t raw;
1039};
1040
1041struct dp_color_depth_caps {
1042 uint8_t support_6bpc :1;
1043 uint8_t support_8bpc :1;
1044 uint8_t support_10bpc :1;
1045 uint8_t support_12bpc :1;
1046 uint8_t support_16bpc :1;
1047 uint8_t RESERVED :3;
1048};
1049
1050struct dp_encoding_format_caps {
1051 uint8_t support_rgb :1;
1052 uint8_t support_ycbcr444:1;
1053 uint8_t support_ycbcr422:1;
1054 uint8_t support_ycbcr420:1;
1055 uint8_t RESERVED :4;
1056};
1057
1058union dp_dfp_cap_ext {
1059 struct {
1060 uint8_t supported;
1061 uint8_t max_pixel_rate_in_mps[2];
1062 uint8_t max_video_h_active_width[2];
1063 uint8_t max_video_v_active_height[2];
1064 struct dp_encoding_format_caps encoding_format_caps;
1065 struct dp_color_depth_caps rgb_color_depth_caps;
1066 struct dp_color_depth_caps ycbcr444_color_depth_caps;
1067 struct dp_color_depth_caps ycbcr422_color_depth_caps;
1068 struct dp_color_depth_caps ycbcr420_color_depth_caps;
1069 } fields;
1070 uint8_t raw[12];
1071};
1072
1073union dp_128b_132b_training_aux_rd_interval {
1074 struct {
1075 uint8_t VALUE :7;
1076 uint8_t UNIT :1;
1077 } bits;
1078 uint8_t raw;
1079};
1080
1081union edp_alpm_caps {
1082 struct {
1083 uint8_t AUX_WAKE_ALPM_CAP :1;
1084 uint8_t PM_STATE_2A_SUPPORT :1;
1085 uint8_t AUX_LESS_ALPM_CAP :1;
1086 uint8_t RESERVED :5;
1087 } bits;
1088 uint8_t raw;
1089};
1090
1091union edp_psr_dpcd_caps {
1092 struct {
1093 uint8_t LINK_TRAINING_ON_EXIT_NOT_REQUIRED :1;
1094 uint8_t PSR_SETUP_TIME :3;
1095 uint8_t Y_COORDINATE_REQUIRED :1;
1096 uint8_t SU_GRANULARITY_REQUIRED :1;
1097 uint8_t FRAME_SYNC_IS_NOT_NEEDED_FOR_SU :1;
1098 uint8_t RESERVED :1;
1099 } bits;
1100 uint8_t raw;
1101};
1102
1103struct edp_psr_info {
1104 uint8_t psr_version;
1105 union edp_psr_dpcd_caps psr_dpcd_caps;
1106 uint8_t psr2_su_y_granularity_cap;
1107 uint8_t force_psrsu_cap;
1108};
1109
1110#endif
1111
