LXR linux/drivers/gpu/drm/amd/display/include/grph_object

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef __DAL_GRPH_OBJECT_DEFS_H__
  27#define __DAL_GRPH_OBJECT_DEFS_H__
  28
  29#include "grph_object_id.h"
  30
  31/* ********************************************************************
  32 * ********************************************************************
  33 *
  34 *  These defines shared between All Graphics Objects
  35 *
  36 * ********************************************************************
  37 * ********************************************************************
  38 */
  39
  40#define MAX_CONNECTOR_NUMBER_PER_SLOT   (16)
  41#define MAX_BOARD_SLOTS                                 (4)
  42#define INVALID_CONNECTOR_INDEX                 ((unsigned int)(-1))
  43
  44/* HPD unit id - HW direct translation */
  45enum hpd_source_id {
  46        HPD_SOURCEID1 = 0,
  47        HPD_SOURCEID2,
  48        HPD_SOURCEID3,
  49        HPD_SOURCEID4,
  50        HPD_SOURCEID5,
  51        HPD_SOURCEID6,
  52
  53        HPD_SOURCEID_COUNT,
  54        HPD_SOURCEID_UNKNOWN
  55};
  56
  57/* DDC unit id - HW direct translation */
  58enum channel_id {
  59        CHANNEL_ID_UNKNOWN = 0,
  60        CHANNEL_ID_DDC1,
  61        CHANNEL_ID_DDC2,
  62        CHANNEL_ID_DDC3,
  63        CHANNEL_ID_DDC4,
  64        CHANNEL_ID_DDC5,
  65        CHANNEL_ID_DDC6,
  66        CHANNEL_ID_DDC_VGA,
  67        CHANNEL_ID_I2C_PAD,
  68        CHANNEL_ID_COUNT
  69};
  70
  71#define DECODE_CHANNEL_ID(ch_id) \
  72        (ch_id) == CHANNEL_ID_DDC1 ? "CHANNEL_ID_DDC1" : \
  73        (ch_id) == CHANNEL_ID_DDC2 ? "CHANNEL_ID_DDC2" : \
  74        (ch_id) == CHANNEL_ID_DDC3 ? "CHANNEL_ID_DDC3" : \
  75        (ch_id) == CHANNEL_ID_DDC4 ? "CHANNEL_ID_DDC4" : \
  76        (ch_id) == CHANNEL_ID_DDC5 ? "CHANNEL_ID_DDC5" : \
  77        (ch_id) == CHANNEL_ID_DDC6 ? "CHANNEL_ID_DDC6" : \
  78        (ch_id) == CHANNEL_ID_DDC_VGA ? "CHANNEL_ID_DDC_VGA" : \
  79        (ch_id) == CHANNEL_ID_I2C_PAD ? "CHANNEL_ID_I2C_PAD" : "Invalid"
  80
  81enum transmitter {
  82        TRANSMITTER_UNKNOWN = (-1L),
  83        TRANSMITTER_UNIPHY_A,
  84        TRANSMITTER_UNIPHY_B,
  85        TRANSMITTER_UNIPHY_C,
  86        TRANSMITTER_UNIPHY_D,
  87        TRANSMITTER_UNIPHY_E,
  88        TRANSMITTER_UNIPHY_F,
  89        TRANSMITTER_NUTMEG_CRT,
  90        TRANSMITTER_TRAVIS_CRT,
  91        TRANSMITTER_TRAVIS_LCD,
  92        TRANSMITTER_UNIPHY_G,
  93        TRANSMITTER_COUNT
  94};
  95
  96/* Generic source of the synchronisation input/output signal */
  97/* Can be used for flow control, stereo sync, timing sync, frame sync, etc */
  98enum sync_source {
  99        SYNC_SOURCE_NONE = 0,
 100
 101        /* Source based on controllers */
 102        SYNC_SOURCE_CONTROLLER0,
 103        SYNC_SOURCE_CONTROLLER1,
 104        SYNC_SOURCE_CONTROLLER2,
 105        SYNC_SOURCE_CONTROLLER3,
 106        SYNC_SOURCE_CONTROLLER4,
 107        SYNC_SOURCE_CONTROLLER5,
 108
 109        /* Source based on GSL group */
 110        SYNC_SOURCE_GSL_GROUP0,
 111        SYNC_SOURCE_GSL_GROUP1,
 112        SYNC_SOURCE_GSL_GROUP2,
 113
 114        /* Source based on GSL IOs */
 115        /* These IOs normally used as GSL input/output */
 116        SYNC_SOURCE_GSL_IO_FIRST,
 117        SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK = SYNC_SOURCE_GSL_IO_FIRST,
 118        SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC,
 119        SYNC_SOURCE_GSL_IO_SWAPLOCK_A,
 120        SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
 121        SYNC_SOURCE_GSL_IO_LAST = SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
 122
 123        /* Source based on regular IOs */
 124        SYNC_SOURCE_IO_FIRST,
 125        SYNC_SOURCE_IO_GENERIC_A = SYNC_SOURCE_IO_FIRST,
 126        SYNC_SOURCE_IO_GENERIC_B,
 127        SYNC_SOURCE_IO_GENERIC_C,
 128        SYNC_SOURCE_IO_GENERIC_D,
 129        SYNC_SOURCE_IO_GENERIC_E,
 130        SYNC_SOURCE_IO_GENERIC_F,
 131        SYNC_SOURCE_IO_HPD1,
 132        SYNC_SOURCE_IO_HPD2,
 133        SYNC_SOURCE_IO_HSYNC_A,
 134        SYNC_SOURCE_IO_VSYNC_A,
 135        SYNC_SOURCE_IO_HSYNC_B,
 136        SYNC_SOURCE_IO_VSYNC_B,
 137        SYNC_SOURCE_IO_LAST = SYNC_SOURCE_IO_VSYNC_B,
 138
 139        /* Misc. flow control sources */
 140        SYNC_SOURCE_DUAL_GPU_PIN
 141};
 142
 143enum tx_ffe_id {
 144        TX_FFE0 = 0,
 145        TX_FFE1,
 146        TX_FFE2,
 147        TX_FFE3,
 148        TX_FFE_DeEmphasis_Only,
 149        TX_FFE_PreShoot_Only,
 150        TX_FFE_No_FFE,
 151};
 152
 153/* connector sizes in millimeters - from BiosParserTypes.hpp */
 154#define CONNECTOR_SIZE_DVI                      40
 155#define CONNECTOR_SIZE_VGA                      32
 156#define CONNECTOR_SIZE_HDMI                     16
 157#define CONNECTOR_SIZE_DP                       16
 158#define CONNECTOR_SIZE_MINI_DP                  9
 159#define CONNECTOR_SIZE_UNKNOWN                  30
 160
 161enum connector_layout_type {
 162        CONNECTOR_LAYOUT_TYPE_UNKNOWN,
 163        CONNECTOR_LAYOUT_TYPE_DVI_D,
 164        CONNECTOR_LAYOUT_TYPE_DVI_I,
 165        CONNECTOR_LAYOUT_TYPE_VGA,
 166        CONNECTOR_LAYOUT_TYPE_HDMI,
 167        CONNECTOR_LAYOUT_TYPE_DP,
 168        CONNECTOR_LAYOUT_TYPE_MINI_DP,
 169};
 170struct connector_layout_info {
 171        struct graphics_object_id connector_id;
 172        enum connector_layout_type connector_type;
 173        unsigned int length;
 174        unsigned int position;  /* offset in mm from right side of the board */
 175};
 176
 177/* length and width in mm */
 178struct slot_layout_info {
 179        unsigned int length;
 180        unsigned int width;
 181        unsigned int num_of_connectors;
 182        struct connector_layout_info connectors[MAX_CONNECTOR_NUMBER_PER_SLOT];
 183};
 184
 185struct board_layout_info {
 186        unsigned int num_of_slots;
 187
 188        /* indicates valid information in bracket layout structure. */
 189        unsigned int is_number_of_slots_valid : 1;
 190        unsigned int is_slots_size_valid : 1;
 191        unsigned int is_connector_offsets_valid : 1;
 192        unsigned int is_connector_lengths_valid : 1;
 193
 194        struct slot_layout_info slots[MAX_BOARD_SLOTS];
 195};
 196#endif
 197