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23#ifndef __AMDGPU_DPM_H__
24#define __AMDGPU_DPM_H__
25
26
27enum gfx_change_state {
28 sGpuChangeState_D0Entry = 1,
29 sGpuChangeState_D3Entry,
30};
31
32enum amdgpu_int_thermal_type {
33 THERMAL_TYPE_NONE,
34 THERMAL_TYPE_EXTERNAL,
35 THERMAL_TYPE_EXTERNAL_GPIO,
36 THERMAL_TYPE_RV6XX,
37 THERMAL_TYPE_RV770,
38 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
39 THERMAL_TYPE_EVERGREEN,
40 THERMAL_TYPE_SUMO,
41 THERMAL_TYPE_NI,
42 THERMAL_TYPE_SI,
43 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
44 THERMAL_TYPE_CI,
45 THERMAL_TYPE_KV,
46};
47
48struct amdgpu_ps {
49 u32 caps;
50 u32 class;
51 u32 class2;
52
53 u32 vclk;
54 u32 dclk;
55
56 u32 evclk;
57 u32 ecclk;
58 bool vce_active;
59 enum amd_vce_level vce_level;
60
61 void *ps_priv;
62};
63
64struct amdgpu_dpm_thermal {
65
66 struct work_struct work;
67
68 int min_temp;
69
70 int max_temp;
71
72 int max_edge_emergency_temp;
73
74 int min_hotspot_temp;
75
76 int max_hotspot_crit_temp;
77
78 int max_hotspot_emergency_temp;
79
80 int min_mem_temp;
81
82 int max_mem_crit_temp;
83
84 int max_mem_emergency_temp;
85
86 bool high_to_low;
87
88 struct amdgpu_irq_src irq;
89};
90
91struct amdgpu_clock_and_voltage_limits {
92 u32 sclk;
93 u32 mclk;
94 u16 vddc;
95 u16 vddci;
96};
97
98struct amdgpu_clock_array {
99 u32 count;
100 u32 *values;
101};
102
103struct amdgpu_clock_voltage_dependency_entry {
104 u32 clk;
105 u16 v;
106};
107
108struct amdgpu_clock_voltage_dependency_table {
109 u32 count;
110 struct amdgpu_clock_voltage_dependency_entry *entries;
111};
112
113union amdgpu_cac_leakage_entry {
114 struct {
115 u16 vddc;
116 u32 leakage;
117 };
118 struct {
119 u16 vddc1;
120 u16 vddc2;
121 u16 vddc3;
122 };
123};
124
125struct amdgpu_cac_leakage_table {
126 u32 count;
127 union amdgpu_cac_leakage_entry *entries;
128};
129
130struct amdgpu_phase_shedding_limits_entry {
131 u16 voltage;
132 u32 sclk;
133 u32 mclk;
134};
135
136struct amdgpu_phase_shedding_limits_table {
137 u32 count;
138 struct amdgpu_phase_shedding_limits_entry *entries;
139};
140
141struct amdgpu_uvd_clock_voltage_dependency_entry {
142 u32 vclk;
143 u32 dclk;
144 u16 v;
145};
146
147struct amdgpu_uvd_clock_voltage_dependency_table {
148 u8 count;
149 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
150};
151
152struct amdgpu_vce_clock_voltage_dependency_entry {
153 u32 ecclk;
154 u32 evclk;
155 u16 v;
156};
157
158struct amdgpu_vce_clock_voltage_dependency_table {
159 u8 count;
160 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
161};
162
163struct amdgpu_ppm_table {
164 u8 ppm_design;
165 u16 cpu_core_number;
166 u32 platform_tdp;
167 u32 small_ac_platform_tdp;
168 u32 platform_tdc;
169 u32 small_ac_platform_tdc;
170 u32 apu_tdp;
171 u32 dgpu_tdp;
172 u32 dgpu_ulv_power;
173 u32 tj_max;
174};
175
176struct amdgpu_cac_tdp_table {
177 u16 tdp;
178 u16 configurable_tdp;
179 u16 tdc;
180 u16 battery_power_limit;
181 u16 small_power_limit;
182 u16 low_cac_leakage;
183 u16 high_cac_leakage;
184 u16 maximum_power_delivery_limit;
185};
186
187struct amdgpu_dpm_dynamic_state {
188 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
189 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
190 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
191 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
192 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
193 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
194 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
195 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
196 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
197 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
198 struct amdgpu_clock_array valid_sclk_values;
199 struct amdgpu_clock_array valid_mclk_values;
200 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
201 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
202 u32 mclk_sclk_ratio;
203 u32 sclk_mclk_delta;
204 u16 vddc_vddci_delta;
205 u16 min_vddc_for_pcie_gen2;
206 struct amdgpu_cac_leakage_table cac_leakage_table;
207 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
208 struct amdgpu_ppm_table *ppm_table;
209 struct amdgpu_cac_tdp_table *cac_tdp_table;
210};
211
212struct amdgpu_dpm_fan {
213 u16 t_min;
214 u16 t_med;
215 u16 t_high;
216 u16 pwm_min;
217 u16 pwm_med;
218 u16 pwm_high;
219 u8 t_hyst;
220 u32 cycle_delay;
221 u16 t_max;
222 u8 control_mode;
223 u16 default_max_fan_pwm;
224 u16 default_fan_output_sensitivity;
225 u16 fan_output_sensitivity;
226 bool ucode_fan_control;
227};
228
229struct amdgpu_dpm {
230 struct amdgpu_ps *ps;
231
232 int num_ps;
233
234 struct amdgpu_ps *current_ps;
235
236 struct amdgpu_ps *requested_ps;
237
238 struct amdgpu_ps *boot_ps;
239
240 struct amdgpu_ps *uvd_ps;
241
242 u32 num_of_vce_states;
243 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
244 enum amd_vce_level vce_level;
245 enum amd_pm_state_type state;
246 enum amd_pm_state_type user_state;
247 enum amd_pm_state_type last_state;
248 enum amd_pm_state_type last_user_state;
249 u32 platform_caps;
250 u32 voltage_response_time;
251 u32 backbias_response_time;
252 void *priv;
253 u32 new_active_crtcs;
254 int new_active_crtc_count;
255 u32 current_active_crtcs;
256 int current_active_crtc_count;
257 struct amdgpu_dpm_dynamic_state dyn_state;
258 struct amdgpu_dpm_fan fan;
259 u32 tdp_limit;
260 u32 near_tdp_limit;
261 u32 near_tdp_limit_adjusted;
262 u32 sq_ramping_threshold;
263 u32 cac_leakage;
264 u16 tdp_od_limit;
265 u32 tdp_adjustment;
266 u16 load_line_slope;
267 bool power_control;
268
269 bool thermal_active;
270 bool uvd_active;
271 bool vce_active;
272
273 struct amdgpu_dpm_thermal thermal;
274
275 enum amd_dpm_forced_level forced_level;
276};
277
278enum ip_power_state {
279 POWER_STATE_UNKNOWN,
280 POWER_STATE_ON,
281 POWER_STATE_OFF,
282};
283
284
285#define SMU_DEBUG_HALT_ON_ERROR 0x1
286
287#define MAX_SMU_I2C_BUSES 2
288
289struct amdgpu_smu_i2c_bus {
290 struct i2c_adapter adapter;
291 struct amdgpu_device *adev;
292 int port;
293 struct mutex mutex;
294};
295
296struct config_table_setting
297{
298 uint16_t gfxclk_average_tau;
299 uint16_t socclk_average_tau;
300 uint16_t uclk_average_tau;
301 uint16_t gfx_activity_average_tau;
302 uint16_t mem_activity_average_tau;
303 uint16_t socket_power_average_tau;
304 uint16_t apu_socket_power_average_tau;
305 uint16_t fclk_average_tau;
306};
307
308struct amdgpu_pm {
309 struct mutex mutex;
310 u32 current_sclk;
311 u32 current_mclk;
312 u32 default_sclk;
313 u32 default_mclk;
314 struct amdgpu_i2c_chan *i2c_bus;
315 bool bus_locked;
316
317 enum amdgpu_int_thermal_type int_thermal_type;
318 struct device *int_hwmon_dev;
319
320 bool no_fan;
321 u8 fan_pulses_per_revolution;
322 u8 fan_min_rpm;
323 u8 fan_max_rpm;
324
325 bool dpm_enabled;
326 bool sysfs_initialized;
327 struct amdgpu_dpm dpm;
328 const struct firmware *fw;
329 uint32_t fw_version;
330 uint32_t pcie_gen_mask;
331 uint32_t pcie_mlw_mask;
332 struct amd_pp_display_configuration pm_display_cfg;
333 uint32_t smu_prv_buffer_size;
334 struct amdgpu_bo *smu_prv_buffer;
335 bool ac_power;
336
337 uint32_t pp_feature;
338
339
340 struct amdgpu_smu_i2c_bus smu_i2c[MAX_SMU_I2C_BUSES];
341 struct i2c_adapter *ras_eeprom_i2c_bus;
342 struct i2c_adapter *fru_eeprom_i2c_bus;
343 struct list_head pm_attr_list;
344
345 atomic_t pwr_state[AMD_IP_BLOCK_TYPE_NUM];
346
347
348
349
350 uint32_t smu_debug_mask;
351
352 bool pp_force_state_enabled;
353
354 struct mutex stable_pstate_ctx_lock;
355 struct amdgpu_ctx *stable_pstate_ctx;
356
357 struct config_table_setting config_table;
358};
359
360int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
361 void *data, uint32_t *size);
362
363int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
364 uint32_t block_type, bool gate);
365
366extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low);
367
368extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low);
369
370int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
371 uint32_t pstate);
372
373int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,
374 enum PP_SMC_POWER_PROFILE type,
375 bool en);
376
377int amdgpu_dpm_baco_reset(struct amdgpu_device *adev);
378
379int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev);
380
381bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev);
382
383bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev);
384int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev);
385
386int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
387 enum pp_mp1_state mp1_state);
388
389int amdgpu_dpm_baco_exit(struct amdgpu_device *adev);
390
391int amdgpu_dpm_baco_enter(struct amdgpu_device *adev);
392
393int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev,
394 uint32_t cstate);
395
396int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en);
397
398int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev);
399
400int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev,
401 uint32_t msg_id);
402
403int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev,
404 bool acquire);
405
406void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
407
408void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev);
409void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
410void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
411void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
412int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version);
413int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable);
414int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size);
415int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size);
416int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
417 enum pp_clock_type type,
418 uint32_t *min,
419 uint32_t *max);
420int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev,
421 enum pp_clock_type type,
422 uint32_t min,
423 uint32_t max);
424int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev);
425int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,
426 uint64_t event_arg);
427int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
428uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev);
429void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev,
430 enum gfx_change_state state);
431int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev,
432 void *umc_ecc);
433struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev,
434 uint32_t idx);
435void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, enum amd_pm_state_type *state);
436void amdgpu_dpm_set_power_state(struct amdgpu_device *adev,
437 enum amd_pm_state_type state);
438enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev);
439int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev,
440 enum amd_dpm_forced_level level);
441int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev,
442 struct pp_states_info *states);
443int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev,
444 enum amd_pp_task task_id,
445 enum amd_pm_state_type *user_state);
446int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table);
447int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev,
448 uint32_t type,
449 long *input,
450 uint32_t size);
451int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev,
452 uint32_t type,
453 long *input,
454 uint32_t size);
455int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev,
456 enum pp_clock_type type,
457 char *buf);
458int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev,
459 enum pp_clock_type type,
460 char *buf,
461 int *offset);
462int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev,
463 uint64_t ppfeature_masks);
464int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf);
465int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev,
466 enum pp_clock_type type,
467 uint32_t mask);
468int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev);
469int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value);
470int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev);
471int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value);
472int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev,
473 char *buf);
474int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev,
475 long *input, uint32_t size);
476int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table);
477int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev,
478 uint32_t *fan_mode);
479int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev,
480 uint32_t speed);
481int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev,
482 uint32_t *speed);
483int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev,
484 uint32_t *speed);
485int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev,
486 uint32_t speed);
487int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev,
488 uint32_t mode);
489int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev,
490 uint32_t *limit,
491 enum pp_power_limit_level pp_limit_level,
492 enum pp_power_type power_type);
493int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev,
494 uint32_t limit);
495int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev);
496int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
497 struct seq_file *m);
498int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev,
499 void **addr,
500 size_t *size);
501int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev);
502int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev,
503 const char *buf,
504 size_t size);
505int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev);
506void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev);
507int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev,
508 const struct amd_pp_display_configuration *input);
509int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev,
510 enum amd_pp_clock_type type,
511 struct amd_pp_clocks *clocks);
512int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev,
513 struct amd_pp_simple_clock_info *clocks);
514int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev,
515 enum amd_pp_clock_type type,
516 struct pp_clock_levels_with_latency *clocks);
517int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev,
518 enum amd_pp_clock_type type,
519 struct pp_clock_levels_with_voltage *clocks);
520int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev,
521 void *clock_ranges);
522int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev,
523 struct pp_display_clock_request *clock);
524int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev,
525 struct amd_pp_clock_info *clocks);
526void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev);
527int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev,
528 uint32_t count);
529int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev,
530 uint32_t clock);
531void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev,
532 uint32_t clock);
533void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev,
534 uint32_t clock);
535int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev,
536 bool disable_memory_clock_switch);
537int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev,
538 struct pp_smu_nv_clock_table *max_clocks);
539enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev,
540 unsigned int *clock_values_in_khz,
541 unsigned int *num_states);
542int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev,
543 struct dpm_clocks *clock_table);
544#endif
545
