/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef _I915_REG_H_
#define _I915_REG_H_

#include "i915_reg_defs.h"

/**
 * DOC: The i915 register macro definition style guide
 *
 * Follow the style described here for new macros, and while changing existing
 * macros. Do **not** mass change existing definitions just to update the style.
 *
 * File Layout
 * ~~~~~~~~~~~
 *
 * Keep helper macros near the top. For example, _PIPE() and friends.
 *
 * Prefix macros that generally should not be used outside of this file with
 * underscore '_'. For example, _PIPE() and friends, single instances of
 * registers that are defined solely for the use by function-like macros.
 *
 * Avoid using the underscore prefixed macros outside of this file. There are
 * exceptions, but keep them to a minimum.
 *
 * There are two basic types of register definitions: Single registers and
 * register groups. Register groups are registers which have two or more
 * instances, for example one per pipe, port, transcoder, etc. Register groups
 * should be defined using function-like macros.
 *
 * For single registers, define the register offset first, followed by register
 * contents.
 *
 * For register groups, define the register instance offsets first, prefixed
 * with underscore, followed by a function-like macro choosing the right
 * instance based on the parameter, followed by register contents.
 *
 * Define the register contents (i.e. bit and bit field macros) from most
 * significant to least significant bit. Indent the register content macros
 * using two extra spaces between ``#define`` and the macro name.
 *
 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
 * shifted in place, so they can be directly OR'd together. For convenience,
 * function-like macros may be used to define bit fields, but do note that the
 * macros may be needed to read as well as write the register contents.
 *
 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
 *
 * Group the register and its contents together without blank lines, separate
 * from other registers and their contents with one blank line.
 *
 * Indent macro values from macro names using TABs. Align values vertically. Use
 * braces in macro values as needed to avoid unintended precedence after macro
 * substitution. Use spaces in macro values according to kernel coding
 * style. Use lower case in hexadecimal values.
 *
 * Naming
 * ~~~~~~
 *
 * Try to name registers according to the specs. If the register name changes in
 * the specs from platform to another, stick to the original name.
 *
 * Try to re-use existing register macro definitions. Only add new macros for
 * new register offsets, or when the register contents have changed enough to
 * warrant a full redefinition.
 *
 * When a register macro changes for a new platform, prefix the new macro using
 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
 * prefix signifies the start platform/generation using the register.
 *
 * When a bit (field) macro changes or gets added for a new platform, while
 * retaining the existing register macro, add a platform acronym or generation
 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
 *
 * Examples
 * ~~~~~~~~
 *
 * (Note that the values in the example are indented using spaces instead of
 * TABs to avoid misalignment in generated documentation. Use TABs in the
 * definitions.)::
 *
 *  #define _FOO_A                      0xf000
 *  #define _FOO_B                      0xf001
 *  #define FOO(pipe)                   _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
 *  #define   FOO_ENABLE                REG_BIT(31)
 *  #define   FOO_MODE_MASK             REG_GENMASK(19, 16)
 *  #define   FOO_MODE_BAR              REG_FIELD_PREP(FOO_MODE_MASK, 0)
 *  #define   FOO_MODE_BAZ              REG_FIELD_PREP(FOO_MODE_MASK, 1)
 *  #define   FOO_MODE_QUX_SNB          REG_FIELD_PREP(FOO_MODE_MASK, 2)
 *
 *  #define BAR                         _MMIO(0xb000)
 *  #define GEN8_BAR                    _MMIO(0xb888)
 */

#define DISPLAY_MMIO_BASE(dev_priv)     (INTEL_INFO(dev_priv)->display_mmio_offset)

/*
 * Given the first two numbers __a and __b of arbitrarily many evenly spaced
 * numbers, pick the 0-based __index'th value.
 *
 * Always prefer this over _PICK() if the numbers are evenly spaced.
 */
#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))

/*
 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
 *
 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
 */
#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])

/*
 * Named helper wrappers around _PICK_EVEN() and _PICK().
 */
#define _PIPE(pipe, a, b)               _PICK_EVEN(pipe, a, b)
#define _PLANE(plane, a, b)             _PICK_EVEN(plane, a, b)
#define _TRANS(tran, a, b)              _PICK_EVEN(tran, a, b)
#define _PORT(port, a, b)               _PICK_EVEN(port, a, b)
#define _PLL(pll, a, b)                 _PICK_EVEN(pll, a, b)
#define _PHY(phy, a, b)                 _PICK_EVEN(phy, a, b)

#define _MMIO_PIPE(pipe, a, b)          _MMIO(_PIPE(pipe, a, b))
#define _MMIO_PLANE(plane, a, b)        _MMIO(_PLANE(plane, a, b))
#define _MMIO_TRANS(tran, a, b)         _MMIO(_TRANS(tran, a, b))
#define _MMIO_PORT(port, a, b)          _MMIO(_PORT(port, a, b))
#define _MMIO_PLL(pll, a, b)            _MMIO(_PLL(pll, a, b))
#define _MMIO_PHY(phy, a, b)            _MMIO(_PHY(phy, a, b))

#define _PHY3(phy, ...)                 _PICK(phy, __VA_ARGS__)

#define _MMIO_PIPE3(pipe, a, b, c)      _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PORT3(pipe, a, b, c)      _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c)        _MMIO(_PHY3(phy, a, b, c))
#define _MMIO_PLL3(pll, ...)            _MMIO(_PICK(pll, __VA_ARGS__))


/*
 * Device info offset array based helpers for groups of registers with unevenly
 * spaced base offsets.
 */
#define _MMIO_PIPE2(pipe, reg)          _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
                                              INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
                                              DISPLAY_MMIO_BASE(dev_priv))
#define _TRANS2(tran, reg)              (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
                                         INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
                                         DISPLAY_MMIO_BASE(dev_priv))
#define _MMIO_TRANS2(tran, reg)         _MMIO(_TRANS2(tran, reg))
#define _CURSOR2(pipe, reg)             _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
                                              INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
                                              DISPLAY_MMIO_BASE(dev_priv))

#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
#define _MASKED_FIELD(mask, value) ({                                      \
        if (__builtin_constant_p(mask))                                    \
                BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
        if (__builtin_constant_p(value))                                   \
                BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
        if (__builtin_constant_p(mask) && __builtin_constant_p(value))     \
                BUILD_BUG_ON_MSG((value) & ~(mask),                        \
                                 "Incorrect value for mask");              \
        __MASKED_FIELD(mask, value); })
#define _MASKED_BIT_ENABLE(a)   ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
#define _MASKED_BIT_DISABLE(a)  (_MASKED_FIELD((a), 0))

#define GU_CNTL                         _MMIO(0x101010)
#define   LMEM_INIT                     REG_BIT(7)

#define GEN6_STOLEN_RESERVED            _MMIO(0x1082C0)
#define GEN6_STOLEN_RESERVED_ADDR_MASK  (0xFFF << 20)
#define GEN7_STOLEN_RESERVED_ADDR_MASK  (0x3FFF << 18)
#define GEN6_STOLEN_RESERVED_SIZE_MASK  (3 << 4)
#define GEN6_STOLEN_RESERVED_1M         (0 << 4)
#define GEN6_STOLEN_RESERVED_512K       (1 << 4)
#define GEN6_STOLEN_RESERVED_256K       (2 << 4)
#define GEN6_STOLEN_RESERVED_128K       (3 << 4)
#define GEN7_STOLEN_RESERVED_SIZE_MASK  (1 << 5)
#define GEN7_STOLEN_RESERVED_1M         (0 << 5)
#define GEN7_STOLEN_RESERVED_256K       (1 << 5)
#define GEN8_STOLEN_RESERVED_SIZE_MASK  (3 << 7)
#define GEN8_STOLEN_RESERVED_1M         (0 << 7)
#define GEN8_STOLEN_RESERVED_2M         (1 << 7)
#define GEN8_STOLEN_RESERVED_4M         (2 << 7)
#define GEN8_STOLEN_RESERVED_8M         (3 << 7)
#define GEN6_STOLEN_RESERVED_ENABLE     (1 << 0)
#define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)

#define _VGA_MSR_WRITE _MMIO(0x3c2)

#define _GEN7_PIPEA_DE_LOAD_SL  0x70068
#define _GEN7_PIPEB_DE_LOAD_SL  0x71068
#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)

/*
 * Reset registers
 */
#define DEBUG_RESET_I830                _MMIO(0x6070)
#define  DEBUG_RESET_FULL               (1 << 7)
#define  DEBUG_RESET_RENDER             (1 << 8)
#define  DEBUG_RESET_DISPLAY            (1 << 9)

/*
 * IOSF sideband
 */
#define VLV_IOSF_DOORBELL_REQ                   _MMIO(VLV_DISPLAY_BASE + 0x2100)
#define   IOSF_DEVFN_SHIFT                      24
#define   IOSF_OPCODE_SHIFT                     16
#define   IOSF_PORT_SHIFT                       8
#define   IOSF_BYTE_ENABLES_SHIFT               4
#define   IOSF_BAR_SHIFT                        1
#define   IOSF_SB_BUSY                          (1 << 0)
#define   IOSF_PORT_BUNIT                       0x03
#define   IOSF_PORT_PUNIT                       0x04
#define   IOSF_PORT_NC                          0x11
#define   IOSF_PORT_DPIO                        0x12
#define   IOSF_PORT_GPIO_NC                     0x13
#define   IOSF_PORT_CCK                         0x14
#define   IOSF_PORT_DPIO_2                      0x1a
#define   IOSF_PORT_FLISDSI                     0x1b
#define   IOSF_PORT_GPIO_SC                     0x48
#define   IOSF_PORT_GPIO_SUS                    0xa8
#define   IOSF_PORT_CCU                         0xa9
#define   CHV_IOSF_PORT_GPIO_N                  0x13
#define   CHV_IOSF_PORT_GPIO_SE                 0x48
#define   CHV_IOSF_PORT_GPIO_E                  0xa8
#define   CHV_IOSF_PORT_GPIO_SW                 0xb2
#define VLV_IOSF_DATA                           _MMIO(VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR                           _MMIO(VLV_DISPLAY_BASE + 0x2108)

/* DPIO registers */
#define DPIO_DEVFN                      0

#define DPIO_CTL                        _MMIO(VLV_DISPLAY_BASE + 0x2110)
#define  DPIO_MODSEL1                   (1 << 3) /* if ref clk b == 27 */
#define  DPIO_MODSEL0                   (1 << 2) /* if ref clk a == 27 */
#define  DPIO_SFR_BYPASS                (1 << 1)
#define  DPIO_CMNRST                    (1 << 0)

#define DPIO_PHY(pipe)                  ((pipe) >> 1)

/*
 * Per pipe/PLL DPIO regs
 */
#define _VLV_PLL_DW3_CH0                0x800c
#define   DPIO_POST_DIV_SHIFT           (28) /* 3 bits */
#define   DPIO_POST_DIV_DAC             0
#define   DPIO_POST_DIV_HDMIDP          1 /* DAC 225-400M rate */
#define   DPIO_POST_DIV_LVDS1           2
#define   DPIO_POST_DIV_LVDS2           3
#define   DPIO_K_SHIFT                  (24) /* 4 bits */
#define   DPIO_P1_SHIFT                 (21) /* 3 bits */
#define   DPIO_P2_SHIFT                 (16) /* 5 bits */
#define   DPIO_N_SHIFT                  (12) /* 4 bits */
#define   DPIO_ENABLE_CALIBRATION       (1 << 11)
#define   DPIO_M1DIV_SHIFT              (8) /* 3 bits */
#define   DPIO_M2DIV_MASK               0xff
#define _VLV_PLL_DW3_CH1                0x802c
#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)

#define _VLV_PLL_DW5_CH0                0x8014
#define   DPIO_REFSEL_OVERRIDE          27
#define   DPIO_PLL_MODESEL_SHIFT        24 /* 3 bits */
#define   DPIO_BIAS_CURRENT_CTL_SHIFT   21 /* 3 bits, always 0x7 */
#define   DPIO_PLL_REFCLK_SEL_SHIFT     16 /* 2 bits */
#define   DPIO_PLL_REFCLK_SEL_MASK      3
#define   DPIO_DRIVER_CTL_SHIFT         12 /* always set to 0x8 */
#define   DPIO_CLK_BIAS_CTL_SHIFT       8 /* always set to 0x5 */
#define _VLV_PLL_DW5_CH1                0x8034
#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)

#define _VLV_PLL_DW7_CH0                0x801c
#define _VLV_PLL_DW7_CH1                0x803c
#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)

#define _VLV_PLL_DW8_CH0                0x8040
#define _VLV_PLL_DW8_CH1                0x8060
#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)

#define VLV_PLL_DW9_BCAST               0xc044
#define _VLV_PLL_DW9_CH0                0x8044
#define _VLV_PLL_DW9_CH1                0x8064
#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)

#define _VLV_PLL_DW10_CH0               0x8048
#define _VLV_PLL_DW10_CH1               0x8068
#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)

#define _VLV_PLL_DW11_CH0               0x804c
#define _VLV_PLL_DW11_CH1               0x806c
#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)

/* Spec for ref block start counts at DW10 */
#define VLV_REF_DW13                    0x80ac

#define VLV_CMN_DW0                     0x8100

/*
 * Per DDI channel DPIO regs
 */

#define _VLV_PCS_DW0_CH0                0x8200
#define _VLV_PCS_DW0_CH1                0x8400
#define   DPIO_PCS_TX_LANE2_RESET       (1 << 16)
#define   DPIO_PCS_TX_LANE1_RESET       (1 << 7)
#define   DPIO_LEFT_TXFIFO_RST_MASTER2  (1 << 4)
#define   DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)

#define _VLV_PCS01_DW0_CH0              0x200
#define _VLV_PCS23_DW0_CH0              0x400
#define _VLV_PCS01_DW0_CH1              0x2600
#define _VLV_PCS23_DW0_CH1              0x2800
#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)

#define _VLV_PCS_DW1_CH0                0x8204
#define _VLV_PCS_DW1_CH1                0x8404
#define   CHV_PCS_REQ_SOFTRESET_EN      (1 << 23)
#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
#define   DPIO_PCS_CLK_DATAWIDTH_SHIFT  (6)
#define   DPIO_PCS_CLK_SOFT_RESET       (1 << 5)
#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)

#define _VLV_PCS01_DW1_CH0              0x204
#define _VLV_PCS23_DW1_CH0              0x404
#define _VLV_PCS01_DW1_CH1              0x2604
#define _VLV_PCS23_DW1_CH1              0x2804
#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)

#define _VLV_PCS_DW8_CH0                0x8220
#define _VLV_PCS_DW8_CH1                0x8420
#define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE        (1 << 20)
#define   CHV_PCS_USEDCLKCHANNEL                (1 << 21)
#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)

#define _VLV_PCS01_DW8_CH0              0x0220
#define _VLV_PCS23_DW8_CH0              0x0420
#define _VLV_PCS01_DW8_CH1              0x2620
#define _VLV_PCS23_DW8_CH1              0x2820
#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)

#define _VLV_PCS_DW9_CH0                0x8224
#define _VLV_PCS_DW9_CH1                0x8424
#define   DPIO_PCS_TX2MARGIN_MASK       (0x7 << 13)
#define   DPIO_PCS_TX2MARGIN_000        (0 << 13)
#define   DPIO_PCS_TX2MARGIN_101        (1 << 13)
#define   DPIO_PCS_TX1MARGIN_MASK       (0x7 << 10)
#define   DPIO_PCS_TX1MARGIN_000        (0 << 10)
#define   DPIO_PCS_TX1MARGIN_101        (1 << 10)
#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)

#define _VLV_PCS01_DW9_CH0              0x224
#define _VLV_PCS23_DW9_CH0              0x424
#define _VLV_PCS01_DW9_CH1              0x2624
#define _VLV_PCS23_DW9_CH1              0x2824
#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)

#define _CHV_PCS_DW10_CH0               0x8228
#define _CHV_PCS_DW10_CH1               0x8428
#define   DPIO_PCS_SWING_CALC_TX0_TX2   (1 << 30)
#define   DPIO_PCS_SWING_CALC_TX1_TX3   (1 << 31)
#define   DPIO_PCS_TX2DEEMP_MASK        (0xf << 24)
#define   DPIO_PCS_TX2DEEMP_9P5         (0 << 24)
#define   DPIO_PCS_TX2DEEMP_6P0         (2 << 24)
#define   DPIO_PCS_TX1DEEMP_MASK        (0xf << 16)
#define   DPIO_PCS_TX1DEEMP_9P5         (0 << 16)
#define   DPIO_PCS_TX1DEEMP_6P0         (2 << 16)
#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)

#define _VLV_PCS01_DW10_CH0             0x0228
#define _VLV_PCS23_DW10_CH0             0x0428
#define _VLV_PCS01_DW10_CH1             0x2628
#define _VLV_PCS23_DW10_CH1             0x2828
#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)

#define _VLV_PCS_DW11_CH0               0x822c
#define _VLV_PCS_DW11_CH1               0x842c
#define   DPIO_TX2_STAGGER_MASK(x)      ((x) << 24)
#define   DPIO_LANEDESKEW_STRAP_OVRD    (1 << 3)
#define   DPIO_LEFT_TXFIFO_RST_MASTER   (1 << 1)
#define   DPIO_RIGHT_TXFIFO_RST_MASTER  (1 << 0)
#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)

#define _VLV_PCS01_DW11_CH0             0x022c
#define _VLV_PCS23_DW11_CH0             0x042c
#define _VLV_PCS01_DW11_CH1             0x262c
#define _VLV_PCS23_DW11_CH1             0x282c
#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)

#define _VLV_PCS01_DW12_CH0             0x0230
#define _VLV_PCS23_DW12_CH0             0x0430
#define _VLV_PCS01_DW12_CH1             0x2630
#define _VLV_PCS23_DW12_CH1             0x2830
#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)

#define _VLV_PCS_DW12_CH0               0x8230
#define _VLV_PCS_DW12_CH1               0x8430
#define   DPIO_TX2_STAGGER_MULT(x)      ((x) << 20)
#define   DPIO_TX1_STAGGER_MULT(x)      ((x) << 16)
#define   DPIO_TX1_STAGGER_MASK(x)      ((x) << 8)
#define   DPIO_LANESTAGGER_STRAP_OVRD   (1 << 6)
#define   DPIO_LANESTAGGER_STRAP(x)     ((x) << 0)
#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)

#define _VLV_PCS_DW14_CH0               0x8238
#define _VLV_PCS_DW14_CH1               0x8438
#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)

#define _VLV_PCS_DW23_CH0               0x825c
#define _VLV_PCS_DW23_CH1               0x845c
#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)

#define _VLV_TX_DW2_CH0                 0x8288
#define _VLV_TX_DW2_CH1                 0x8488
#define   DPIO_SWING_MARGIN000_SHIFT    16
#define   DPIO_SWING_MARGIN000_MASK     (0xff << DPIO_SWING_MARGIN000_SHIFT)
#define   DPIO_UNIQ_TRANS_SCALE_SHIFT   8
#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)

#define _VLV_TX_DW3_CH0                 0x828c
#define _VLV_TX_DW3_CH1                 0x848c
/* The following bit for CHV phy */
#define   DPIO_TX_UNIQ_TRANS_SCALE_EN   (1 << 27)
#define   DPIO_SWING_MARGIN101_SHIFT    16
#define   DPIO_SWING_MARGIN101_MASK     (0xff << DPIO_SWING_MARGIN101_SHIFT)
#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)

#define _VLV_TX_DW4_CH0                 0x8290
#define _VLV_TX_DW4_CH1                 0x8490
#define   DPIO_SWING_DEEMPH9P5_SHIFT    24
#define   DPIO_SWING_DEEMPH9P5_MASK     (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
#define   DPIO_SWING_DEEMPH6P0_SHIFT    16
#define   DPIO_SWING_DEEMPH6P0_MASK     (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)

#define _VLV_TX3_DW4_CH0                0x690
#define _VLV_TX3_DW4_CH1                0x2a90
#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)

#define _VLV_TX_DW5_CH0                 0x8294
#define _VLV_TX_DW5_CH1                 0x8494
#define   DPIO_TX_OCALINIT_EN           (1 << 31)
#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)

#define _VLV_TX_DW11_CH0                0x82ac
#define _VLV_TX_DW11_CH1                0x84ac
#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)

#define _VLV_TX_DW14_CH0                0x82b8
#define _VLV_TX_DW14_CH1                0x84b8
#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)

/* CHV dpPhy registers */
#define _CHV_PLL_DW0_CH0                0x8000
#define _CHV_PLL_DW0_CH1                0x8180
#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)

#define _CHV_PLL_DW1_CH0                0x8004
#define _CHV_PLL_DW1_CH1                0x8184
#define   DPIO_CHV_N_DIV_SHIFT          8
#define   DPIO_CHV_M1_DIV_BY_2          (0 << 0)
#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)

#define _CHV_PLL_DW2_CH0                0x8008
#define _CHV_PLL_DW2_CH1                0x8188
#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)

#define _CHV_PLL_DW3_CH0                0x800c
#define _CHV_PLL_DW3_CH1                0x818c
#define  DPIO_CHV_FRAC_DIV_EN           (1 << 16)
#define  DPIO_CHV_FIRST_MOD             (0 << 8)
#define  DPIO_CHV_SECOND_MOD            (1 << 8)
#define  DPIO_CHV_FEEDFWD_GAIN_SHIFT    0
#define  DPIO_CHV_FEEDFWD_GAIN_MASK             (0xF << 0)
#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)

#define _CHV_PLL_DW6_CH0                0x8018
#define _CHV_PLL_DW6_CH1                0x8198
#define   DPIO_CHV_GAIN_CTRL_SHIFT      16
#define   DPIO_CHV_INT_COEFF_SHIFT      8
#define   DPIO_CHV_PROP_COEFF_SHIFT     0
#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)

#define _CHV_PLL_DW8_CH0                0x8020
#define _CHV_PLL_DW8_CH1                0x81A0
#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
#define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)

#define _CHV_PLL_DW9_CH0                0x8024
#define _CHV_PLL_DW9_CH1                0x81A4
#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT              1 /* 3 bits */
#define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK               (7 << 1)
#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine  */
#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)

#define _CHV_CMN_DW0_CH0               0x8100
#define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0        19
#define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0        18
#define   DPIO_ALLDL_POWERDOWN                  (1 << 1)
#define   DPIO_ANYDL_POWERDOWN                  (1 << 0)

#define _CHV_CMN_DW5_CH0               0x8114
#define   CHV_BUFRIGHTENA1_DISABLE      (0 << 20)
#define   CHV_BUFRIGHTENA1_NORMAL       (1 << 20)
#define   CHV_BUFRIGHTENA1_FORCE        (3 << 20)
#define   CHV_BUFRIGHTENA1_MASK         (3 << 20)
#define   CHV_BUFLEFTENA1_DISABLE       (0 << 22)
#define   CHV_BUFLEFTENA1_NORMAL        (1 << 22)
#define   CHV_BUFLEFTENA1_FORCE         (3 << 22)
#define   CHV_BUFLEFTENA1_MASK          (3 << 22)

#define _CHV_CMN_DW13_CH0               0x8134
#define _CHV_CMN_DW0_CH1                0x8080
#define   DPIO_CHV_S1_DIV_SHIFT         21
#define   DPIO_CHV_P1_DIV_SHIFT         13 /* 3 bits */
#define   DPIO_CHV_P2_DIV_SHIFT         8  /* 5 bits */
#define   DPIO_CHV_K_DIV_SHIFT          4
#define   DPIO_PLL_FREQLOCK             (1 << 1)
#define   DPIO_PLL_LOCK                 (1 << 0)
#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)

#define _CHV_CMN_DW14_CH0               0x8138
#define _CHV_CMN_DW1_CH1                0x8084
#define   DPIO_AFC_RECAL                (1 << 14)
#define   DPIO_DCLKP_EN                 (1 << 13)
#define   CHV_BUFLEFTENA2_DISABLE       (0 << 17) /* CL2 DW1 only */
#define   CHV_BUFLEFTENA2_NORMAL        (1 << 17) /* CL2 DW1 only */
#define   CHV_BUFLEFTENA2_FORCE         (3 << 17) /* CL2 DW1 only */
#define   CHV_BUFLEFTENA2_MASK          (3 << 17) /* CL2 DW1 only */
#define   CHV_BUFRIGHTENA2_DISABLE      (0 << 19) /* CL2 DW1 only */
#define   CHV_BUFRIGHTENA2_NORMAL       (1 << 19) /* CL2 DW1 only */
#define   CHV_BUFRIGHTENA2_FORCE        (3 << 19) /* CL2 DW1 only */
#define   CHV_BUFRIGHTENA2_MASK         (3 << 19) /* CL2 DW1 only */
#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)

#define _CHV_CMN_DW19_CH0               0x814c
#define _CHV_CMN_DW6_CH1                0x8098
#define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1        30 /* CL2 DW6 only */
#define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1        29 /* CL2 DW6 only */
#define   DPIO_DYNPWRDOWNEN_CH1         (1 << 28) /* CL2 DW6 only */
#define   CHV_CMN_USEDCLKCHANNEL        (1 << 13)

#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)

#define CHV_CMN_DW28                    0x8170
#define   DPIO_CL1POWERDOWNEN           (1 << 23)
#define   DPIO_DYNPWRDOWNEN_CH0         (1 << 22)
#define   DPIO_SUS_CLK_CONFIG_ON                (0 << 0)
#define   DPIO_SUS_CLK_CONFIG_CLKREQ            (1 << 0)
#define   DPIO_SUS_CLK_CONFIG_GATE              (2 << 0)
#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ       (3 << 0)

#define CHV_CMN_DW30                    0x8178
#define   DPIO_CL2_LDOFUSE_PWRENB       (1 << 6)
#define   DPIO_LRC_BYPASS               (1 << 3)

#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
                                        (lane) * 0x200 + (offset))

#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
#define   DPIO_FRC_LATENCY_SHFIT        8
#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
#define   DPIO_UPAR_SHIFT               30

/* BXT PHY registers */
#define _BXT_PHY0_BASE                  0x6C000
#define _BXT_PHY1_BASE                  0x162000
#define _BXT_PHY2_BASE                  0x163000
#define BXT_PHY_BASE(phy)               _PHY3((phy), _BXT_PHY0_BASE, \
                                                     _BXT_PHY1_BASE, \
                                                     _BXT_PHY2_BASE)

#define _BXT_PHY(phy, reg)                                              \
        _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))

#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)          \
        (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE,    \
                                         (reg_ch1) - _BXT_PHY0_BASE))
#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)             \
        _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))

#define BXT_P_CR_GT_DISP_PWRON          _MMIO(0x138090)
#define  MIPIO_RST_CTRL                         (1 << 2)

#define _BXT_PHY_CTL_DDI_A              0x64C00
#define _BXT_PHY_CTL_DDI_B              0x64C10
#define _BXT_PHY_CTL_DDI_C              0x64C20
#define   BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
#define   BXT_PHY_LANE_POWERDOWN_ACK    (1 << 9)
#define   BXT_PHY_LANE_ENABLED          (1 << 8)
#define BXT_PHY_CTL(port)               _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
                                                         _BXT_PHY_CTL_DDI_B)

#define _PHY_CTL_FAMILY_EDP             0x64C80
#define _PHY_CTL_FAMILY_DDI             0x64C90
#define _PHY_CTL_FAMILY_DDI_C           0x64CA0
#define   COMMON_RESET_DIS              (1 << 31)
#define BXT_PHY_CTL_FAMILY(phy)         _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
                                                          _PHY_CTL_FAMILY_EDP, \
                                                          _PHY_CTL_FAMILY_DDI_C)

/* BXT PHY PLL registers */
#define _PORT_PLL_A                     0x46074
#define _PORT_PLL_B                     0x46078
#define _PORT_PLL_C                     0x4607c
#define   PORT_PLL_ENABLE               REG_BIT(31)
#define   PORT_PLL_LOCK                 REG_BIT(30)
#define   PORT_PLL_REF_SEL              REG_BIT(27)
#define   PORT_PLL_POWER_ENABLE         REG_BIT(26)
#define   PORT_PLL_POWER_STATE          REG_BIT(25)
#define BXT_PORT_PLL_ENABLE(port)       _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)

#define _PORT_PLL_EBB_0_A               0x162034
#define _PORT_PLL_EBB_0_B               0x6C034
#define _PORT_PLL_EBB_0_C               0x6C340
#define   PORT_PLL_P1_MASK              REG_GENMASK(15, 13)
#define   PORT_PLL_P1(p1)               REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
#define   PORT_PLL_P2_MASK              REG_GENMASK(12, 8)
#define   PORT_PLL_P2(p2)               REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))
#define BXT_PORT_PLL_EBB_0(phy, ch)     _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_PLL_EBB_0_B, \
                                                         _PORT_PLL_EBB_0_C)

#define _PORT_PLL_EBB_4_A               0x162038
#define _PORT_PLL_EBB_4_B               0x6C038
#define _PORT_PLL_EBB_4_C               0x6C344
#define   PORT_PLL_RECALIBRATE          REG_BIT(14)
#define   PORT_PLL_10BIT_CLK_ENABLE     REG_BIT(13)
#define BXT_PORT_PLL_EBB_4(phy, ch)     _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_PLL_EBB_4_B, \
                                                         _PORT_PLL_EBB_4_C)

#define _PORT_PLL_0_A                   0x162100
#define _PORT_PLL_0_B                   0x6C100
#define _PORT_PLL_0_C                   0x6C380
/* PORT_PLL_0_A */
#define   PORT_PLL_M2_INT_MASK          REG_GENMASK(7, 0)
#define   PORT_PLL_M2_INT(m2_int)       REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int))
/* PORT_PLL_1_A */
#define   PORT_PLL_N_MASK               REG_GENMASK(11, 8)
#define   PORT_PLL_N(n)                 REG_FIELD_PREP(PORT_PLL_N_MASK, (n))
/* PORT_PLL_2_A */
#define   PORT_PLL_M2_FRAC_MASK         REG_GENMASK(21, 0)
#define   PORT_PLL_M2_FRAC(m2_frac)     REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac))
/* PORT_PLL_3_A */
#define   PORT_PLL_M2_FRAC_ENABLE       REG_BIT(16)
/* PORT_PLL_6_A */
#define   PORT_PLL_GAIN_CTL_MASK        REG_GENMASK(18, 16)
#define   PORT_PLL_GAIN_CTL(x)          REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x))
#define   PORT_PLL_INT_COEFF_MASK       REG_GENMASK(12, 8)
#define   PORT_PLL_INT_COEFF(x)         REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x))
#define   PORT_PLL_PROP_COEFF_MASK      REG_GENMASK(3, 0)
#define   PORT_PLL_PROP_COEFF(x)        REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x))
/* PORT_PLL_8_A */
#define   PORT_PLL_TARGET_CNT_MASK      REG_GENMASK(9, 0)
#define   PORT_PLL_TARGET_CNT(x)        REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x))
/* PORT_PLL_9_A */
#define  PORT_PLL_LOCK_THRESHOLD_MASK   REG_GENMASK(3, 1)
#define  PORT_PLL_LOCK_THRESHOLD(x)     REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x))
/* PORT_PLL_10_A */
#define  PORT_PLL_DCO_AMP_OVR_EN_H      REG_BIT(27)
#define  PORT_PLL_DCO_AMP_MASK          REG_GENMASK(13, 10)
#define  PORT_PLL_DCO_AMP(x)            REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x))
#define _PORT_PLL_BASE(phy, ch)         _BXT_PHY_CH(phy, ch, \
                                                    _PORT_PLL_0_B, \
                                                    _PORT_PLL_0_C)
#define BXT_PORT_PLL(phy, ch, idx)      _MMIO(_PORT_PLL_BASE(phy, ch) + \
                                              (idx) * 4)

/* BXT PHY common lane registers */
#define _PORT_CL1CM_DW0_A               0x162000
#define _PORT_CL1CM_DW0_BC              0x6C000
#define   PHY_POWER_GOOD                (1 << 16)
#define   PHY_RESERVED                  (1 << 7)
#define BXT_PORT_CL1CM_DW0(phy)         _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)

#define _PORT_CL1CM_DW9_A               0x162024
#define _PORT_CL1CM_DW9_BC              0x6C024
#define   IREF0RC_OFFSET_SHIFT          8
#define   IREF0RC_OFFSET_MASK           (0xFF << IREF0RC_OFFSET_SHIFT)
#define BXT_PORT_CL1CM_DW9(phy)         _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)

#define _PORT_CL1CM_DW10_A              0x162028
#define _PORT_CL1CM_DW10_BC             0x6C028
#define   IREF1RC_OFFSET_SHIFT          8
#define   IREF1RC_OFFSET_MASK           (0xFF << IREF1RC_OFFSET_SHIFT)
#define BXT_PORT_CL1CM_DW10(phy)        _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)

#define _PORT_CL1CM_DW28_A              0x162070
#define _PORT_CL1CM_DW28_BC             0x6C070
#define   OCL1_POWER_DOWN_EN            (1 << 23)
#define   DW28_OLDO_DYN_PWR_DOWN_EN     (1 << 22)
#define   SUS_CLK_CONFIG                0x3
#define BXT_PORT_CL1CM_DW28(phy)        _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)

#define _PORT_CL1CM_DW30_A              0x162078
#define _PORT_CL1CM_DW30_BC             0x6C078
#define   OCL2_LDOFUSE_PWR_DIS          (1 << 6)
#define BXT_PORT_CL1CM_DW30(phy)        _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)

/* The spec defines this only for BXT PHY0, but lets assume that this
 * would exist for PHY1 too if it had a second channel.
 */
#define _PORT_CL2CM_DW6_A               0x162358
#define _PORT_CL2CM_DW6_BC              0x6C358
#define BXT_PORT_CL2CM_DW6(phy)         _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
#define   DW6_OLDO_DYN_PWR_DOWN_EN      (1 << 28)

/* BXT PHY Ref registers */
#define _PORT_REF_DW3_A                 0x16218C
#define _PORT_REF_DW3_BC                0x6C18C
#define   GRC_DONE                      (1 << 22)
#define BXT_PORT_REF_DW3(phy)           _BXT_PHY((phy), _PORT_REF_DW3_BC)

#define _PORT_REF_DW6_A                 0x162198
#define _PORT_REF_DW6_BC                0x6C198
#define   GRC_CODE_SHIFT                24
#define   GRC_CODE_MASK                 (0xFF << GRC_CODE_SHIFT)
#define   GRC_CODE_FAST_SHIFT           16
#define   GRC_CODE_FAST_MASK            (0xFF << GRC_CODE_FAST_SHIFT)
#define   GRC_CODE_SLOW_SHIFT           8
#define   GRC_CODE_SLOW_MASK            (0xFF << GRC_CODE_SLOW_SHIFT)
#define   GRC_CODE_NOM_MASK             0xFF
#define BXT_PORT_REF_DW6(phy)           _BXT_PHY((phy), _PORT_REF_DW6_BC)

#define _PORT_REF_DW8_A                 0x1621A0
#define _PORT_REF_DW8_BC                0x6C1A0
#define   GRC_DIS                       (1 << 15)
#define   GRC_RDY_OVRD                  (1 << 1)
#define BXT_PORT_REF_DW8(phy)           _BXT_PHY((phy), _PORT_REF_DW8_BC)

/* BXT PHY PCS registers */
#define _PORT_PCS_DW10_LN01_A           0x162428
#define _PORT_PCS_DW10_LN01_B           0x6C428
#define _PORT_PCS_DW10_LN01_C           0x6C828
#define _PORT_PCS_DW10_GRP_A            0x162C28
#define _PORT_PCS_DW10_GRP_B            0x6CC28
#define _PORT_PCS_DW10_GRP_C            0x6CE28
#define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_PCS_DW10_LN01_B, \
                                                         _PORT_PCS_DW10_LN01_C)
#define BXT_PORT_PCS_DW10_GRP(phy, ch)  _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_PCS_DW10_GRP_B, \
                                                         _PORT_PCS_DW10_GRP_C)

#define   TX2_SWING_CALC_INIT           (1 << 31)
#define   TX1_SWING_CALC_INIT           (1 << 30)

#define _PORT_PCS_DW12_LN01_A           0x162430
#define _PORT_PCS_DW12_LN01_B           0x6C430
#define _PORT_PCS_DW12_LN01_C           0x6C830
#define _PORT_PCS_DW12_LN23_A           0x162630
#define _PORT_PCS_DW12_LN23_B           0x6C630
#define _PORT_PCS_DW12_LN23_C           0x6CA30
#define _PORT_PCS_DW12_GRP_A            0x162c30
#define _PORT_PCS_DW12_GRP_B            0x6CC30
#define _PORT_PCS_DW12_GRP_C            0x6CE30
#define   LANESTAGGER_STRAP_OVRD        (1 << 6)
#define   LANE_STAGGER_MASK             0x1F
#define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_PCS_DW12_LN01_B, \
                                                         _PORT_PCS_DW12_LN01_C)
#define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_PCS_DW12_LN23_B, \
                                                         _PORT_PCS_DW12_LN23_C)
#define BXT_PORT_PCS_DW12_GRP(phy, ch)  _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_PCS_DW12_GRP_B, \
                                                         _PORT_PCS_DW12_GRP_C)

/* BXT PHY TX registers */
#define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +       \
                                          ((lane) & 1) * 0x80)

#define _PORT_TX_DW2_LN0_A              0x162508
#define _PORT_TX_DW2_LN0_B              0x6C508
#define _PORT_TX_DW2_LN0_C              0x6C908
#define _PORT_TX_DW2_GRP_A              0x162D08
#define _PORT_TX_DW2_GRP_B              0x6CD08
#define _PORT_TX_DW2_GRP_C              0x6CF08
#define BXT_PORT_TX_DW2_LN0(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_TX_DW2_LN0_B, \
                                                         _PORT_TX_DW2_LN0_C)
#define BXT_PORT_TX_DW2_GRP(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_TX_DW2_GRP_B, \
                                                         _PORT_TX_DW2_GRP_C)
#define   MARGIN_000_SHIFT              16
#define   MARGIN_000                    (0xFF << MARGIN_000_SHIFT)
#define   UNIQ_TRANS_SCALE_SHIFT        8
#define   UNIQ_TRANS_SCALE              (0xFF << UNIQ_TRANS_SCALE_SHIFT)

#define _PORT_TX_DW3_LN0_A              0x16250C
#define _PORT_TX_DW3_LN0_B              0x6C50C
#define _PORT_TX_DW3_LN0_C              0x6C90C
#define _PORT_TX_DW3_GRP_A              0x162D0C
#define _PORT_TX_DW3_GRP_B              0x6CD0C
#define _PORT_TX_DW3_GRP_C              0x6CF0C
#define BXT_PORT_TX_DW3_LN0(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_TX_DW3_LN0_B, \
                                                         _PORT_TX_DW3_LN0_C)
#define BXT_PORT_TX_DW3_GRP(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_TX_DW3_GRP_B, \
                                                         _PORT_TX_DW3_GRP_C)
#define   SCALE_DCOMP_METHOD            (1 << 26)
#define   UNIQUE_TRANGE_EN_METHOD       (1 << 27)

#define _PORT_TX_DW4_LN0_A              0x162510
#define _PORT_TX_DW4_LN0_B              0x6C510
#define _PORT_TX_DW4_LN0_C              0x6C910
#define _PORT_TX_DW4_GRP_A              0x162D10
#define _PORT_TX_DW4_GRP_B              0x6CD10
#define _PORT_TX_DW4_GRP_C              0x6CF10
#define BXT_PORT_TX_DW4_LN0(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_TX_DW4_LN0_B, \
                                                         _PORT_TX_DW4_LN0_C)
#define BXT_PORT_TX_DW4_GRP(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_TX_DW4_GRP_B, \
                                                         _PORT_TX_DW4_GRP_C)
#define   DEEMPH_SHIFT                  24
#define   DE_EMPHASIS                   (0xFF << DEEMPH_SHIFT)

#define _PORT_TX_DW5_LN0_A              0x162514
#define _PORT_TX_DW5_LN0_B              0x6C514
#define _PORT_TX_DW5_LN0_C              0x6C914
#define _PORT_TX_DW5_GRP_A              0x162D14
#define _PORT_TX_DW5_GRP_B              0x6CD14
#define _PORT_TX_DW5_GRP_C              0x6CF14
#define BXT_PORT_TX_DW5_LN0(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_TX_DW5_LN0_B, \
                                                         _PORT_TX_DW5_LN0_C)
#define BXT_PORT_TX_DW5_GRP(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_TX_DW5_GRP_B, \
                                                         _PORT_TX_DW5_GRP_C)
#define   DCC_DELAY_RANGE_1             (1 << 9)
#define   DCC_DELAY_RANGE_2             (1 << 8)

#define _PORT_TX_DW14_LN0_A             0x162538
#define _PORT_TX_DW14_LN0_B             0x6C538
#define _PORT_TX_DW14_LN0_C             0x6C938
#define   LATENCY_OPTIM_SHIFT           30
#define   LATENCY_OPTIM                 (1 << LATENCY_OPTIM_SHIFT)
#define BXT_PORT_TX_DW14_LN(phy, ch, lane)                              \
        _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B,                 \
                                   _PORT_TX_DW14_LN0_C) +               \
              _BXT_LANE_OFFSET(lane))

/* UAIMI scratch pad register 1 */
#define UAIMI_SPR1                      _MMIO(0x4F074)
/* SKL VccIO mask */
#define SKL_VCCIO_MASK                  0x1
/* SKL balance leg register */
#define DISPIO_CR_TX_BMU_CR0            _MMIO(0x6C00C)
/* I_boost values */
#define BALANCE_LEG_SHIFT(port)         (8 + 3 * (port))
#define BALANCE_LEG_MASK(port)          (7 << (8 + 3 * (port)))
/* Balance leg disable bits */
#define BALANCE_LEG_DISABLE_SHIFT       23
#define BALANCE_LEG_DISABLE(port)       (1 << (23 + (port)))

/*
 * Fence registers
 * [0-7]  @ 0x2000 gen2,gen3
 * [8-15] @ 0x3000 945,g33,pnv
 *
 * [0-15] @ 0x3000 gen4,gen5
 *
 * [0-15] @ 0x100000 gen6,vlv,chv
 * [0-31] @ 0x100000 gen7+
 */
#define FENCE_REG(i)                    _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
#define   I830_FENCE_START_MASK         0x07f80000
#define   I830_FENCE_TILING_Y_SHIFT     12
#define   I830_FENCE_SIZE_BITS(size)    ((ffs((size) >> 19) - 1) << 8)
#define   I830_FENCE_PITCH_SHIFT        4
#define   I830_FENCE_REG_VALID          (1 << 0)
#define   I915_FENCE_MAX_PITCH_VAL      4
#define   I830_FENCE_MAX_PITCH_VAL      6
#define   I830_FENCE_MAX_SIZE_VAL       (1 << 8)

#define   I915_FENCE_START_MASK         0x0ff00000
#define   I915_FENCE_SIZE_BITS(size)    ((ffs((size) >> 20) - 1) << 8)

#define FENCE_REG_965_LO(i)             _MMIO(0x03000 + (i) * 8)
#define FENCE_REG_965_HI(i)             _MMIO(0x03000 + (i) * 8 + 4)
#define   I965_FENCE_PITCH_SHIFT        2
#define   I965_FENCE_TILING_Y_SHIFT     1
#define   I965_FENCE_REG_VALID          (1 << 0)
#define   I965_FENCE_MAX_PITCH_VAL      0x0400

#define FENCE_REG_GEN6_LO(i)            _MMIO(0x100000 + (i) * 8)
#define FENCE_REG_GEN6_HI(i)            _MMIO(0x100000 + (i) * 8 + 4)
#define   GEN6_FENCE_PITCH_SHIFT        32
#define   GEN7_FENCE_MAX_PITCH_VAL      0x0800


/* control register for cpu gtt access */
#define TILECTL                         _MMIO(0x101000)
#define   TILECTL_SWZCTL                        (1 << 0)
#define   TILECTL_TLBPF                 (1 << 1)
#define   TILECTL_TLB_PREFETCH_DIS      (1 << 2)
#define   TILECTL_BACKSNOOP_DIS         (1 << 3)

/*
 * Instruction and interrupt control regs
 */
#define PGTBL_CTL       _MMIO(0x02020)
#define   PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
#define   PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
#define PGTBL_ER        _MMIO(0x02024)
#define PRB0_BASE       (0x2030 - 0x30)
#define PRB1_BASE       (0x2040 - 0x30) /* 830,gen3 */
#define PRB2_BASE       (0x2050 - 0x30) /* gen3 */
#define SRB0_BASE       (0x2100 - 0x30) /* gen2 */
#define SRB1_BASE       (0x2110 - 0x30) /* gen2 */
#define SRB2_BASE       (0x2120 - 0x30) /* 830 */
#define SRB3_BASE       (0x2130 - 0x30) /* 830 */
#define RENDER_RING_BASE        0x02000
#define BSD_RING_BASE           0x04000
#define GEN6_BSD_RING_BASE      0x12000
#define GEN8_BSD2_RING_BASE     0x1c000
#define GEN11_BSD_RING_BASE     0x1c0000
#define GEN11_BSD2_RING_BASE    0x1c4000
#define GEN11_BSD3_RING_BASE    0x1d0000
#define GEN11_BSD4_RING_BASE    0x1d4000
#define XEHP_BSD5_RING_BASE     0x1e0000
#define XEHP_BSD6_RING_BASE     0x1e4000
#define XEHP_BSD7_RING_BASE     0x1f0000
#define XEHP_BSD8_RING_BASE     0x1f4000
#define VEBOX_RING_BASE         0x1a000
#define GEN11_VEBOX_RING_BASE           0x1c8000
#define GEN11_VEBOX2_RING_BASE          0x1d8000
#define XEHP_VEBOX3_RING_BASE           0x1e8000
#define XEHP_VEBOX4_RING_BASE           0x1f8000
#define GEN12_COMPUTE0_RING_BASE        0x1a000
#define GEN12_COMPUTE1_RING_BASE        0x1c000
#define GEN12_COMPUTE2_RING_BASE        0x1e000
#define GEN12_COMPUTE3_RING_BASE        0x26000
#define BLT_RING_BASE           0x22000
#define DG1_GSC_HECI1_BASE      0x00258000
#define DG1_GSC_HECI2_BASE      0x00259000
#define DG2_GSC_HECI1_BASE      0x00373000
#define DG2_GSC_HECI2_BASE      0x00374000



#define HSW_GTT_CACHE_EN        _MMIO(0x4024)
#define   GTT_CACHE_EN_ALL      0xF0007FFF
#define GEN7_WR_WATERMARK       _MMIO(0x4028)
#define GEN7_GFX_PRIO_CTRL      _MMIO(0x402C)
#define ARB_MODE                _MMIO(0x4030)
#define   ARB_MODE_SWIZZLE_SNB  (1 << 4)
#define   ARB_MODE_SWIZZLE_IVB  (1 << 5)
#define GEN7_GFX_PEND_TLB0      _MMIO(0x4034)
#define GEN7_GFX_PEND_TLB1      _MMIO(0x4038)
/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
#define GEN7_LRA_LIMITS(i)      _MMIO(0x403C + (i) * 4)
#define GEN7_LRA_LIMITS_REG_NUM 13
#define GEN7_MEDIA_MAX_REQ_COUNT        _MMIO(0x4070)
#define GEN7_GFX_MAX_REQ_COUNT          _MMIO(0x4074)

#define GEN7_ERR_INT    _MMIO(0x44040)
#define   ERR_INT_POISON                (1 << 31)
#define   ERR_INT_MMIO_UNCLAIMED        (1 << 13)
#define   ERR_INT_PIPE_CRC_DONE_C       (1 << 8)
#define   ERR_INT_FIFO_UNDERRUN_C       (1 << 6)
#define   ERR_INT_PIPE_CRC_DONE_B       (1 << 5)
#define   ERR_INT_FIFO_UNDERRUN_B       (1 << 3)
#define   ERR_INT_PIPE_CRC_DONE_A       (1 << 2)
#define   ERR_INT_PIPE_CRC_DONE(pipe)   (1 << (2 + (pipe) * 3))
#define   ERR_INT_FIFO_UNDERRUN_A       (1 << 0)
#define   ERR_INT_FIFO_UNDERRUN(pipe)   (1 << ((pipe) * 3))

#define FPGA_DBG                _MMIO(0x42300)
#define   FPGA_DBG_RM_NOCLAIM   REG_BIT(31)

#define CLAIM_ER                _MMIO(VLV_DISPLAY_BASE + 0x2028)
#define   CLAIM_ER_CLR          REG_BIT(31)
#define   CLAIM_ER_OVERFLOW     REG_BIT(16)
#define   CLAIM_ER_CTR_MASK     REG_GENMASK(15, 0)

#define DERRMR          _MMIO(0x44050)
/* Note that HBLANK events are reserved on bdw+ */
#define   DERRMR_PIPEA_SCANLINE         (1 << 0)
#define   DERRMR_PIPEA_PRI_FLIP_DONE    (1 << 1)
#define   DERRMR_PIPEA_SPR_FLIP_DONE    (1 << 2)
#define   DERRMR_PIPEA_VBLANK           (1 << 3)
#define   DERRMR_PIPEA_HBLANK           (1 << 5)
#define   DERRMR_PIPEB_SCANLINE         (1 << 8)
#define   DERRMR_PIPEB_PRI_FLIP_DONE    (1 << 9)
#define   DERRMR_PIPEB_SPR_FLIP_DONE    (1 << 10)
#define   DERRMR_PIPEB_VBLANK           (1 << 11)
#define   DERRMR_PIPEB_HBLANK           (1 << 13)
/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
#define   DERRMR_PIPEC_SCANLINE         (1 << 14)
#define   DERRMR_PIPEC_PRI_FLIP_DONE    (1 << 15)
#define   DERRMR_PIPEC_SPR_FLIP_DONE    (1 << 20)
#define   DERRMR_PIPEC_VBLANK           (1 << 21)
#define   DERRMR_PIPEC_HBLANK           (1 << 22)

#define VLV_GU_CTL0     _MMIO(VLV_DISPLAY_BASE + 0x2030)
#define VLV_GU_CTL1     _MMIO(VLV_DISPLAY_BASE + 0x2034)
#define SCPD0           _MMIO(0x209c) /* 915+ only */
#define  SCPD_FBC_IGNORE_3D                     (1 << 6)
#define  CSTATE_RENDER_CLOCK_GATE_DISABLE       (1 << 5)
#define GEN2_IER        _MMIO(0x20a0)
#define GEN2_IIR        _MMIO(0x20a4)
#define GEN2_IMR        _MMIO(0x20a8)
#define GEN2_ISR        _MMIO(0x20ac)
#define VLV_GUNIT_CLOCK_GATE    _MMIO(VLV_DISPLAY_BASE + 0x2060)
#define   GINT_DIS              (1 << 22)
#define   GCFG_DIS              (1 << 8)
#define VLV_GUNIT_CLOCK_GATE2   _MMIO(VLV_DISPLAY_BASE + 0x2064)
#define VLV_IIR_RW      _MMIO(VLV_DISPLAY_BASE + 0x2084)
#define VLV_IER         _MMIO(VLV_DISPLAY_BASE + 0x20a0)
#define VLV_IIR         _MMIO(VLV_DISPLAY_BASE + 0x20a4)
#define VLV_IMR         _MMIO(VLV_DISPLAY_BASE + 0x20a8)
#define VLV_ISR         _MMIO(VLV_DISPLAY_BASE + 0x20ac)
#define VLV_PCBR        _MMIO(VLV_DISPLAY_BASE + 0x2120)
#define VLV_PCBR_ADDR_SHIFT     12

#define   DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
#define EIR             _MMIO(0x20b0)
#define EMR             _MMIO(0x20b4)
#define ESR             _MMIO(0x20b8)
#define   GM45_ERROR_PAGE_TABLE                         (1 << 5)
#define   GM45_ERROR_MEM_PRIV                           (1 << 4)
#define   I915_ERROR_PAGE_TABLE                         (1 << 4)
#define   GM45_ERROR_CP_PRIV                            (1 << 3)
#define   I915_ERROR_MEMORY_REFRESH                     (1 << 1)
#define   I915_ERROR_INSTRUCTION                        (1 << 0)
#define INSTPM          _MMIO(0x20c0)
#define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
#define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
                                        will not assert AGPBUSY# and will only
                                        be delivered when out of C3. */
#define   INSTPM_FORCE_ORDERING                         (1 << 7) /* GEN6+ */
#define   INSTPM_TLB_INVALIDATE (1 << 9)
#define   INSTPM_SYNC_FLUSH     (1 << 5)
#define MEM_MODE        _MMIO(0x20cc)
#define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
#define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
#define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
#define FW_BLC          _MMIO(0x20d8)
#define FW_BLC2         _MMIO(0x20dc)
#define FW_BLC_SELF     _MMIO(0x20e0) /* 915+ only */
#define   FW_BLC_SELF_EN_MASK      (1 << 31)
#define   FW_BLC_SELF_FIFO_MASK    (1 << 16) /* 945 only */
#define   FW_BLC_SELF_EN           (1 << 15) /* 945 only */
#define MM_BURST_LENGTH     0x00700000
#define MM_FIFO_WATERMARK   0x0001F000
#define LM_BURST_LENGTH     0x00000700
#define LM_FIFO_WATERMARK   0x0000001F
#define MI_ARB_STATE    _MMIO(0x20e4) /* 915+ only */

#define _MBUS_ABOX0_CTL                 0x45038
#define _MBUS_ABOX1_CTL                 0x45048
#define _MBUS_ABOX2_CTL                 0x4504C
#define MBUS_ABOX_CTL(x)                _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \
                                                    _MBUS_ABOX1_CTL, \
                                                    _MBUS_ABOX2_CTL))
#define MBUS_ABOX_BW_CREDIT_MASK        (3 << 20)
#define MBUS_ABOX_BW_CREDIT(x)          ((x) << 20)
#define MBUS_ABOX_B_CREDIT_MASK         (0xF << 16)
#define MBUS_ABOX_B_CREDIT(x)           ((x) << 16)
#define MBUS_ABOX_BT_CREDIT_POOL2_MASK  (0x1F << 8)
#define MBUS_ABOX_BT_CREDIT_POOL2(x)    ((x) << 8)
#define MBUS_ABOX_BT_CREDIT_POOL1_MASK  (0x1F << 0)
#define MBUS_ABOX_BT_CREDIT_POOL1(x)    ((x) << 0)

#define _PIPEA_MBUS_DBOX_CTL                    0x7003C
#define _PIPEB_MBUS_DBOX_CTL                    0x7103C
#define PIPE_MBUS_DBOX_CTL(pipe)                _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
                                                           _PIPEB_MBUS_DBOX_CTL)
#define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK     REG_GENMASK(24, 20) /* tgl+ */
#define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x)       REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x)
#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK   REG_GENMASK(19, 17) /* tgl+ */
#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x)     REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x)
#define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN  REG_BIT(16) /* tgl+ */
#define MBUS_DBOX_BW_CREDIT_MASK                REG_GENMASK(15, 14)
#define MBUS_DBOX_BW_CREDIT(x)                  REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
#define MBUS_DBOX_B_CREDIT_MASK                 REG_GENMASK(12, 8)
#define MBUS_DBOX_B_CREDIT(x)                   REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
#define MBUS_DBOX_A_CREDIT_MASK                 REG_GENMASK(3, 0)
#define MBUS_DBOX_A_CREDIT(x)                   REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)

#define MBUS_UBOX_CTL                   _MMIO(0x4503C)
#define MBUS_BBOX_CTL_S1                _MMIO(0x45040)
#define MBUS_BBOX_CTL_S2                _MMIO(0x45044)

#define MBUS_CTL                        _MMIO(0x4438C)
#define MBUS_JOIN                       REG_BIT(31)
#define MBUS_HASHING_MODE_MASK          REG_BIT(30)
#define MBUS_HASHING_MODE_2x2           REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
#define MBUS_HASHING_MODE_1x4           REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
#define MBUS_JOIN_PIPE_SELECT_MASK      REG_GENMASK(28, 26)
#define MBUS_JOIN_PIPE_SELECT(pipe)     REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
#define MBUS_JOIN_PIPE_SELECT_NONE      MBUS_JOIN_PIPE_SELECT(7)

#define HDPORT_STATE                    _MMIO(0x45050)
#define   HDPORT_DPLL_USED_MASK         REG_GENMASK(15, 12)
#define   HDPORT_DDI_USED(phy)          REG_BIT(2 * (phy) + 1)
#define   HDPORT_ENABLED                REG_BIT(0)

/* Make render/texture TLB fetches lower priorty than associated data
 *   fetches. This is not turned on by default
 */
#define   MI_ARB_RENDER_TLB_LOW_PRIORITY        (1 << 15)

/* Isoch request wait on GTT enable (Display A/B/C streams).
 * Make isoch requests stall on the TLB update. May cause
 * display underruns (test mode only)
 */
#define   MI_ARB_ISOCH_WAIT_GTT                 (1 << 14)

/* Block grant count for isoch requests when block count is
 * set to a finite value.
 */
#define   MI_ARB_BLOCK_GRANT_MASK               (3 << 12)
#define   MI_ARB_BLOCK_GRANT_8                  (0 << 12)       /* for 3 display planes */
#define   MI_ARB_BLOCK_GRANT_4                  (1 << 12)       /* for 2 display planes */
#define   MI_ARB_BLOCK_GRANT_2                  (2 << 12)       /* for 1 display plane */
#define   MI_ARB_BLOCK_GRANT_0                  (3 << 12)       /* don't use */

/* Enable render writes to complete in C2/C3/C4 power states.
 * If this isn't enabled, render writes are prevented in low
 * power states. That seems bad to me.
 */
#define   MI_ARB_C3_LP_WRITE_ENABLE             (1 << 11)

/* This acknowledges an async flip immediately instead
 * of waiting for 2TLB fetches.
 */
#define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE       (1 << 10)

/* Enables non-sequential data reads through arbiter
 */
#define   MI_ARB_DUAL_DATA_PHASE_DISABLE        (1 << 9)

/* Disable FSB snooping of cacheable write cycles from binner/render
 * command stream
 */
#define   MI_ARB_CACHE_SNOOP_DISABLE            (1 << 8)

/* Arbiter time slice for non-isoch streams */
#define   MI_ARB_TIME_SLICE_MASK                (7 << 5)
#define   MI_ARB_TIME_SLICE_1                   (0 << 5)
#define   MI_ARB_TIME_SLICE_2                   (1 << 5)
#define   MI_ARB_TIME_SLICE_4                   (2 << 5)
#define   MI_ARB_TIME_SLICE_6                   (3 << 5)
#define   MI_ARB_TIME_SLICE_8                   (4 << 5)
#define   MI_ARB_TIME_SLICE_10                  (5 << 5)
#define   MI_ARB_TIME_SLICE_14                  (6 << 5)
#define   MI_ARB_TIME_SLICE_16                  (7 << 5)

/* Low priority grace period page size */
#define   MI_ARB_LOW_PRIORITY_GRACE_4KB         (0 << 4)        /* default */
#define   MI_ARB_LOW_PRIORITY_GRACE_8KB         (1 << 4)

/* Disable display A/B trickle feed */
#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE   (1 << 2)

/* Set display plane priority */
#define   MI_ARB_DISPLAY_PRIORITY_A_B           (0 << 0)        /* display A > display B */
#define   MI_ARB_DISPLAY_PRIORITY_B_A           (1 << 0)        /* display B > display A */

#define MI_STATE        _MMIO(0x20e4) /* gen2 only */
#define   MI_AGPBUSY_INT_EN                     (1 << 1) /* 85x only */
#define   MI_AGPBUSY_830_MODE                   (1 << 0) /* 85x only */

/* On modern GEN architectures interrupt control consists of two sets
 * of registers. The first set pertains to the ring generating the
 * interrupt. The second control is for the functional block generating the
 * interrupt. These are PM, GT, DE, etc.
 *
 * Luckily *knocks on wood* all the ring interrupt bits match up with the
 * GT interrupt bits, so we don't need to duplicate the defines.
 *
 * These defines should cover us well from SNB->HSW with minor exceptions
 * it can also work on ILK.
 */
#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT         (1 << 26)
#define GT_BLT_CS_ERROR_INTERRUPT               (1 << 25)
#define GT_BLT_USER_INTERRUPT                   (1 << 22)
#define GT_BSD_CS_ERROR_INTERRUPT               (1 << 15)
#define GT_BSD_USER_INTERRUPT                   (1 << 12)
#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1  (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
#define GT_WAIT_SEMAPHORE_INTERRUPT             REG_BIT(11) /* bdw+ */
#define GT_CONTEXT_SWITCH_INTERRUPT             (1 <<  8)
#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT     (1 <<  5) /* !snb */
#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT      (1 <<  4)
#define GT_CS_MASTER_ERROR_INTERRUPT            REG_BIT(3)
#define GT_RENDER_SYNC_STATUS_INTERRUPT         (1 <<  2)
#define GT_RENDER_DEBUG_INTERRUPT               (1 <<  1)
#define GT_RENDER_USER_INTERRUPT                (1 <<  0)

#define PM_VEBOX_CS_ERROR_INTERRUPT             (1 << 12) /* hsw+ */
#define PM_VEBOX_USER_INTERRUPT                 (1 << 10) /* hsw+ */

#define GT_PARITY_ERROR(dev_priv) \
        (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
         (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))

/* These are all the "old" interrupts */
#define ILK_BSD_USER_INTERRUPT                          (1 << 5)

#define I915_PM_INTERRUPT                               (1 << 31)
#define I915_ISP_INTERRUPT                              (1 << 22)
#define I915_LPE_PIPE_B_INTERRUPT                       (1 << 21)
#define I915_LPE_PIPE_A_INTERRUPT                       (1 << 20)
#define I915_MIPIC_INTERRUPT                            (1 << 19)
#define I915_MIPIA_INTERRUPT                            (1 << 18)
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT              (1 << 18)
#define I915_DISPLAY_PORT_INTERRUPT                     (1 << 17)
#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT            (1 << 16)
#define I915_MASTER_ERROR_INTERRUPT                     (1 << 15)
#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT            (1 << 14)
#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT        (1 << 14) /* p-state */
#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT            (1 << 13)
#define I915_HWB_OOM_INTERRUPT                          (1 << 13)
#define I915_LPE_PIPE_C_INTERRUPT                       (1 << 12)
#define I915_SYNC_STATUS_INTERRUPT                      (1 << 12)
#define I915_MISC_INTERRUPT                             (1 << 11)
#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT     (1 << 11)
#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT            (1 << 10)
#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT     (1 << 10)
#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT             (1 << 9)
#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT       (1 << 9)
#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT              (1 << 8)
#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT     (1 << 8)
#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT            (1 << 7)
#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT             (1 << 6)
#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT            (1 << 5)
#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT             (1 << 4)
#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT              (1 << 3)
#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT              (1 << 2)
#define I915_DEBUG_INTERRUPT                            (1 << 2)
#define I915_WINVALID_INTERRUPT                         (1 << 1)
#define I915_USER_INTERRUPT                             (1 << 1)
#define I915_ASLE_INTERRUPT                             (1 << 0)
#define I915_BSD_USER_INTERRUPT                         (1 << 25)

#define I915_HDMI_LPE_AUDIO_BASE        (VLV_DISPLAY_BASE + 0x65000)
#define I915_HDMI_LPE_AUDIO_SIZE        0x1000

/* DisplayPort Audio w/ LPE */
#define VLV_AUD_CHICKEN_BIT_REG         _MMIO(VLV_DISPLAY_BASE + 0x62F38)
#define VLV_CHICKEN_BIT_DBG_ENABLE      (1 << 0)

#define _VLV_AUD_PORT_EN_B_DBG          (VLV_DISPLAY_BASE + 0x62F20)
#define _VLV_AUD_PORT_EN_C_DBG          (VLV_DISPLAY_BASE + 0x62F30)
#define _VLV_AUD_PORT_EN_D_DBG          (VLV_DISPLAY_BASE + 0x62F34)
#define VLV_AUD_PORT_EN_DBG(port)       _MMIO_PORT3((port) - PORT_B,       \
                                                    _VLV_AUD_PORT_EN_B_DBG, \
                                                    _VLV_AUD_PORT_EN_C_DBG, \
                                                    _VLV_AUD_PORT_EN_D_DBG)
#define VLV_AMP_MUTE                    (1 << 1)

#define GEN6_BSD_RNCID                  _MMIO(0x12198)

#define GEN7_FF_THREAD_MODE             _MMIO(0x20a0)
#define   GEN7_FF_SCHED_MASK            0x0077070
#define   GEN8_FF_DS_REF_CNT_FFME       (1 << 19)
#define   GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
#define   GEN7_FF_TS_SCHED_HS1          (0x5 << 16)
#define   GEN7_FF_TS_SCHED_HS0          (0x3 << 16)
#define   GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
#define   GEN7_FF_TS_SCHED_HW           (0x0 << 16) /* Default */
#define   GEN7_FF_VS_REF_CNT_FFME       (1 << 15)
#define   GEN7_FF_VS_SCHED_HS1          (0x5 << 12)
#define   GEN7_FF_VS_SCHED_HS0          (0x3 << 12)
#define   GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
#define   GEN7_FF_VS_SCHED_HW           (0x0 << 12)
#define   GEN7_FF_DS_SCHED_HS1          (0x5 << 4)
#define   GEN7_FF_DS_SCHED_HS0          (0x3 << 4)
#define   GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4)  /* Default */
#define   GEN7_FF_DS_SCHED_HW           (0x0 << 4)

/*
 * Framebuffer compression (915+ only)
 */

#define FBC_CFB_BASE            _MMIO(0x3200) /* 4k page aligned */
#define FBC_LL_BASE             _MMIO(0x3204) /* 4k page aligned */
#define FBC_CONTROL             _MMIO(0x3208)
#define   FBC_CTL_EN                    REG_BIT(31)
#define   FBC_CTL_PERIODIC              REG_BIT(30)
#define   FBC_CTL_INTERVAL_MASK         REG_GENMASK(29, 16)
#define   FBC_CTL_INTERVAL(x)           REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
#define   FBC_CTL_STOP_ON_MOD           REG_BIT(15)
#define   FBC_CTL_UNCOMPRESSIBLE        REG_BIT(14) /* i915+ */
#define   FBC_CTL_C3_IDLE               REG_BIT(13) /* i945gm only */
#define   FBC_CTL_STRIDE_MASK           REG_GENMASK(12, 5)
#define   FBC_CTL_STRIDE(x)             REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
#define   FBC_CTL_FENCENO_MASK          REG_GENMASK(3, 0)
#define   FBC_CTL_FENCENO(x)            REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
#define FBC_COMMAND             _MMIO(0x320c)
#define   FBC_CMD_COMPRESS              REG_BIT(0)
#define FBC_STATUS              _MMIO(0x3210)
#define   FBC_STAT_COMPRESSING          REG_BIT(31)
#define   FBC_STAT_COMPRESSED           REG_BIT(30)
#define   FBC_STAT_MODIFIED             REG_BIT(29)
#define   FBC_STAT_CURRENT_LINE_MASK    REG_GENMASK(10, 0)
#define FBC_CONTROL2            _MMIO(0x3214) /* i965gm only */
#define   FBC_CTL_FENCE_DBL             REG_BIT(4)
#define   FBC_CTL_IDLE_MASK             REG_GENMASK(3, 2)
#define   FBC_CTL_IDLE_IMM              REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
#define   FBC_CTL_IDLE_FULL             REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
#define   FBC_CTL_IDLE_LINE             REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
#define   FBC_CTL_IDLE_DEBUG            REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
#define   FBC_CTL_CPU_FENCE_EN          REG_BIT(1)
#define   FBC_CTL_PLANE_MASK            REG_GENMASK(1, 0)
#define   FBC_CTL_PLANE(i9xx_plane)     REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
#define FBC_FENCE_OFF           _MMIO(0x3218)  /* i965gm only, BSpec typo has 321Bh */
#define FBC_MOD_NUM             _MMIO(0x3220)  /* i965gm only */
#define   FBC_MOD_NUM_MASK              REG_GENMASK(31, 1)
#define   FBC_MOD_NUM_VALID             REG_BIT(0)
#define FBC_TAG(i)              _MMIO(0x3300 + (i) * 4) /* 49 reisters */
#define   FBC_TAG_MASK                  REG_GENMASK(1, 0) /* 16 tags per register */
#define   FBC_TAG_MODIFIED              REG_FIELD_PREP(FBC_TAG_MASK, 0)
#define   FBC_TAG_UNCOMPRESSED          REG_FIELD_PREP(FBC_TAG_MASK, 1)
#define   FBC_TAG_UNCOMPRESSIBLE        REG_FIELD_PREP(FBC_TAG_MASK, 2)
#define   FBC_TAG_COMPRESSED            REG_FIELD_PREP(FBC_TAG_MASK, 3)

#define FBC_LL_SIZE             (1536)

/* Framebuffer compression for GM45+ */
#define DPFC_CB_BASE                    _MMIO(0x3200)
#define ILK_DPFC_CB_BASE(fbc_id)        _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
#define DPFC_CONTROL                    _MMIO(0x3208)
#define ILK_DPFC_CONTROL(fbc_id)        _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
#define   DPFC_CTL_EN                           REG_BIT(31)
#define   DPFC_CTL_PLANE_MASK_G4X               REG_BIT(30) /* g4x-snb */
#define   DPFC_CTL_PLANE_G4X(i9xx_plane)        REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
#define   DPFC_CTL_FENCE_EN_G4X                 REG_BIT(29) /* g4x-snb */
#define   DPFC_CTL_PLANE_MASK_IVB               REG_GENMASK(30, 29) /* ivb only */
#define   DPFC_CTL_PLANE_IVB(i9xx_plane)        REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
#define   DPFC_CTL_FENCE_EN_IVB                 REG_BIT(28) /* ivb+ */
#define   DPFC_CTL_PERSISTENT_MODE              REG_BIT(25) /* g4x-snb */
#define   DPFC_CTL_FALSE_COLOR                  REG_BIT(10) /* ivb+ */
#define   DPFC_CTL_SR_EN                        REG_BIT(10) /* g4x only */
#define   DPFC_CTL_SR_EXIT_DIS                  REG_BIT(9) /* g4x only */
#define   DPFC_CTL_LIMIT_MASK                   REG_GENMASK(7, 6)
#define   DPFC_CTL_LIMIT_1X                     REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
#define   DPFC_CTL_LIMIT_2X                     REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
#define   DPFC_CTL_LIMIT_4X                     REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
#define   DPFC_CTL_FENCENO_MASK                 REG_GENMASK(3, 0)
#define   DPFC_CTL_FENCENO(fence)               REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
#define DPFC_RECOMP_CTL                 _MMIO(0x320c)
#define ILK_DPFC_RECOMP_CTL(fbc_id)     _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
#define   DPFC_RECOMP_STALL_EN                  REG_BIT(27)
#define   DPFC_RECOMP_STALL_WM_MASK             REG_GENMASK(26, 16)
#define   DPFC_RECOMP_TIMER_COUNT_MASK          REG_GENMASK(5, 0)
#define DPFC_STATUS                     _MMIO(0x3210)
#define ILK_DPFC_STATUS(fbc_id)         _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
#define   DPFC_INVAL_SEG_MASK                   REG_GENMASK(26, 16)
#define   DPFC_COMP_SEG_MASK                    REG_GENMASK(10, 0)
#define DPFC_STATUS2                    _MMIO(0x3214)
#define ILK_DPFC_STATUS2(fbc_id)        _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
#define   DPFC_COMP_SEG_MASK_IVB                REG_GENMASK(11, 0)
#define DPFC_FENCE_YOFF                 _MMIO(0x3218)
#define ILK_DPFC_FENCE_YOFF(fbc_id)     _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
#define DPFC_CHICKEN                    _MMIO(0x3224)
#define ILK_DPFC_CHICKEN(fbc_id)        _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
#define   DPFC_HT_MODIFY                        REG_BIT(31) /* pre-ivb */
#define   DPFC_NUKE_ON_ANY_MODIFICATION         REG_BIT(23) /* bdw+ */
#define   DPFC_CHICKEN_COMP_DUMMY_PIXEL         REG_BIT(14) /* glk+ */
#define   DPFC_CHICKEN_FORCE_SLB_INVALIDATION   REG_BIT(13) /* icl+ */
#define   DPFC_DISABLE_DUMMY0                   REG_BIT(8) /* ivb+ */

#define GLK_FBC_STRIDE(fbc_id)  _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
#define   FBC_STRIDE_OVERRIDE   REG_BIT(15)
#define   FBC_STRIDE_MASK       REG_GENMASK(14, 0)
#define   FBC_STRIDE(x)         REG_FIELD_PREP(FBC_STRIDE_MASK, (x))

#define ILK_FBC_RT_BASE         _MMIO(0x2128)
#define   ILK_FBC_RT_VALID      REG_BIT(0)
#define   SNB_FBC_FRONT_BUFFER  REG_BIT(1)

#define ILK_DISPLAY_CHICKEN1    _MMIO(0x42000)
#define   ILK_FBCQ_DIS          (1 << 22)
#define   ILK_PABSTRETCH_DIS    REG_BIT(21)
#define   ILK_SABSTRETCH_DIS    REG_BIT(20)
#define   IVB_PRI_STRETCH_MAX_MASK      REG_GENMASK(21, 20)
#define   IVB_PRI_STRETCH_MAX_X8        REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
#define   IVB_PRI_STRETCH_MAX_X4        REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
#define   IVB_PRI_STRETCH_MAX_X2        REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
#define   IVB_PRI_STRETCH_MAX_X1        REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
#define   IVB_SPR_STRETCH_MAX_MASK      REG_GENMASK(19, 18)
#define   IVB_SPR_STRETCH_MAX_X8        REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
#define   IVB_SPR_STRETCH_MAX_X4        REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
#define   IVB_SPR_STRETCH_MAX_X2        REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
#define   IVB_SPR_STRETCH_MAX_X1        REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)


/*
 * Framebuffer compression for Sandybridge
 *
 * The following two registers are of type GTTMMADR
 */
#define SNB_DPFC_CTL_SA         _MMIO(0x100100)
#define   SNB_DPFC_FENCE_EN             REG_BIT(29)
#define   SNB_DPFC_FENCENO_MASK         REG_GENMASK(4, 0)
#define   SNB_DPFC_FENCENO(fence)       REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
#define SNB_DPFC_CPU_FENCE_OFFSET       _MMIO(0x100104)

/* Framebuffer compression for Ivybridge */
#define IVB_FBC_RT_BASE                 _MMIO(0x7020)
#define IVB_FBC_RT_BASE_UPPER           _MMIO(0x7024)

#define IPS_CTL         _MMIO(0x43408)
#define   IPS_ENABLE    (1 << 31)

#define MSG_FBC_REND_STATE(fbc_id)      _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
#define   FBC_REND_NUKE                 REG_BIT(2)
#define   FBC_REND_CACHE_CLEAN          REG_BIT(1)

/*
 * GPIO regs
 */
#define GPIO(gpio)              _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
                                      4 * (gpio))

# define GPIO_CLOCK_DIR_MASK            (1 << 0)
# define GPIO_CLOCK_DIR_IN              (0 << 1)
# define GPIO_CLOCK_DIR_OUT             (1 << 1)
# define GPIO_CLOCK_VAL_MASK            (1 << 2)
# define GPIO_CLOCK_VAL_OUT             (1 << 3)
# define GPIO_CLOCK_VAL_IN              (1 << 4)
# define GPIO_CLOCK_PULLUP_DISABLE      (1 << 5)
# define GPIO_DATA_DIR_MASK             (1 << 8)
# define GPIO_DATA_DIR_IN               (0 << 9)
# define GPIO_DATA_DIR_OUT              (1 << 9)
# define GPIO_DATA_VAL_MASK             (1 << 10)
# define GPIO_DATA_VAL_OUT              (1 << 11)
# define GPIO_DATA_VAL_IN               (1 << 12)
# define GPIO_DATA_PULLUP_DISABLE       (1 << 13)

#define GMBUS0                  _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
#define   GMBUS_AKSV_SELECT     (1 << 11)
#define   GMBUS_RATE_100KHZ     (0 << 8)
#define   GMBUS_RATE_50KHZ      (1 << 8)
#define   GMBUS_RATE_400KHZ     (2 << 8) /* reserved on Pineview */
#define   GMBUS_RATE_1MHZ       (3 << 8) /* reserved on Pineview */
#define   GMBUS_HOLD_EXT        (1 << 7) /* 300ns hold time, rsvd on Pineview */
#define   GMBUS_BYTE_CNT_OVERRIDE (1 << 6)

#define GMBUS1                  _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
#define   GMBUS_SW_CLR_INT      (1 << 31)
#define   GMBUS_SW_RDY          (1 << 30)
#define   GMBUS_ENT             (1 << 29) /* enable timeout */
#define   GMBUS_CYCLE_NONE      (0 << 25)
#define   GMBUS_CYCLE_WAIT      (1 << 25)
#define   GMBUS_CYCLE_INDEX     (2 << 25)
#define   GMBUS_CYCLE_STOP      (4 << 25)
#define   GMBUS_BYTE_COUNT_SHIFT 16
#define   GMBUS_BYTE_COUNT_MAX   256U
#define   GEN9_GMBUS_BYTE_COUNT_MAX 511U
#define   GMBUS_SLAVE_INDEX_SHIFT 8
#define   GMBUS_SLAVE_ADDR_SHIFT 1
#define   GMBUS_SLAVE_READ      (1 << 0)
#define   GMBUS_SLAVE_WRITE     (0 << 0)
#define GMBUS2                  _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
#define   GMBUS_INUSE           (1 << 15)
#define   GMBUS_HW_WAIT_PHASE   (1 << 14)
#define   GMBUS_STALL_TIMEOUT   (1 << 13)
#define   GMBUS_INT             (1 << 12)
#define   GMBUS_HW_RDY          (1 << 11)
#define   GMBUS_SATOER          (1 << 10)
#define   GMBUS_ACTIVE          (1 << 9)
#define GMBUS3                  _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
#define GMBUS4                  _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
#define   GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
#define   GMBUS_NAK_EN          (1 << 3)
#define   GMBUS_IDLE_EN         (1 << 2)
#define   GMBUS_HW_WAIT_EN      (1 << 1)
#define   GMBUS_HW_RDY_EN       (1 << 0)
#define GMBUS5                  _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
#define   GMBUS_2BYTE_INDEX_EN  (1 << 31)

/*
 * Clock control & power management
 */
#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)

#define VGA0    _MMIO(0x6000)
#define VGA1    _MMIO(0x6004)
#define VGA_PD  _MMIO(0x6010)
#define   VGA0_PD_P2_DIV_4      (1 << 7)
#define   VGA0_PD_P1_DIV_2      (1 << 5)
#define   VGA0_PD_P1_SHIFT      0
#define   VGA0_PD_P1_MASK       (0x1f << 0)
#define   VGA1_PD_P2_DIV_4      (1 << 15)
#define   VGA1_PD_P1_DIV_2      (1 << 13)
#define   VGA1_PD_P1_SHIFT      8
#define   VGA1_PD_P1_MASK       (0x1f << 8)
#define   DPLL_VCO_ENABLE               (1 << 31)
#define   DPLL_SDVO_HIGH_SPEED          (1 << 30)
#define   DPLL_DVO_2X_MODE              (1 << 30)
#define   DPLL_EXT_BUFFER_ENABLE_VLV    (1 << 30)
#define   DPLL_SYNCLOCK_ENABLE          (1 << 29)
#define   DPLL_REF_CLK_ENABLE_VLV       (1 << 29)
#define   DPLL_VGA_MODE_DIS             (1 << 28)
#define   DPLLB_MODE_DAC_SERIAL         (1 << 26) /* i915 */
#define   DPLLB_MODE_LVDS               (2 << 26) /* i915 */
#define   DPLL_MODE_MASK                (3 << 26)
#define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
#define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
#define   DPLLB_LVDS_P2_CLOCK_DIV_14    (0 << 24) /* i915 */
#define   DPLLB_LVDS_P2_CLOCK_DIV_7     (1 << 24) /* i915 */
#define   DPLL_P2_CLOCK_DIV_MASK        0x03000000 /* i915 */
#define   DPLL_FPA01_P1_POST_DIV_MASK   0x00ff0000 /* i915 */
#define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW  0x00ff8000 /* Pineview */
#define   DPLL_LOCK_VLV                 (1 << 15)
#define   DPLL_INTEGRATED_CRI_CLK_VLV   (1 << 14)
#define   DPLL_INTEGRATED_REF_CLK_VLV   (1 << 13)
#define   DPLL_SSC_REF_CLK_CHV          (1 << 13)
#define   DPLL_PORTC_READY_MASK         (0xf << 4)
#define   DPLL_PORTB_READY_MASK         (0xf)

#define   DPLL_FPA01_P1_POST_DIV_MASK_I830      0x001f0000

/* Additional CHV pll/phy registers */
#define DPIO_PHY_STATUS                 _MMIO(VLV_DISPLAY_BASE + 0x6240)
#define   DPLL_PORTD_READY_MASK         (0xf)
#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
#define   PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)    (1 << (2 * (phy) + (ch) + 27))
#define   PHY_LDO_DELAY_0NS                     0x0
#define   PHY_LDO_DELAY_200NS                   0x1
#define   PHY_LDO_DELAY_600NS                   0x2
#define   PHY_LDO_SEQ_DELAY(delay, phy)         ((delay) << (2 * (phy) + 23))
#define   PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
#define   PHY_CH_SU_PSR                         0x1
#define   PHY_CH_DEEP_PSR                       0x7
#define   PHY_CH_POWER_MODE(mode, phy, ch)      ((mode) << (6 * (phy) + 3 * (ch) + 2))
#define   PHY_COM_LANE_RESET_DEASSERT(phy)      (1 << (phy))
#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
#define   PHY_POWERGOOD(phy)    (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
#define   PHY_STATUS_CMN_LDO(phy, ch)                   (1 << (6 - (6 * (phy) + 3 * (ch))))
#define   PHY_STATUS_SPLINE_LDO(phy, ch, spline)        (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))

/*
 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
 * this field (only one bit may be set).
 */
#define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
#define   DPLL_FPA01_P1_POST_DIV_SHIFT  16
#define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
/* i830, required in DVO non-gang */
#define   PLL_P2_DIVIDE_BY_4            (1 << 23)
#define   PLL_P1_DIVIDE_BY_TWO          (1 << 21) /* i830 */
#define   PLL_REF_INPUT_DREFCLK         (0 << 13)
#define   PLL_REF_INPUT_TVCLKINA        (1 << 13) /* i830 */
#define   PLL_REF_INPUT_TVCLKINBC       (2 << 13) /* SDVO TVCLKIN */
#define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
#define   PLL_REF_INPUT_MASK            (3 << 13)
#define   PLL_LOAD_PULSE_PHASE_SHIFT            9
/* Ironlake */
# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
# define PLL_REF_SDVO_HDMI_MULTIPLIER(x)        (((x) - 1) << 9)
# define DPLL_FPA1_P1_POST_DIV_SHIFT            0
# define DPLL_FPA1_P1_POST_DIV_MASK             0xff

/*
 * Parallel to Serial Load Pulse phase selection.
 * Selects the phase for the 10X DPLL clock for the PCIe
 * digital display port. The range is 4 to 13; 10 or more
 * is just a flip delay. The default is 6
 */
#define   PLL_LOAD_PULSE_PHASE_MASK             (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
#define   DISPLAY_RATE_SELECT_FPA1              (1 << 8)
/*
 * SDVO multiplier for 945G/GM. Not used on 965.
 */
#define   SDVO_MULTIPLIER_MASK                  0x000000ff
#define   SDVO_MULTIPLIER_SHIFT_HIRES           4
#define   SDVO_MULTIPLIER_SHIFT_VGA             0

#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)

/*
 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
 *
 * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
 */
#define   DPLL_MD_UDI_DIVIDER_MASK              0x3f000000
#define   DPLL_MD_UDI_DIVIDER_SHIFT             24
/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
#define   DPLL_MD_VGA_UDI_DIVIDER_MASK          0x003f0000
#define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT         16
/*
 * SDVO/UDI pixel multiplier.
 *
 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
 * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
 * dummy bytes in the datastream at an increased clock rate, with both sides of
 * the link knowing how many bytes are fill.
 *
 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
 * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
 * through an SDVO command.
 *
 * This register field has values of multiplication factor minus 1, with
 * a maximum multiplier of 5 for SDVO.
 */
#define   DPLL_MD_UDI_MULTIPLIER_MASK           0x00003f00
#define   DPLL_MD_UDI_MULTIPLIER_SHIFT          8
/*
 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
 * This best be set to the default value (3) or the CRT won't work. No,
 * I don't entirely understand what this does...
 */
#define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK       0x0000003f
#define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT      0

#define RAWCLK_FREQ_VLV         _MMIO(VLV_DISPLAY_BASE + 0x6024)

#define _FPA0   0x6040
#define _FPA1   0x6044
#define _FPB0   0x6048
#define _FPB1   0x604c
#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
#define   FP_N_DIV_MASK         0x003f0000
#define   FP_N_PINEVIEW_DIV_MASK        0x00ff0000
#define   FP_N_DIV_SHIFT                16
#define   FP_M1_DIV_MASK        0x00003f00
#define   FP_M1_DIV_SHIFT                8
#define   FP_M2_DIV_MASK        0x0000003f
#define   FP_M2_PINEVIEW_DIV_MASK       0x000000ff
#define   FP_M2_DIV_SHIFT                0
#define DPLL_TEST       _MMIO(0x606c)
#define   DPLLB_TEST_SDVO_DIV_1         (0 << 22)
#define   DPLLB_TEST_SDVO_DIV_2         (1 << 22)
#define   DPLLB_TEST_SDVO_DIV_4         (2 << 22)
#define   DPLLB_TEST_SDVO_DIV_MASK      (3 << 22)
#define   DPLLB_TEST_N_BYPASS           (1 << 19)
#define   DPLLB_TEST_M_BYPASS           (1 << 18)
#define   DPLLB_INPUT_BUFFER_ENABLE     (1 << 16)
#define   DPLLA_TEST_N_BYPASS           (1 << 3)
#define   DPLLA_TEST_M_BYPASS           (1 << 2)
#define   DPLLA_INPUT_BUFFER_ENABLE     (1 << 0)
#define D_STATE         _MMIO(0x6104)
#define  DSTATE_GFX_RESET_I830                  (1 << 6)
#define  DSTATE_PLL_D3_OFF                      (1 << 3)
#define  DSTATE_GFX_CLOCK_GATING                (1 << 1)
#define  DSTATE_DOT_CLOCK_GATING                (1 << 0)
#define DSPCLK_GATE_D   _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
# define DPUNIT_B_CLOCK_GATE_DISABLE            (1 << 30) /* 965 */
# define VSUNIT_CLOCK_GATE_DISABLE              (1 << 29) /* 965 */
# define VRHUNIT_CLOCK_GATE_DISABLE             (1 << 28) /* 965 */
# define VRDUNIT_CLOCK_GATE_DISABLE             (1 << 27) /* 965 */
# define AUDUNIT_CLOCK_GATE_DISABLE             (1 << 26) /* 965 */
# define DPUNIT_A_CLOCK_GATE_DISABLE            (1 << 25) /* 965 */
# define DPCUNIT_CLOCK_GATE_DISABLE             (1 << 24) /* 965 */
# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE       (1 << 24) /* pnv */
# define TVRUNIT_CLOCK_GATE_DISABLE             (1 << 23) /* 915-945 */
# define TVCUNIT_CLOCK_GATE_DISABLE             (1 << 22) /* 915-945 */
# define TVFUNIT_CLOCK_GATE_DISABLE             (1 << 21) /* 915-945 */
# define TVEUNIT_CLOCK_GATE_DISABLE             (1 << 20) /* 915-945 */
# define DVSUNIT_CLOCK_GATE_DISABLE             (1 << 19) /* 915-945 */
# define DSSUNIT_CLOCK_GATE_DISABLE             (1 << 18) /* 915-945 */
# define DDBUNIT_CLOCK_GATE_DISABLE             (1 << 17) /* 915-945 */
# define DPRUNIT_CLOCK_GATE_DISABLE             (1 << 16) /* 915-945 */
# define DPFUNIT_CLOCK_GATE_DISABLE             (1 << 15) /* 915-945 */
# define DPBMUNIT_CLOCK_GATE_DISABLE            (1 << 14) /* 915-945 */
# define DPLSUNIT_CLOCK_GATE_DISABLE            (1 << 13) /* 915-945 */
# define DPLUNIT_CLOCK_GATE_DISABLE             (1 << 12) /* 915-945 */
# define DPOUNIT_CLOCK_GATE_DISABLE             (1 << 11)
# define DPBUNIT_CLOCK_GATE_DISABLE             (1 << 10)
# define DCUNIT_CLOCK_GATE_DISABLE              (1 << 9)
# define DPUNIT_CLOCK_GATE_DISABLE              (1 << 8)
# define VRUNIT_CLOCK_GATE_DISABLE              (1 << 7) /* 915+: reserved */
# define OVHUNIT_CLOCK_GATE_DISABLE             (1 << 6) /* 830-865 */
# define DPIOUNIT_CLOCK_GATE_DISABLE            (1 << 6) /* 915-945 */
# define OVFUNIT_CLOCK_GATE_DISABLE             (1 << 5)
# define OVBUNIT_CLOCK_GATE_DISABLE             (1 << 4)
/*
 * This bit must be set on the 830 to prevent hangs when turning off the
 * overlay scaler.
 */
# define OVRUNIT_CLOCK_GATE_DISABLE             (1 << 3)
# define OVCUNIT_CLOCK_GATE_DISABLE             (1 << 2)
# define OVUUNIT_CLOCK_GATE_DISABLE             (1 << 1)
# define ZVUNIT_CLOCK_GATE_DISABLE              (1 << 0) /* 830 */
# define OVLUNIT_CLOCK_GATE_DISABLE             (1 << 0) /* 845,865 */

#define RENCLK_GATE_D1          _MMIO(0x6204)
# define BLITTER_CLOCK_GATE_DISABLE             (1 << 13) /* 945GM only */
# define MPEG_CLOCK_GATE_DISABLE                (1 << 12) /* 945GM only */
# define PC_FE_CLOCK_GATE_DISABLE               (1 << 11)
# define PC_BE_CLOCK_GATE_DISABLE               (1 << 10)
# define WINDOWER_CLOCK_GATE_DISABLE            (1 << 9)
# define INTERPOLATOR_CLOCK_GATE_DISABLE        (1 << 8)
# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE    (1 << 7)
# define MOTION_COMP_CLOCK_GATE_DISABLE         (1 << 6)
# define MAG_CLOCK_GATE_DISABLE                 (1 << 5)
/* This bit must be unset on 855,865 */
# define MECI_CLOCK_GATE_DISABLE                (1 << 4)
# define DCMP_CLOCK_GATE_DISABLE                (1 << 3)
# define MEC_CLOCK_GATE_DISABLE                 (1 << 2)
# define MECO_CLOCK_GATE_DISABLE                (1 << 1)
/* This bit must be set on 855,865. */
# define SV_CLOCK_GATE_DISABLE                  (1 << 0)
# define I915_MPEG_CLOCK_GATE_DISABLE           (1 << 16)
# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE      (1 << 15)
# define I915_MOTION_COMP_CLOCK_GATE_DISABLE    (1 << 14)
# define I915_BD_BF_CLOCK_GATE_DISABLE          (1 << 13)
# define I915_SF_SE_CLOCK_GATE_DISABLE          (1 << 12)
# define I915_WM_CLOCK_GATE_DISABLE             (1 << 11)
# define I915_IZ_CLOCK_GATE_DISABLE             (1 << 10)
# define I915_PI_CLOCK_GATE_DISABLE             (1 << 9)
# define I915_DI_CLOCK_GATE_DISABLE             (1 << 8)
# define I915_SH_SV_CLOCK_GATE_DISABLE          (1 << 7)
# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE    (1 << 6)
# define I915_SC_CLOCK_GATE_DISABLE             (1 << 5)
# define I915_FL_CLOCK_GATE_DISABLE             (1 << 4)
# define I915_DM_CLOCK_GATE_DISABLE             (1 << 3)
# define I915_PS_CLOCK_GATE_DISABLE             (1 << 2)
# define I915_CC_CLOCK_GATE_DISABLE             (1 << 1)
# define I915_BY_CLOCK_GATE_DISABLE             (1 << 0)

# define I965_RCZ_CLOCK_GATE_DISABLE            (1 << 30)
/* This bit must always be set on 965G/965GM */
# define I965_RCC_CLOCK_GATE_DISABLE            (1 << 29)
# define I965_RCPB_CLOCK_GATE_DISABLE           (1 << 28)
# define I965_DAP_CLOCK_GATE_DISABLE            (1 << 27)
# define I965_ROC_CLOCK_GATE_DISABLE            (1 << 26)
# define I965_GW_CLOCK_GATE_DISABLE             (1 << 25)
# define I965_TD_CLOCK_GATE_DISABLE             (1 << 24)
/* This bit must always be set on 965G */
# define I965_ISC_CLOCK_GATE_DISABLE            (1 << 23)
# define I965_IC_CLOCK_GATE_DISABLE             (1 << 22)
# define I965_EU_CLOCK_GATE_DISABLE             (1 << 21)
# define I965_IF_CLOCK_GATE_DISABLE             (1 << 20)
# define I965_TC_CLOCK_GATE_DISABLE             (1 << 19)
# define I965_SO_CLOCK_GATE_DISABLE             (1 << 17)
# define I965_FBC_CLOCK_GATE_DISABLE            (1 << 16)
# define I965_MARI_CLOCK_GATE_DISABLE           (1 << 15)
# define I965_MASF_CLOCK_GATE_DISABLE           (1 << 14)
# define I965_MAWB_CLOCK_GATE_DISABLE           (1 << 13)
# define I965_EM_CLOCK_GATE_DISABLE             (1 << 12)
# define I965_UC_CLOCK_GATE_DISABLE             (1 << 11)
# define I965_SI_CLOCK_GATE_DISABLE             (1 << 6)
# define I965_MT_CLOCK_GATE_DISABLE             (1 << 5)
# define I965_PL_CLOCK_GATE_DISABLE             (1 << 4)
# define I965_DG_CLOCK_GATE_DISABLE             (1 << 3)
# define I965_QC_CLOCK_GATE_DISABLE             (1 << 2)
# define I965_FT_CLOCK_GATE_DISABLE             (1 << 1)
# define I965_DM_CLOCK_GATE_DISABLE             (1 << 0)

#define RENCLK_GATE_D2          _MMIO(0x6208)
#define VF_UNIT_CLOCK_GATE_DISABLE              (1 << 9)
#define GS_UNIT_CLOCK_GATE_DISABLE              (1 << 7)
#define CL_UNIT_CLOCK_GATE_DISABLE              (1 << 6)

#define VDECCLK_GATE_D          _MMIO(0x620C)           /* g4x only */
#define  VCP_UNIT_CLOCK_GATE_DISABLE            (1 << 4)

#define RAMCLK_GATE_D           _MMIO(0x6210)           /* CRL only */
#define DEUC                    _MMIO(0x6214)          /* CRL only */

#define FW_BLC_SELF_VLV         _MMIO(VLV_DISPLAY_BASE + 0x6500)
#define  FW_CSPWRDWNEN          (1 << 15)

#define MI_ARB_VLV              _MMIO(VLV_DISPLAY_BASE + 0x6504)

#define CZCLK_CDCLK_FREQ_RATIO  _MMIO(VLV_DISPLAY_BASE + 0x6508)
#define   CDCLK_FREQ_SHIFT      4
#define   CDCLK_FREQ_MASK       (0x1f << CDCLK_FREQ_SHIFT)
#define   CZCLK_FREQ_MASK       0xf

#define GCI_CONTROL             _MMIO(VLV_DISPLAY_BASE + 0x650C)
#define   PFI_CREDIT_63         (9 << 28)               /* chv only */
#define   PFI_CREDIT_31         (8 << 28)               /* chv only */
#define   PFI_CREDIT(x)         (((x) - 8) << 28)       /* 8-15 */
#define   PFI_CREDIT_RESEND     (1 << 27)
#define   VGA_FAST_MODE_DISABLE (1 << 14)

#define GMBUSFREQ_VLV           _MMIO(VLV_DISPLAY_BASE + 0x6510)

/*
 * Palette regs
 */
#define _PALETTE_A              0xa000
#define _PALETTE_B              0xa800
#define _CHV_PALETTE_C          0xc000
#define PALETTE_RED_MASK        REG_GENMASK(23, 16)
#define PALETTE_GREEN_MASK      REG_GENMASK(15, 8)
#define PALETTE_BLUE_MASK       REG_GENMASK(7, 0)
#define PALETTE(pipe, i)        _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
                                      _PICK((pipe), _PALETTE_A,         \
                                            _PALETTE_B, _CHV_PALETTE_C) + \
                                      (i) * 4)

#define PEG_BAND_GAP_DATA       _MMIO(0x14d68)

#define BXT_RP_STATE_CAP        _MMIO(0x138170)
#define GEN9_RP_STATE_LIMITS    _MMIO(0x138148)
#define XEHPSDV_RP_STATE_CAP    _MMIO(0x250014)

#define GT0_PERF_LIMIT_REASONS          _MMIO(0x1381a8)
#define   GT0_PERF_LIMIT_REASONS_MASK   0xde3
#define   PROCHOT_MASK                  REG_BIT(1)
#define   THERMAL_LIMIT_MASK            REG_BIT(2)
#define   RATL_MASK                     REG_BIT(6)
#define   VR_THERMALERT_MASK            REG_BIT(7)
#define   VR_TDC_MASK                   REG_BIT(8)
#define   POWER_LIMIT_4_MASK            REG_BIT(9)
#define   POWER_LIMIT_1_MASK            REG_BIT(11)
#define   POWER_LIMIT_2_MASK            REG_BIT(12)

#define CHV_CLK_CTL1                    _MMIO(0x101100)
#define VLV_CLK_CTL2                    _MMIO(0x101104)
#define   CLK_CTL2_CZCOUNT_30NS_SHIFT   28

/*
 * Overlay regs
 */

#define OVADD                   _MMIO(0x30000)
#define DOVSTA                  _MMIO(0x30008)
#define OC_BUF                  (0x3 << 20)
#define OGAMC5                  _MMIO(0x30010)
#define OGAMC4                  _MMIO(0x30014)
#define OGAMC3                  _MMIO(0x30018)
#define OGAMC2                  _MMIO(0x3001c)
#define OGAMC1                  _MMIO(0x30020)
#define OGAMC0                  _MMIO(0x30024)

/*
 * GEN9 clock gating regs
 */
#define GEN9_CLKGATE_DIS_0              _MMIO(0x46530)
#define   DARBF_GATING_DIS              (1 << 27)
#define   PWM2_GATING_DIS               (1 << 14)
#define   PWM1_GATING_DIS               (1 << 13)

#define GEN9_CLKGATE_DIS_3              _MMIO(0x46538)
#define   TGL_VRH_GATING_DIS            REG_BIT(31)
#define   DPT_GATING_DIS                REG_BIT(22)

#define GEN9_CLKGATE_DIS_4              _MMIO(0x4653C)
#define   BXT_GMBUS_GATING_DIS          (1 << 14)

#define GEN9_CLKGATE_DIS_5              _MMIO(0x46540)
#define   DPCE_GATING_DIS               REG_BIT(17)

#define _CLKGATE_DIS_PSL_A              0x46520
#define _CLKGATE_DIS_PSL_B              0x46524
#define _CLKGATE_DIS_PSL_C              0x46528
#define   DUPS1_GATING_DIS              (1 << 15)
#define   DUPS2_GATING_DIS              (1 << 19)
#define   DUPS3_GATING_DIS              (1 << 23)
#define   CURSOR_GATING_DIS             REG_BIT(28)
#define   DPF_GATING_DIS                (1 << 10)
#define   DPF_RAM_GATING_DIS            (1 << 9)
#define   DPFR_GATING_DIS               (1 << 8)

#define CLKGATE_DIS_PSL(pipe) \
        _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)

/*
 * Display engine regs
 */

/* Pipe A CRC regs */
#define _PIPE_CRC_CTL_A                 0x60050
#define   PIPE_CRC_ENABLE               REG_BIT(31)
/* skl+ source selection */
#define   PIPE_CRC_SOURCE_MASK_SKL      REG_GENMASK(30, 28)
#define   PIPE_CRC_SOURCE_PLANE_1_SKL   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
#define   PIPE_CRC_SOURCE_PLANE_2_SKL   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2)
#define   PIPE_CRC_SOURCE_DMUX_SKL      REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4)
#define   PIPE_CRC_SOURCE_PLANE_3_SKL   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6)
#define   PIPE_CRC_SOURCE_PLANE_4_SKL   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7)
#define   PIPE_CRC_SOURCE_PLANE_5_SKL   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5)
#define   PIPE_CRC_SOURCE_PLANE_6_SKL   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3)
#define   PIPE_CRC_SOURCE_PLANE_7_SKL   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1)
/* ivb+ source selection */
#define   PIPE_CRC_SOURCE_MASK_IVB      REG_GENMASK(30, 29)
#define   PIPE_CRC_SOURCE_PRIMARY_IVB   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
#define   PIPE_CRC_SOURCE_SPRITE_IVB    REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1)
#define   PIPE_CRC_SOURCE_PF_IVB        REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2)
/* ilk+ source selection */
#define   PIPE_CRC_SOURCE_MASK_ILK      REG_GENMASK(30, 28)
#define   PIPE_CRC_SOURCE_PRIMARY_ILK   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
#define   PIPE_CRC_SOURCE_SPRITE_ILK    REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1)
#define   PIPE_CRC_SOURCE_PIPE_ILK      REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2)
/* embedded DP port on the north display block */
#define   PIPE_CRC_SOURCE_PORT_A_ILK    REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4)
#define   PIPE_CRC_SOURCE_FDI_ILK       REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5)
/* vlv source selection */
#define   PIPE_CRC_SOURCE_MASK_VLV      REG_GENMASK(30, 27)
#define   PIPE_CRC_SOURCE_PIPE_VLV      REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
#define   PIPE_CRC_SOURCE_HDMIB_VLV     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1)
#define   PIPE_CRC_SOURCE_HDMIC_VLV     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2)
/* with DP port the pipe source is invalid */
#define   PIPE_CRC_SOURCE_DP_D_VLV      REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3)
#define   PIPE_CRC_SOURCE_DP_B_VLV      REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6)
#define   PIPE_CRC_SOURCE_DP_C_VLV      REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7)
/* gen3+ source selection */
#define   PIPE_CRC_SOURCE_MASK_I9XX     REG_GENMASK(30, 28)
#define   PIPE_CRC_SOURCE_PIPE_I9XX     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
#define   PIPE_CRC_SOURCE_SDVOB_I9XX    REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1)
#define   PIPE_CRC_SOURCE_SDVOC_I9XX    REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2)
/* with DP/TV port the pipe source is invalid */
#define   PIPE_CRC_SOURCE_DP_D_G4X      REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3)
#define   PIPE_CRC_SOURCE_TV_PRE        REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4)
#define   PIPE_CRC_SOURCE_TV_POST       REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5)
#define   PIPE_CRC_SOURCE_DP_B_G4X      REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6)
#define   PIPE_CRC_SOURCE_DP_C_G4X      REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7)
/* gen2 doesn't have source selection bits */
#define   PIPE_CRC_INCLUDE_BORDER_I8XX  REG_BIT(30)

#define _PIPE_CRC_RES_1_A_IVB           0x60064
#define _PIPE_CRC_RES_2_A_IVB           0x60068
#define _PIPE_CRC_RES_3_A_IVB           0x6006c
#define _PIPE_CRC_RES_4_A_IVB           0x60070
#define _PIPE_CRC_RES_5_A_IVB           0x60074

#define _PIPE_CRC_RES_RED_A             0x60060
#define _PIPE_CRC_RES_GREEN_A           0x60064
#define _PIPE_CRC_RES_BLUE_A            0x60068
#define _PIPE_CRC_RES_RES1_A_I915       0x6006c
#define _PIPE_CRC_RES_RES2_A_G4X        0x60080

/* Pipe B CRC regs */
#define _PIPE_CRC_RES_1_B_IVB           0x61064
#define _PIPE_CRC_RES_2_B_IVB           0x61068
#define _PIPE_CRC_RES_3_B_IVB           0x6106c
#define _PIPE_CRC_RES_4_B_IVB           0x61070
#define _PIPE_CRC_RES_5_B_IVB           0x61074

#define PIPE_CRC_CTL(pipe)              _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
#define PIPE_CRC_RES_1_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
#define PIPE_CRC_RES_2_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
#define PIPE_CRC_RES_3_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
#define PIPE_CRC_RES_4_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
#define PIPE_CRC_RES_5_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)

#define PIPE_CRC_RES_RED(pipe)          _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
#define PIPE_CRC_RES_GREEN(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
#define PIPE_CRC_RES_BLUE(pipe)         _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
#define PIPE_CRC_RES_RES1_I915(pipe)    _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
#define PIPE_CRC_RES_RES2_G4X(pipe)     _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)

/* Pipe A timing regs */
#define _HTOTAL_A       0x60000
#define _HBLANK_A       0x60004
#define _HSYNC_A        0x60008
#define _VTOTAL_A       0x6000c

#define _VBLANK_A       0x60010
#define _VSYNC_A        0x60014
#define _EXITLINE_A     0x60018
#define _PIPEASRC       0x6001c
#define   PIPESRC_WIDTH_MASK    REG_GENMASK(31, 16)
#define   PIPESRC_WIDTH(w)      REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
#define   PIPESRC_HEIGHT_MASK   REG_GENMASK(15, 0)
#define   PIPESRC_HEIGHT(h)     REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
#define _BCLRPAT_A      0x60020
#define _VSYNCSHIFT_A   0x60028
#define _PIPE_MULT_A    0x6002c

/* Pipe B timing regs */
#define _HTOTAL_B       0x61000
#define _HBLANK_B       0x61004
#define _HSYNC_B        0x61008
#define _VTOTAL_B       0x6100c
#define _VBLANK_B       0x61010
#define _VSYNC_B        0x61014
#define _PIPEBSRC       0x6101c
#define _BCLRPAT_B      0x61020
#define _VSYNCSHIFT_B   0x61028
#define _PIPE_MULT_B    0x6102c

/* DSI 0 timing regs */
#define _HTOTAL_DSI0            0x6b000
#define _HSYNC_DSI0             0x6b008
#define _VTOTAL_DSI0            0x6b00c
#define _VSYNC_DSI0             0x6b014
#define _VSYNCSHIFT_DSI0        0x6b028

/* DSI 1 timing regs */
#define _HTOTAL_DSI1            0x6b800
#define _HSYNC_DSI1             0x6b808
#define _VTOTAL_DSI1            0x6b80c
#define _VSYNC_DSI1             0x6b814
#define _VSYNCSHIFT_DSI1        0x6b828

#define TRANSCODER_A_OFFSET 0x60000
#define TRANSCODER_B_OFFSET 0x61000
#define TRANSCODER_C_OFFSET 0x62000
#define CHV_TRANSCODER_C_OFFSET 0x63000
#define TRANSCODER_D_OFFSET 0x63000
#define TRANSCODER_EDP_OFFSET 0x6f000
#define TRANSCODER_DSI0_OFFSET  0x6b000
#define TRANSCODER_DSI1_OFFSET  0x6b800

#define HTOTAL(trans)           _MMIO_TRANS2(trans, _HTOTAL_A)
#define HBLANK(trans)           _MMIO_TRANS2(trans, _HBLANK_A)
#define HSYNC(trans)            _MMIO_TRANS2(trans, _HSYNC_A)
#define VTOTAL(trans)           _MMIO_TRANS2(trans, _VTOTAL_A)
#define VBLANK(trans)           _MMIO_TRANS2(trans, _VBLANK_A)
#define VSYNC(trans)            _MMIO_TRANS2(trans, _VSYNC_A)
#define BCLRPAT(trans)          _MMIO_TRANS2(trans, _BCLRPAT_A)
#define VSYNCSHIFT(trans)       _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
#define PIPESRC(trans)          _MMIO_TRANS2(trans, _PIPEASRC)
#define PIPE_MULT(trans)        _MMIO_TRANS2(trans, _PIPE_MULT_A)

#define EXITLINE(trans)         _MMIO_TRANS2(trans, _EXITLINE_A)
#define   EXITLINE_ENABLE       REG_BIT(31)
#define   EXITLINE_MASK         REG_GENMASK(12, 0)
#define   EXITLINE_SHIFT        0

/* VRR registers */
#define _TRANS_VRR_CTL_A                0x60420
#define _TRANS_VRR_CTL_B                0x61420
#define _TRANS_VRR_CTL_C                0x62420
#define _TRANS_VRR_CTL_D                0x63420
#define TRANS_VRR_CTL(trans)                    _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
#define   VRR_CTL_VRR_ENABLE                    REG_BIT(31)
#define   VRR_CTL_IGN_MAX_SHIFT                 REG_BIT(30)
#define   VRR_CTL_FLIP_LINE_EN                  REG_BIT(29)
#define   VRR_CTL_PIPELINE_FULL_MASK            REG_GENMASK(10, 3)
#define   VRR_CTL_PIPELINE_FULL(x)              REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
#define   VRR_CTL_PIPELINE_FULL_OVERRIDE        REG_BIT(0)
#define   XELPD_VRR_CTL_VRR_GUARDBAND_MASK      REG_GENMASK(15, 0)
#define   XELPD_VRR_CTL_VRR_GUARDBAND(x)        REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))

#define _TRANS_VRR_VMAX_A               0x60424
#define _TRANS_VRR_VMAX_B               0x61424
#define _TRANS_VRR_VMAX_C               0x62424
#define _TRANS_VRR_VMAX_D               0x63424
#define TRANS_VRR_VMAX(trans)           _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A)
#define   VRR_VMAX_MASK                 REG_GENMASK(19, 0)

#define _TRANS_VRR_VMIN_A               0x60434
#define _TRANS_VRR_VMIN_B               0x61434
#define _TRANS_VRR_VMIN_C               0x62434
#define _TRANS_VRR_VMIN_D               0x63434
#define TRANS_VRR_VMIN(trans)           _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A)
#define   VRR_VMIN_MASK                 REG_GENMASK(15, 0)

#define _TRANS_VRR_VMAXSHIFT_A          0x60428
#define _TRANS_VRR_VMAXSHIFT_B          0x61428
#define _TRANS_VRR_VMAXSHIFT_C          0x62428
#define _TRANS_VRR_VMAXSHIFT_D          0x63428
#define TRANS_VRR_VMAXSHIFT(trans)      _MMIO_TRANS2(trans, \
                                        _TRANS_VRR_VMAXSHIFT_A)
#define   VRR_VMAXSHIFT_DEC_MASK        REG_GENMASK(29, 16)
#define   VRR_VMAXSHIFT_DEC             REG_BIT(16)
#define   VRR_VMAXSHIFT_INC_MASK        REG_GENMASK(12, 0)

#define _TRANS_VRR_STATUS_A             0x6042C
#define _TRANS_VRR_STATUS_B             0x6142C
#define _TRANS_VRR_STATUS_C             0x6242C
#define _TRANS_VRR_STATUS_D             0x6342C
#define TRANS_VRR_STATUS(trans)         _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A)
#define   VRR_STATUS_VMAX_REACHED       REG_BIT(31)
#define   VRR_STATUS_NOFLIP_TILL_BNDR   REG_BIT(30)
#define   VRR_STATUS_FLIP_BEF_BNDR      REG_BIT(29)
#define   VRR_STATUS_NO_FLIP_FRAME      REG_BIT(28)
#define   VRR_STATUS_VRR_EN_LIVE        REG_BIT(27)
#define   VRR_STATUS_FLIPS_SERVICED     REG_BIT(26)
#define   VRR_STATUS_VBLANK_MASK        REG_GENMASK(22, 20)
#define   STATUS_FSM_IDLE               REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
#define   STATUS_FSM_WAIT_TILL_FDB      REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
#define   STATUS_FSM_WAIT_TILL_FS       REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
#define   STATUS_FSM_WAIT_TILL_FLIP     REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
#define   STATUS_FSM_PIPELINE_FILL      REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
#define   STATUS_FSM_ACTIVE             REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
#define   STATUS_FSM_LEGACY_VBLANK      REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)

#define _TRANS_VRR_VTOTAL_PREV_A        0x60480
#define _TRANS_VRR_VTOTAL_PREV_B        0x61480
#define _TRANS_VRR_VTOTAL_PREV_C        0x62480
#define _TRANS_VRR_VTOTAL_PREV_D        0x63480
#define TRANS_VRR_VTOTAL_PREV(trans)    _MMIO_TRANS2(trans, \
                                        _TRANS_VRR_VTOTAL_PREV_A)
#define   VRR_VTOTAL_FLIP_BEFR_BNDR     REG_BIT(31)
#define   VRR_VTOTAL_FLIP_AFTER_BNDR    REG_BIT(30)
#define   VRR_VTOTAL_FLIP_AFTER_DBLBUF  REG_BIT(29)
#define   VRR_VTOTAL_PREV_FRAME_MASK    REG_GENMASK(19, 0)

#define _TRANS_VRR_FLIPLINE_A           0x60438
#define _TRANS_VRR_FLIPLINE_B           0x61438
#define _TRANS_VRR_FLIPLINE_C           0x62438
#define _TRANS_VRR_FLIPLINE_D           0x63438
#define TRANS_VRR_FLIPLINE(trans)       _MMIO_TRANS2(trans, \
                                        _TRANS_VRR_FLIPLINE_A)
#define   VRR_FLIPLINE_MASK             REG_GENMASK(19, 0)

#define _TRANS_VRR_STATUS2_A            0x6043C
#define _TRANS_VRR_STATUS2_B            0x6143C
#define _TRANS_VRR_STATUS2_C            0x6243C
#define _TRANS_VRR_STATUS2_D            0x6343C
#define TRANS_VRR_STATUS2(trans)        _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
#define   VRR_STATUS2_VERT_LN_CNT_MASK  REG_GENMASK(19, 0)

#define _TRANS_PUSH_A                   0x60A70
#define _TRANS_PUSH_B                   0x61A70
#define _TRANS_PUSH_C                   0x62A70
#define _TRANS_PUSH_D                   0x63A70
#define TRANS_PUSH(trans)               _MMIO_TRANS2(trans, _TRANS_PUSH_A)
#define   TRANS_PUSH_EN                 REG_BIT(31)
#define   TRANS_PUSH_SEND               REG_BIT(30)

/*
 * HSW+ eDP PSR registers
 *
 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
 * instance of it
 */
#define _SRD_CTL_A                              0x60800
#define _SRD_CTL_EDP                            0x6f800
#define EDP_PSR_CTL(tran)                       _MMIO(_TRANS2(tran, _SRD_CTL_A))
#define   EDP_PSR_ENABLE                        (1 << 31)
#define   BDW_PSR_SINGLE_FRAME                  (1 << 30)
#define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK   (1 << 29) /* SW can't modify */
#define   EDP_PSR_LINK_STANDBY                  (1 << 27)
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK      (3 << 25)
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES   (0 << 25)
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES   (1 << 25)
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES   (2 << 25)
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES   (3 << 25)
#define   EDP_PSR_MAX_SLEEP_TIME_SHIFT          20
#define   EDP_PSR_SKIP_AUX_EXIT                 (1 << 12)
#define   EDP_PSR_TP1_TP2_SEL                   (0 << 11)
#define   EDP_PSR_TP1_TP3_SEL                   (1 << 11)
#define   EDP_PSR_CRC_ENABLE                    (1 << 10) /* BDW+ */
#define   EDP_PSR_TP2_TP3_TIME_500us            (0 << 8)
#define   EDP_PSR_TP2_TP3_TIME_100us            (1 << 8)
#define   EDP_PSR_TP2_TP3_TIME_2500us           (2 << 8)
#define   EDP_PSR_TP2_TP3_TIME_0us              (3 << 8)
#define   EDP_PSR_TP4_TIME_0US                  (3 << 6) /* ICL+ */
#define   EDP_PSR_TP1_TIME_500us                (0 << 4)
#define   EDP_PSR_TP1_TIME_100us                (1 << 4)
#define   EDP_PSR_TP1_TIME_2500us               (2 << 4)
#define   EDP_PSR_TP1_TIME_0us                  (3 << 4)
#define   EDP_PSR_IDLE_FRAME_SHIFT              0

/*
 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
 * to transcoder and bits defined for each one as if using no shift (i.e. as if
 * it was for TRANSCODER_EDP)
 */
#define EDP_PSR_IMR                             _MMIO(0x64834)
#define EDP_PSR_IIR                             _MMIO(0x64838)
#define _PSR_IMR_A                              0x60814
#define _PSR_IIR_A                              0x60818
#define TRANS_PSR_IMR(tran)                     _MMIO_TRANS2(tran, _PSR_IMR_A)
#define TRANS_PSR_IIR(tran)                     _MMIO_TRANS2(tran, _PSR_IIR_A)
#define   _EDP_PSR_TRANS_SHIFT(trans)           ((trans) == TRANSCODER_EDP ? \
                                                 0 : ((trans) - TRANSCODER_A + 1) * 8)
#define   EDP_PSR_TRANS_MASK(trans)             (0x7 << _EDP_PSR_TRANS_SHIFT(trans))
#define   EDP_PSR_ERROR(trans)                  (0x4 << _EDP_PSR_TRANS_SHIFT(trans))
#define   EDP_PSR_POST_EXIT(trans)              (0x2 << _EDP_PSR_TRANS_SHIFT(trans))
#define   EDP_PSR_PRE_ENTRY(trans)              (0x1 << _EDP_PSR_TRANS_SHIFT(trans))

#define _SRD_AUX_DATA_A                         0x60814
#define _SRD_AUX_DATA_EDP                       0x6f814
#define EDP_PSR_AUX_DATA(tran, i)               _MMIO(_TRANS2(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */

#define _SRD_STATUS_A                           0x60840
#define _SRD_STATUS_EDP                         0x6f840
#define EDP_PSR_STATUS(tran)                    _MMIO(_TRANS2(tran, _SRD_STATUS_A))
#define   EDP_PSR_STATUS_STATE_MASK             (7 << 29)
#define   EDP_PSR_STATUS_STATE_SHIFT            29
#define   EDP_PSR_STATUS_STATE_IDLE             (0 << 29)
#define   EDP_PSR_STATUS_STATE_SRDONACK         (1 << 29)
#define   EDP_PSR_STATUS_STATE_SRDENT           (2 << 29)
#define   EDP_PSR_STATUS_STATE_BUFOFF           (3 << 29)
#define   EDP_PSR_STATUS_STATE_BUFON            (4 << 29)
#define   EDP_PSR_STATUS_STATE_AUXACK           (5 << 29)
#define   EDP_PSR_STATUS_STATE_SRDOFFACK        (6 << 29)
#define   EDP_PSR_STATUS_LINK_MASK              (3 << 26)
#define   EDP_PSR_STATUS_LINK_FULL_OFF          (0 << 26)
#define   EDP_PSR_STATUS_LINK_FULL_ON           (1 << 26)
#define   EDP_PSR_STATUS_LINK_STANDBY           (2 << 26)
#define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT  20
#define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK   0x1f
#define   EDP_PSR_STATUS_COUNT_SHIFT            16
#define   EDP_PSR_STATUS_COUNT_MASK             0xf
#define   EDP_PSR_STATUS_AUX_ERROR              (1 << 15)
#define   EDP_PSR_STATUS_AUX_SENDING            (1 << 12)
#define   EDP_PSR_STATUS_SENDING_IDLE           (1 << 9)
#define   EDP_PSR_STATUS_SENDING_TP2_TP3        (1 << 8)
#define   EDP_PSR_STATUS_SENDING_TP1            (1 << 4)
#define   EDP_PSR_STATUS_IDLE_MASK              0xf

#define _SRD_PERF_CNT_A                 0x60844
#define _SRD_PERF_CNT_EDP               0x6f844
#define EDP_PSR_PERF_CNT(tran)          _MMIO(_TRANS2(tran, _SRD_PERF_CNT_A))
#define   EDP_PSR_PERF_CNT_MASK         0xffffff

/* PSR_MASK on SKL+ */
#define _SRD_DEBUG_A                            0x60860
#define _SRD_DEBUG_EDP                          0x6f860
#define EDP_PSR_DEBUG(tran)                     _MMIO(_TRANS2(tran, _SRD_DEBUG_A))
#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1 << 28)
#define   EDP_PSR_DEBUG_MASK_LPSP              (1 << 27)
#define   EDP_PSR_DEBUG_MASK_MEMUP             (1 << 26)
#define   EDP_PSR_DEBUG_MASK_HPD               (1 << 25)
#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1 << 16) /* Reserved in ICL+ */
#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */

#define _PSR2_CTL_A                             0x60900
#define _PSR2_CTL_EDP                           0x6f900
#define EDP_PSR2_CTL(tran)                      _MMIO_TRANS2(tran, _PSR2_CTL_A)
#define   EDP_PSR2_ENABLE                       (1 << 31)
#define   EDP_SU_TRACK_ENABLE                   (1 << 30) /* up to adl-p */
#define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2        (0 << 28)
#define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_3        (1 << 28)
#define   EDP_Y_COORDINATE_ENABLE               REG_BIT(25) /* display 10, 11 and 12 */
#define   EDP_PSR2_SU_SDP_SCANLINE              REG_BIT(25) /* display 13+ */
#define   EDP_MAX_SU_DISABLE_TIME(t)            ((t) << 20)
#define   EDP_MAX_SU_DISABLE_TIME_MASK          (0x1f << 20)
#define   EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES     8
#define   EDP_PSR2_IO_BUFFER_WAKE(lines)        ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
#define   EDP_PSR2_IO_BUFFER_WAKE_MASK          (3 << 13)
#define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5
#define   TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT     13
#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)    (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)
#define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK      (7 << 13)
#define   EDP_PSR2_FAST_WAKE_MAX_LINES          8
#define   EDP_PSR2_FAST_WAKE(lines)             ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
#define   EDP_PSR2_FAST_WAKE_MASK               (3 << 11)
#define   TGL_EDP_PSR2_FAST_WAKE_MIN_LINES      5
#define   TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT      10
#define   TGL_EDP_PSR2_FAST_WAKE(lines)         (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)
#define   TGL_EDP_PSR2_FAST_WAKE_MASK           (7 << 10)
#define   EDP_PSR2_TP2_TIME_500us               (0 << 8)
#define   EDP_PSR2_TP2_TIME_100us               (1 << 8)
#define   EDP_PSR2_TP2_TIME_2500us              (2 << 8)
#define   EDP_PSR2_TP2_TIME_50us                (3 << 8)
#define   EDP_PSR2_TP2_TIME_MASK                (3 << 8)
#define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT        4
#define   EDP_PSR2_FRAME_BEFORE_SU_MASK         (0xf << 4)
#define   EDP_PSR2_FRAME_BEFORE_SU(a)           ((a) << 4)
#define   EDP_PSR2_IDLE_FRAME_MASK              0xf
#define   EDP_PSR2_IDLE_FRAME_SHIFT             0

#define _PSR_EVENT_TRANS_A                      0x60848
#define _PSR_EVENT_TRANS_B                      0x61848
#define _PSR_EVENT_TRANS_C                      0x62848
#define _PSR_EVENT_TRANS_D                      0x63848
#define _PSR_EVENT_TRANS_EDP                    0x6f848
#define PSR_EVENT(tran)                         _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)
#define  PSR_EVENT_PSR2_WD_TIMER_EXPIRE         (1 << 17)
#define  PSR_EVENT_PSR2_DISABLED                (1 << 16)
#define  PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN       (1 << 15)
#define  PSR_EVENT_SU_CRC_FIFO_UNDERRUN         (1 << 14)
#define  PSR_EVENT_GRAPHICS_RESET               (1 << 12)
#define  PSR_EVENT_PCH_INTERRUPT                (1 << 11)
#define  PSR_EVENT_MEMORY_UP                    (1 << 10)
#define  PSR_EVENT_FRONT_BUFFER_MODIFY          (1 << 9)
#define  PSR_EVENT_WD_TIMER_EXPIRE              (1 << 8)
#define  PSR_EVENT_PIPE_REGISTERS_UPDATE        (1 << 6)
#define  PSR_EVENT_REGISTER_UPDATE              (1 << 5) /* Reserved in ICL+ */
#define  PSR_EVENT_HDCP_ENABLE                  (1 << 4)
#define  PSR_EVENT_KVMR_SESSION_ENABLE          (1 << 3)
#define  PSR_EVENT_VBI_ENABLE                   (1 << 2)
#define  PSR_EVENT_LPSP_MODE_EXIT               (1 << 1)
#define  PSR_EVENT_PSR_DISABLE                  (1 << 0)

#define _PSR2_STATUS_A                          0x60940
#define _PSR2_STATUS_EDP                        0x6f940
#define EDP_PSR2_STATUS(tran)                   _MMIO_TRANS2(tran, _PSR2_STATUS_A)
#define EDP_PSR2_STATUS_STATE_MASK              REG_GENMASK(31, 28)
#define EDP_PSR2_STATUS_STATE_DEEP_SLEEP        REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)

#define _PSR2_SU_STATUS_A               0x60914
#define _PSR2_SU_STATUS_EDP             0x6f914
#define _PSR2_SU_STATUS(tran, index)    _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4)
#define PSR2_SU_STATUS(tran, frame)     (_PSR2_SU_STATUS(tran, (frame) / 3))
#define PSR2_SU_STATUS_SHIFT(frame)     (((frame) % 3) * 10)
#define PSR2_SU_STATUS_MASK(frame)      (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
#define PSR2_SU_STATUS_FRAMES           8

#define _PSR2_MAN_TRK_CTL_A                                     0x60910
#define _PSR2_MAN_TRK_CTL_EDP                                   0x6f910
#define PSR2_MAN_TRK_CTL(tran)                                  _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
#define  PSR2_MAN_TRK_CTL_ENABLE                                REG_BIT(31)
#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK             REG_GENMASK(30, 21)
#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)             REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
#define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK               REG_GENMASK(20, 11)
#define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)               REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
#define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME                  REG_BIT(3)
#define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME               REG_BIT(2)
#define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE               REG_BIT(1)
#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK        REG_GENMASK(28, 16)
#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)        REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK          REG_GENMASK(12, 0)
#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)          REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
#define  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE          REG_BIT(31)
#define  ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME             REG_BIT(14)
#define  ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME          REG_BIT(13)

/* Icelake DSC Rate Control Range Parameter Registers */
#define DSCA_RC_RANGE_PARAMETERS_0              _MMIO(0x6B240)
#define DSCA_RC_RANGE_PARAMETERS_0_UDW          _MMIO(0x6B240 + 4)
#define DSCC_RC_RANGE_PARAMETERS_0              _MMIO(0x6BA40)
#define DSCC_RC_RANGE_PARAMETERS_0_UDW          _MMIO(0x6BA40 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB      (0x78208)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB  (0x78208 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB      (0x78308)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB  (0x78308 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC      (0x78408)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC  (0x78408 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC      (0x78508)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC  (0x78508 + 4)
#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
#define RC_BPG_OFFSET_SHIFT                     10
#define RC_MAX_QP_SHIFT                         5
#define RC_MIN_QP_SHIFT                         0

#define DSCA_RC_RANGE_PARAMETERS_1              _MMIO(0x6B248)
#define DSCA_RC_RANGE_PARAMETERS_1_UDW          _MMIO(0x6B248 + 4)
#define DSCC_RC_RANGE_PARAMETERS_1              _MMIO(0x6BA48)
#define DSCC_RC_RANGE_PARAMETERS_1_UDW          _MMIO(0x6BA48 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB      (0x78210)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB  (0x78210 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB      (0x78310)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB  (0x78310 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC      (0x78410)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC  (0x78410 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC      (0x78510)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC  (0x78510 + 4)
#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)

#define DSCA_RC_RANGE_PARAMETERS_2              _MMIO(0x6B250)
#define DSCA_RC_RANGE_PARAMETERS_2_UDW          _MMIO(0x6B250 + 4)
#define DSCC_RC_RANGE_PARAMETERS_2              _MMIO(0x6BA50)
#define DSCC_RC_RANGE_PARAMETERS_2_UDW          _MMIO(0x6BA50 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB      (0x78218)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB  (0x78218 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB      (0x78318)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB  (0x78318 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC      (0x78418)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC  (0x78418 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC      (0x78518)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC  (0x78518 + 4)
#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)

#define DSCA_RC_RANGE_PARAMETERS_3              _MMIO(0x6B258)
#define DSCA_RC_RANGE_PARAMETERS_3_UDW          _MMIO(0x6B258 + 4)
#define DSCC_RC_RANGE_PARAMETERS_3              _MMIO(0x6BA58)
#define DSCC_RC_RANGE_PARAMETERS_3_UDW          _MMIO(0x6BA58 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB      (0x78220)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB  (0x78220 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB      (0x78320)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB  (0x78320 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC      (0x78420)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC  (0x78420 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC      (0x78520)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC  (0x78520 + 4)
#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
                                                        _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
                                                        _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)

/* VGA port control */
#define ADPA                    _MMIO(0x61100)
#define PCH_ADPA                _MMIO(0xe1100)
#define VLV_ADPA                _MMIO(VLV_DISPLAY_BASE + 0x61100)

#define   ADPA_DAC_ENABLE       (1 << 31)
#define   ADPA_DAC_DISABLE      0
#define   ADPA_PIPE_SEL_SHIFT           30
#define   ADPA_PIPE_SEL_MASK            (1 << 30)
#define   ADPA_PIPE_SEL(pipe)           ((pipe) << 30)
#define   ADPA_PIPE_SEL_SHIFT_CPT       29
#define   ADPA_PIPE_SEL_MASK_CPT        (3 << 29)
#define   ADPA_PIPE_SEL_CPT(pipe)       ((pipe) << 29)
#define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
#define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0 << 24)
#define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3 << 24)
#define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
#define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2 << 24)
#define   ADPA_CRT_HOTPLUG_ENABLE        (1 << 23)
#define   ADPA_CRT_HOTPLUG_PERIOD_64     (0 << 22)
#define   ADPA_CRT_HOTPLUG_PERIOD_128    (1 << 22)
#define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0 << 21)
#define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1 << 21)
#define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0 << 20)
#define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1 << 20)
#define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0 << 18)
#define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1 << 18)
#define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2 << 18)
#define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3 << 18)
#define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0 << 17)
#define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1 << 17)
#define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
#define   ADPA_USE_VGA_HVPOLARITY (1 << 15)
#define   ADPA_SETS_HVPOLARITY  0
#define   ADPA_VSYNC_CNTL_DISABLE (1 << 10)
#define   ADPA_VSYNC_CNTL_ENABLE 0
#define   ADPA_HSYNC_CNTL_DISABLE (1 << 11)
#define   ADPA_HSYNC_CNTL_ENABLE 0
#define   ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
#define   ADPA_VSYNC_ACTIVE_LOW 0
#define   ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
#define   ADPA_HSYNC_ACTIVE_LOW 0
#define   ADPA_DPMS_MASK        (~(3 << 10))
#define   ADPA_DPMS_ON          (0 << 10)
#define   ADPA_DPMS_SUSPEND     (1 << 10)
#define   ADPA_DPMS_STANDBY     (2 << 10)
#define   ADPA_DPMS_OFF         (3 << 10)


/* Hotplug control (945+ only) */
#define PORT_HOTPLUG_EN         _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
#define   PORTB_HOTPLUG_INT_EN                  (1 << 29)
#define   PORTC_HOTPLUG_INT_EN                  (1 << 28)
#define   PORTD_HOTPLUG_INT_EN                  (1 << 27)
#define   SDVOB_HOTPLUG_INT_EN                  (1 << 26)
#define   SDVOC_HOTPLUG_INT_EN                  (1 << 25)
#define   TV_HOTPLUG_INT_EN                     (1 << 18)
#define   CRT_HOTPLUG_INT_EN                    (1 << 9)
#define HOTPLUG_INT_EN_MASK                     (PORTB_HOTPLUG_INT_EN | \
                                                 PORTC_HOTPLUG_INT_EN | \
                                                 PORTD_HOTPLUG_INT_EN | \
                                                 SDVOC_HOTPLUG_INT_EN | \
                                                 SDVOB_HOTPLUG_INT_EN | \
                                                 CRT_HOTPLUG_INT_EN)
#define   CRT_HOTPLUG_FORCE_DETECT              (1 << 3)
#define CRT_HOTPLUG_ACTIVATION_PERIOD_32        (0 << 8)
/* must use period 64 on GM45 according to docs */
#define CRT_HOTPLUG_ACTIVATION_PERIOD_64        (1 << 8)
#define CRT_HOTPLUG_DAC_ON_TIME_2M              (0 << 7)
#define CRT_HOTPLUG_DAC_ON_TIME_4M              (1 << 7)
#define CRT_HOTPLUG_VOLTAGE_COMPARE_40          (0 << 5)
#define CRT_HOTPLUG_VOLTAGE_COMPARE_50          (1 << 5)
#define CRT_HOTPLUG_VOLTAGE_COMPARE_60          (2 << 5)
#define CRT_HOTPLUG_VOLTAGE_COMPARE_70          (3 << 5)
#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK        (3 << 5)
#define CRT_HOTPLUG_DETECT_DELAY_1G             (0 << 4)
#define CRT_HOTPLUG_DETECT_DELAY_2G             (1 << 4)
#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV        (0 << 2)
#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV        (1 << 2)

#define PORT_HOTPLUG_STAT       _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
/*
 * HDMI/DP bits are g4x+
 *
 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
 * Please check the detailed lore in the commit message for for experimental
 * evidence.
 */
/* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
#define   PORTD_HOTPLUG_LIVE_STATUS_GM45        (1 << 29)
#define   PORTC_HOTPLUG_LIVE_STATUS_GM45        (1 << 28)
#define   PORTB_HOTPLUG_LIVE_STATUS_GM45        (1 << 27)
/* G4X/VLV/CHV DP/HDMI bits again match Bspec */
#define   PORTD_HOTPLUG_LIVE_STATUS_G4X         (1 << 27)
#define   PORTC_HOTPLUG_LIVE_STATUS_G4X         (1 << 28)
#define   PORTB_HOTPLUG_LIVE_STATUS_G4X         (1 << 29)
#define   PORTD_HOTPLUG_INT_STATUS              (3 << 21)
#define   PORTD_HOTPLUG_INT_LONG_PULSE          (2 << 21)
#define   PORTD_HOTPLUG_INT_SHORT_PULSE         (1 << 21)
#define   PORTC_HOTPLUG_INT_STATUS              (3 << 19)
#define   PORTC_HOTPLUG_INT_LONG_PULSE          (2 << 19)
#define   PORTC_HOTPLUG_INT_SHORT_PULSE         (1 << 19)
#define   PORTB_HOTPLUG_INT_STATUS              (3 << 17)
#define   PORTB_HOTPLUG_INT_LONG_PULSE          (2 << 17)
#define   PORTB_HOTPLUG_INT_SHORT_PLUSE         (1 << 17)
/* CRT/TV common between gen3+ */
#define   CRT_HOTPLUG_INT_STATUS                (1 << 11)
#define   TV_HOTPLUG_INT_STATUS                 (1 << 10)
#define   CRT_HOTPLUG_MONITOR_MASK              (3 << 8)
#define   CRT_HOTPLUG_MONITOR_COLOR             (3 << 8)
#define   CRT_HOTPLUG_MONITOR_MONO              (2 << 8)
#define   CRT_HOTPLUG_MONITOR_NONE              (0 << 8)
#define   DP_AUX_CHANNEL_D_INT_STATUS_G4X       (1 << 6)
#define   DP_AUX_CHANNEL_C_INT_STATUS_G4X       (1 << 5)
#define   DP_AUX_CHANNEL_B_INT_STATUS_G4X       (1 << 4)
#define   DP_AUX_CHANNEL_MASK_INT_STATUS_G4X    (7 << 4)

/* SDVO is different across gen3/4 */
#define   SDVOC_HOTPLUG_INT_STATUS_G4X          (1 << 3)
#define   SDVOB_HOTPLUG_INT_STATUS_G4X          (1 << 2)
/*
 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
 * since reality corrobates that they're the same as on gen3. But keep these
 * bits here (and the comment!) to help any other lost wanderers back onto the
 * right tracks.
 */
#define   SDVOC_HOTPLUG_INT_STATUS_I965         (3 << 4)
#define   SDVOB_HOTPLUG_INT_STATUS_I965         (3 << 2)
#define   SDVOC_HOTPLUG_INT_STATUS_I915         (1 << 7)
#define   SDVOB_HOTPLUG_INT_STATUS_I915         (1 << 6)
#define   HOTPLUG_INT_STATUS_G4X                (CRT_HOTPLUG_INT_STATUS | \
                                                 SDVOB_HOTPLUG_INT_STATUS_G4X | \
                                                 SDVOC_HOTPLUG_INT_STATUS_G4X | \
                                                 PORTB_HOTPLUG_INT_STATUS | \
                                                 PORTC_HOTPLUG_INT_STATUS | \
                                                 PORTD_HOTPLUG_INT_STATUS)

#define HOTPLUG_INT_STATUS_I915                 (CRT_HOTPLUG_INT_STATUS | \
                                                 SDVOB_HOTPLUG_INT_STATUS_I915 | \
                                                 SDVOC_HOTPLUG_INT_STATUS_I915 | \
                                                 PORTB_HOTPLUG_INT_STATUS | \
                                                 PORTC_HOTPLUG_INT_STATUS | \
                                                 PORTD_HOTPLUG_INT_STATUS)

/* SDVO and HDMI port control.
 * The same register may be used for SDVO or HDMI */
#define _GEN3_SDVOB     0x61140
#define _GEN3_SDVOC     0x61160
#define GEN3_SDVOB      _MMIO(_GEN3_SDVOB)
#define GEN3_SDVOC      _MMIO(_GEN3_SDVOC)
#define GEN4_HDMIB      GEN3_SDVOB
#define GEN4_HDMIC      GEN3_SDVOC
#define VLV_HDMIB       _MMIO(VLV_DISPLAY_BASE + 0x61140)
#define VLV_HDMIC       _MMIO(VLV_DISPLAY_BASE + 0x61160)
#define CHV_HDMID       _MMIO(VLV_DISPLAY_BASE + 0x6116C)
#define PCH_SDVOB       _MMIO(0xe1140)
#define PCH_HDMIB       PCH_SDVOB
#define PCH_HDMIC       _MMIO(0xe1150)
#define PCH_HDMID       _MMIO(0xe1160)

#define PORT_DFT_I9XX                           _MMIO(0x61150)
#define   DC_BALANCE_RESET                      (1 << 25)
#define PORT_DFT2_G4X           _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
#define   DC_BALANCE_RESET_VLV                  (1 << 31)
#define   PIPE_SCRAMBLE_RESET_MASK              ((1 << 14) | (0x3 << 0))
#define   PIPE_C_SCRAMBLE_RESET                 REG_BIT(14) /* chv */
#define   PIPE_B_SCRAMBLE_RESET                 REG_BIT(1)
#define   PIPE_A_SCRAMBLE_RESET                 REG_BIT(0)

/* Gen 3 SDVO bits: */
#define   SDVO_ENABLE                           (1 << 31)
#define   SDVO_PIPE_SEL_SHIFT                   30
#define   SDVO_PIPE_SEL_MASK                    (1 << 30)
#define   SDVO_PIPE_SEL(pipe)                   ((pipe) << 30)
#define   SDVO_STALL_SELECT                     (1 << 29)
#define   SDVO_INTERRUPT_ENABLE                 (1 << 26)
/*
 * 915G/GM SDVO pixel multiplier.
 * Programmed value is multiplier - 1, up to 5x.
 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
 */
#define   SDVO_PORT_MULTIPLY_MASK               (7 << 23)
#define   SDVO_PORT_MULTIPLY_SHIFT              23
#define   SDVO_PHASE_SELECT_MASK                (15 << 19)
#define   SDVO_PHASE_SELECT_DEFAULT             (6 << 19)
#define   SDVO_CLOCK_OUTPUT_INVERT              (1 << 18)
#define   SDVOC_GANG_MODE                       (1 << 16) /* Port C only */
#define   SDVO_BORDER_ENABLE                    (1 << 7) /* SDVO only */
#define   SDVOB_PCIE_CONCURRENCY                (1 << 3) /* Port B only */
#define   SDVO_DETECTED                         (1 << 2)
/* Bits to be preserved when writing */
#define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
                               SDVO_INTERRUPT_ENABLE)
#define   SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)

/* Gen 4 SDVO/HDMI bits: */
#define   SDVO_COLOR_FORMAT_8bpc                (0 << 26)
#define   SDVO_COLOR_FORMAT_MASK                (7 << 26)
#define   SDVO_ENCODING_SDVO                    (0 << 10)
#define   SDVO_ENCODING_HDMI                    (2 << 10)
#define   HDMI_MODE_SELECT_HDMI                 (1 << 9) /* HDMI only */
#define   HDMI_MODE_SELECT_DVI                  (0 << 9) /* HDMI only */
#define   HDMI_COLOR_RANGE_16_235               (1 << 8) /* HDMI only */
#define   HDMI_AUDIO_ENABLE                     (1 << 6) /* HDMI only */
/* VSYNC/HSYNC bits new with 965, default is to be set */
#define   SDVO_VSYNC_ACTIVE_HIGH                (1 << 4)
#define   SDVO_HSYNC_ACTIVE_HIGH                (1 << 3)

/* Gen 5 (IBX) SDVO/HDMI bits: */
#define   HDMI_COLOR_FORMAT_12bpc               (3 << 26) /* HDMI only */
#define   SDVOB_HOTPLUG_ENABLE                  (1 << 23) /* SDVO only */

/* Gen 6 (CPT) SDVO/HDMI bits: */
#define   SDVO_PIPE_SEL_SHIFT_CPT               29
#define   SDVO_PIPE_SEL_MASK_CPT                (3 << 29)
#define   SDVO_PIPE_SEL_CPT(pipe)               ((pipe) << 29)

/* CHV SDVO/HDMI bits: */
#define   SDVO_PIPE_SEL_SHIFT_CHV               24
#define   SDVO_PIPE_SEL_MASK_CHV                (3 << 24)
#define   SDVO_PIPE_SEL_CHV(pipe)               ((pipe) << 24)


/* DVO port control */
#define _DVOA                   0x61120
#define DVOA                    _MMIO(_DVOA)
#define _DVOB                   0x61140
#define DVOB                    _MMIO(_DVOB)
#define _DVOC                   0x61160
#define DVOC                    _MMIO(_DVOC)
#define   DVO_ENABLE                    (1 << 31)
#define   DVO_PIPE_SEL_SHIFT            30
#define   DVO_PIPE_SEL_MASK             (1 << 30)
#define   DVO_PIPE_SEL(pipe)            ((pipe) << 30)
#define   DVO_PIPE_STALL_UNUSED         (0 << 28)
#define   DVO_PIPE_STALL                (1 << 28)
#define   DVO_PIPE_STALL_TV             (2 << 28)
#define   DVO_PIPE_STALL_MASK           (3 << 28)
#define   DVO_USE_VGA_SYNC              (1 << 15)
#define   DVO_DATA_ORDER_I740           (0 << 14)
#define   DVO_DATA_ORDER_FP             (1 << 14)
#define   DVO_VSYNC_DISABLE             (1 << 11)
#define   DVO_HSYNC_DISABLE             (1 << 10)
#define   DVO_VSYNC_TRISTATE            (1 << 9)
#define   DVO_HSYNC_TRISTATE            (1 << 8)
#define   DVO_BORDER_ENABLE             (1 << 7)
#define   DVO_DATA_ORDER_GBRG           (1 << 6)
#define   DVO_DATA_ORDER_RGGB           (0 << 6)
#define   DVO_DATA_ORDER_GBRG_ERRATA    (0 << 6)
#define   DVO_DATA_ORDER_RGGB_ERRATA    (1 << 6)
#define   DVO_VSYNC_ACTIVE_HIGH         (1 << 4)
#define   DVO_HSYNC_ACTIVE_HIGH         (1 << 3)
#define   DVO_BLANK_ACTIVE_HIGH         (1 << 2)
#define   DVO_OUTPUT_CSTATE_PIXELS      (1 << 1)        /* SDG only */
#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0)        /* SDG only */
#define   DVO_PRESERVE_MASK             (0x7 << 24)
#define DVOA_SRCDIM             _MMIO(0x61124)
#define DVOB_SRCDIM             _MMIO(0x61144)
#define DVOC_SRCDIM             _MMIO(0x61164)
#define   DVO_SRCDIM_HORIZONTAL_SHIFT   12
#define   DVO_SRCDIM_VERTICAL_SHIFT     0

/* LVDS port control */
#define LVDS                    _MMIO(0x61180)
/*
 * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
 * the DPLL semantics change when the LVDS is assigned to that pipe.
 */
#define   LVDS_PORT_EN                  (1 << 31)
/* Selects pipe B for LVDS data.  Must be set on pre-965. */
#define   LVDS_PIPE_SEL_SHIFT           30
#define   LVDS_PIPE_SEL_MASK            (1 << 30)
#define   LVDS_PIPE_SEL(pipe)           ((pipe) << 30)
#define   LVDS_PIPE_SEL_SHIFT_CPT       29
#define   LVDS_PIPE_SEL_MASK_CPT        (3 << 29)
#define   LVDS_PIPE_SEL_CPT(pipe)       ((pipe) << 29)
/* LVDS dithering flag on 965/g4x platform */
#define   LVDS_ENABLE_DITHER            (1 << 25)
/* LVDS sync polarity flags. Set to invert (i.e. negative) */
#define   LVDS_VSYNC_POLARITY           (1 << 21)
#define   LVDS_HSYNC_POLARITY           (1 << 20)

/* Enable border for unscaled (or aspect-scaled) display */
#define   LVDS_BORDER_ENABLE            (1 << 15)
/*
 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
 * pixel.
 */
#define   LVDS_A0A2_CLKA_POWER_MASK     (3 << 8)
#define   LVDS_A0A2_CLKA_POWER_DOWN     (0 << 8)
#define   LVDS_A0A2_CLKA_POWER_UP       (3 << 8)
/*
 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
 * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
 * on.
 */
#define   LVDS_A3_POWER_MASK            (3 << 6)
#define   LVDS_A3_POWER_DOWN            (0 << 6)
#define   LVDS_A3_POWER_UP              (3 << 6)
/*
 * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
 * is set.
 */
#define   LVDS_CLKB_POWER_MASK          (3 << 4)
#define   LVDS_CLKB_POWER_DOWN          (0 << 4)
#define   LVDS_CLKB_POWER_UP            (3 << 4)
/*
 * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
 * setting for whether we are in dual-channel mode.  The B3 pair will
 * additionally only be powered up when LVDS_A3_POWER_UP is set.
 */
#define   LVDS_B0B3_POWER_MASK          (3 << 2)
#define   LVDS_B0B3_POWER_DOWN          (0 << 2)
#define   LVDS_B0B3_POWER_UP            (3 << 2)

/* Video Data Island Packet control */
#define VIDEO_DIP_DATA          _MMIO(0x61178)
/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
 * of the infoframe structure specified by CEA-861. */
#define   VIDEO_DIP_DATA_SIZE   32
#define   VIDEO_DIP_GMP_DATA_SIZE       36
#define   VIDEO_DIP_VSC_DATA_SIZE       36
#define   VIDEO_DIP_PPS_DATA_SIZE       132
#define VIDEO_DIP_CTL           _MMIO(0x61170)
/* Pre HSW: */
#define   VIDEO_DIP_ENABLE              (1 << 31)
#define   VIDEO_DIP_PORT(port)          ((port) << 29)
#define   VIDEO_DIP_PORT_MASK           (3 << 29)
#define   VIDEO_DIP_ENABLE_GCP          (1 << 25) /* ilk+ */
#define   VIDEO_DIP_ENABLE_AVI          (1 << 21)
#define   VIDEO_DIP_ENABLE_VENDOR       (2 << 21)
#define   VIDEO_DIP_ENABLE_GAMUT        (4 << 21) /* ilk+ */
#define   VIDEO_DIP_ENABLE_SPD          (8 << 21)
#define   VIDEO_DIP_SELECT_AVI          (0 << 19)
#define   VIDEO_DIP_SELECT_VENDOR       (1 << 19)
#define   VIDEO_DIP_SELECT_GAMUT        (2 << 19)
#define   VIDEO_DIP_SELECT_SPD          (3 << 19)
#define   VIDEO_DIP_SELECT_MASK         (3 << 19)
#define   VIDEO_DIP_FREQ_ONCE           (0 << 16)
#define   VIDEO_DIP_FREQ_VSYNC          (1 << 16)
#define   VIDEO_DIP_FREQ_2VSYNC         (2 << 16)
#define   VIDEO_DIP_FREQ_MASK           (3 << 16)
/* HSW and later: */
#define   VIDEO_DIP_ENABLE_DRM_GLK      (1 << 28)
#define   PSR_VSC_BIT_7_SET             (1 << 27)
#define   VSC_SELECT_MASK               (0x3 << 25)
#define   VSC_SELECT_SHIFT              25
#define   VSC_DIP_HW_HEA_DATA           (0 << 25)
#define   VSC_DIP_HW_HEA_SW_DATA        (1 << 25)
#define   VSC_DIP_HW_DATA_SW_HEA        (2 << 25)
#define   VSC_DIP_SW_HEA_DATA           (3 << 25)
#define   VDIP_ENABLE_PPS               (1 << 24)
#define   VIDEO_DIP_ENABLE_VSC_HSW      (1 << 20)
#define   VIDEO_DIP_ENABLE_GCP_HSW      (1 << 16)
#define   VIDEO_DIP_ENABLE_AVI_HSW      (1 << 12)
#define   VIDEO_DIP_ENABLE_VS_HSW       (1 << 8)
#define   VIDEO_DIP_ENABLE_GMP_HSW      (1 << 4)
#define   VIDEO_DIP_ENABLE_SPD_HSW      (1 << 0)

/* Panel power sequencing */
#define PPS_BASE                        0x61200
#define VLV_PPS_BASE                    (VLV_DISPLAY_BASE + PPS_BASE)
#define PCH_PPS_BASE                    0xC7200

#define _MMIO_PPS(pps_idx, reg)         _MMIO(dev_priv->pps_mmio_base - \
                                              PPS_BASE + (reg) +        \
                                              (pps_idx) * 0x100)

#define _PP_STATUS                      0x61200
#define PP_STATUS(pps_idx)              _MMIO_PPS(pps_idx, _PP_STATUS)
#define   PP_ON                         REG_BIT(31)
/*
 * Indicates that all dependencies of the panel are on:
 *
 * - PLL enabled
 * - pipe enabled
 * - LVDS/DVOB/DVOC on
 */
#define   PP_READY                      REG_BIT(30)
#define   PP_SEQUENCE_MASK              REG_GENMASK(29, 28)
#define   PP_SEQUENCE_NONE              REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
#define   PP_SEQUENCE_POWER_UP          REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
#define   PP_SEQUENCE_POWER_DOWN        REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
#define   PP_CYCLE_DELAY_ACTIVE         REG_BIT(27)
#define   PP_SEQUENCE_STATE_MASK        REG_GENMASK(3, 0)
#define   PP_SEQUENCE_STATE_OFF_IDLE    REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
#define   PP_SEQUENCE_STATE_OFF_S0_1    REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
#define   PP_SEQUENCE_STATE_OFF_S0_2    REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
#define   PP_SEQUENCE_STATE_OFF_S0_3    REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
#define   PP_SEQUENCE_STATE_ON_IDLE     REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
#define   PP_SEQUENCE_STATE_ON_S1_1     REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
#define   PP_SEQUENCE_STATE_ON_S1_2     REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
#define   PP_SEQUENCE_STATE_ON_S1_3     REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
#define   PP_SEQUENCE_STATE_RESET       REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)

#define _PP_CONTROL                     0x61204
#define PP_CONTROL(pps_idx)             _MMIO_PPS(pps_idx, _PP_CONTROL)
#define  PANEL_UNLOCK_MASK              REG_GENMASK(31, 16)
#define  PANEL_UNLOCK_REGS              REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
#define  BXT_POWER_CYCLE_DELAY_MASK     REG_GENMASK(8, 4)
#define  EDP_FORCE_VDD                  REG_BIT(3)
#define  EDP_BLC_ENABLE                 REG_BIT(2)
#define  PANEL_POWER_RESET              REG_BIT(1)
#define  PANEL_POWER_ON                 REG_BIT(0)

#define _PP_ON_DELAYS                   0x61208
#define PP_ON_DELAYS(pps_idx)           _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
#define  PANEL_PORT_SELECT_MASK         REG_GENMASK(31, 30)
#define  PANEL_PORT_SELECT_LVDS         REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
#define  PANEL_PORT_SELECT_DPA          REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
#define  PANEL_PORT_SELECT_DPC          REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
#define  PANEL_PORT_SELECT_DPD          REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
#define  PANEL_PORT_SELECT_VLV(port)    REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
#define  PANEL_POWER_UP_DELAY_MASK      REG_GENMASK(28, 16)
#define  PANEL_LIGHT_ON_DELAY_MASK      REG_GENMASK(12, 0)

#define _PP_OFF_DELAYS                  0x6120C
#define PP_OFF_DELAYS(pps_idx)          _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
#define  PANEL_POWER_DOWN_DELAY_MASK    REG_GENMASK(28, 16)
#define  PANEL_LIGHT_OFF_DELAY_MASK     REG_GENMASK(12, 0)

#define _PP_DIVISOR                     0x61210
#define PP_DIVISOR(pps_idx)             _MMIO_PPS(pps_idx, _PP_DIVISOR)
#define  PP_REFERENCE_DIVIDER_MASK      REG_GENMASK(31, 8)
#define  PANEL_POWER_CYCLE_DELAY_MASK   REG_GENMASK(4, 0)

/* Panel fitting */
#define PFIT_CONTROL    _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
#define   PFIT_ENABLE           (1 << 31)
#define   PFIT_PIPE_MASK        (3 << 29)
#define   PFIT_PIPE_SHIFT       29
#define   PFIT_PIPE(pipe)       ((pipe) << 29)
#define   VERT_INTERP_DISABLE   (0 << 10)
#define   VERT_INTERP_BILINEAR  (1 << 10)
#define   VERT_INTERP_MASK      (3 << 10)
#define   VERT_AUTO_SCALE       (1 << 9)
#define   HORIZ_INTERP_DISABLE  (0 << 6)
#define   HORIZ_INTERP_BILINEAR (1 << 6)
#define   HORIZ_INTERP_MASK     (3 << 6)
#define   HORIZ_AUTO_SCALE      (1 << 5)
#define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
#define   PFIT_FILTER_FUZZY     (0 << 24)
#define   PFIT_SCALING_AUTO     (0 << 26)
#define   PFIT_SCALING_PROGRAMMED (1 << 26)
#define   PFIT_SCALING_PILLAR   (2 << 26)
#define   PFIT_SCALING_LETTER   (3 << 26)
#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
/* Pre-965 */
#define         PFIT_VERT_SCALE_SHIFT           20
#define         PFIT_VERT_SCALE_MASK            0xfff00000
#define         PFIT_HORIZ_SCALE_SHIFT          4
#define         PFIT_HORIZ_SCALE_MASK           0x0000fff0
/* 965+ */
#define         PFIT_VERT_SCALE_SHIFT_965       16
#define         PFIT_VERT_SCALE_MASK_965        0x1fff0000
#define         PFIT_HORIZ_SCALE_SHIFT_965      0
#define         PFIT_HORIZ_SCALE_MASK_965       0x00001fff

#define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)

#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
                                         _VLV_BLC_PWM_CTL2_B)

#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
                                        _VLV_BLC_PWM_CTL_B)

#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
                                         _VLV_BLC_HIST_CTL_B)

/* Backlight control */
#define BLC_PWM_CTL2    _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
#define   BLM_PWM_ENABLE                (1 << 31)
#define   BLM_COMBINATION_MODE          (1 << 30) /* gen4 only */
#define   BLM_PIPE_SELECT               (1 << 29)
#define   BLM_PIPE_SELECT_IVB           (3 << 29)
#define   BLM_PIPE_A                    (0 << 29)
#define   BLM_PIPE_B                    (1 << 29)
#define   BLM_PIPE_C                    (2 << 29) /* ivb + */
#define   BLM_TRANSCODER_A              BLM_PIPE_A /* hsw */
#define   BLM_TRANSCODER_B              BLM_PIPE_B
#define   BLM_TRANSCODER_C              BLM_PIPE_C
#define   BLM_TRANSCODER_EDP            (3 << 29)
#define   BLM_PIPE(pipe)                ((pipe) << 29)
#define   BLM_POLARITY_I965             (1 << 28) /* gen4 only */
#define   BLM_PHASE_IN_INTERUPT_STATUS  (1 << 26)
#define   BLM_PHASE_IN_ENABLE           (1 << 25)
#define   BLM_PHASE_IN_INTERUPT_ENABL   (1 << 24)
#define   BLM_PHASE_IN_TIME_BASE_SHIFT  (16)
#define   BLM_PHASE_IN_TIME_BASE_MASK   (0xff << 16)
#define   BLM_PHASE_IN_COUNT_SHIFT      (8)
#define   BLM_PHASE_IN_COUNT_MASK       (0xff << 8)
#define   BLM_PHASE_IN_INCR_SHIFT       (0)
#define   BLM_PHASE_IN_INCR_MASK        (0xff << 0)
#define BLC_PWM_CTL     _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
/*
 * This is the most significant 15 bits of the number of backlight cycles in a
 * complete cycle of the modulated backlight control.
 *
 * The actual value is this field multiplied by two.
 */
#define   BACKLIGHT_MODULATION_FREQ_SHIFT       (17)
#define   BACKLIGHT_MODULATION_FREQ_MASK        (0x7fff << 17)
#define   BLM_LEGACY_MODE                       (1 << 16) /* gen2 only */
/*
 * This is the number of cycles out of the backlight modulation cycle for which
 * the backlight is on.
 *
 * This field must be no greater than the number of cycles in the complete
 * backlight modulation cycle.
 */
#define   BACKLIGHT_DUTY_CYCLE_SHIFT            (0)
#define   BACKLIGHT_DUTY_CYCLE_MASK             (0xffff)
#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV         (0xfffe)
#define   BLM_POLARITY_PNV                      (1 << 0) /* pnv only */

#define BLC_HIST_CTL    _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
#define  BLM_HISTOGRAM_ENABLE                   (1 << 31)

/* New registers for PCH-split platforms. Safe where new bits show up, the
 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
#define BLC_PWM_CPU_CTL2        _MMIO(0x48250)
#define BLC_PWM_CPU_CTL         _MMIO(0x48254)

#define HSW_BLC_PWM2_CTL        _MMIO(0x48350)

/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
#define BLC_PWM_PCH_CTL1        _MMIO(0xc8250)
#define   BLM_PCH_PWM_ENABLE                    (1 << 31)
#define   BLM_PCH_OVERRIDE_ENABLE               (1 << 30)
#define   BLM_PCH_POLARITY                      (1 << 29)
#define BLC_PWM_PCH_CTL2        _MMIO(0xc8254)

#define UTIL_PIN_CTL                    _MMIO(0x48400)
#define   UTIL_PIN_ENABLE               (1 << 31)
#define   UTIL_PIN_PIPE_MASK            (3 << 29)
#define   UTIL_PIN_PIPE(x)              ((x) << 29)
#define   UTIL_PIN_MODE_MASK            (0xf << 24)
#define   UTIL_PIN_MODE_DATA            (0 << 24)
#define   UTIL_PIN_MODE_PWM             (1 << 24)
#define   UTIL_PIN_MODE_VBLANK          (4 << 24)
#define   UTIL_PIN_MODE_VSYNC           (5 << 24)